On and Off-Chip Crosstalk Avoidance in VLSI Design:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
2010
|
| Schlagworte: | |
| Online-Zugang: | BTU01 FHI01 FHN01 FHR01 Volltext |
| Beschreibung: | On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design. This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book: Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster; Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based; Provides techniques to design extremely efficient CODECs for crosstalk cancellation; Provides crosstalk cancellation approaches for multi-valued busses; Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford |
| Beschreibung: | 1 Online-Ressource (XXIV, 240p. 600 illus., 300 illus. in color) |
| ISBN: | 9781441909473 |
| DOI: | 10.1007/978-1-4419-0947-3 |
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| 500 | |a On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design. This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book: Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster; Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based; Provides techniques to design extremely efficient CODECs for crosstalk cancellation; Provides crosstalk cancellation approaches for multi-valued busses; Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford | ||
| 505 | 0 | |a On-Chip Crosstalk and Avoidance -- of On-Chip Crosstalk Avoidance -- Preliminaries to On-chip Crosstalk -- Memoryless Crosstalk Avoidance Codes -- CODEC Designs for Memoryless Crosstalk Avoidance Codes -- Memory-based Crosstalk Avoidance Codes -- Multi-valued Logic Crosstalk Avoidance Codes -- Summary of On-Chip Crosstalk Avoidance -- Off-Chip Crosstalk and Avoidance -- to Off-Chip Crosstalk -- Package Construction and Electrical Modeling -- Preliminaries and Terminology -- Analytical Model for Off-Chip Bus Performance -- Optimal Bus Sizing -- Bus Expansion Encoder -- Bus Stuttering Encoder -- Impedance Compensation -- Future Trends and Applications -- Summary of Off-Chip Crosstalk Avoidance | |
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Computer aided design | |
| 650 | 4 | |a Systems engineering | |
| 650 | 4 | |a Circuits and Systems | |
| 650 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design | |
| 650 | 4 | |a Ingenieurwissenschaften | |
| 700 | 1 | |a LaMeres, Brock J. |e Sonstige |4 oth | |
| 700 | 1 | |a Khatri, Sunil P. |e Sonstige |4 oth | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druckausgabe |z 978-1-4419-0946-6 |
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Datensatz im Suchindex
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| any_adam_object | |
| author | Duan, Chunjie |
| author_facet | Duan, Chunjie |
| author_role | aut |
| author_sort | Duan, Chunjie |
| author_variant | c d cd |
| building | Verbundindex |
| bvnumber | BV041889574 |
| collection | ZDB-2-ENG |
| contents | On-Chip Crosstalk and Avoidance -- of On-Chip Crosstalk Avoidance -- Preliminaries to On-chip Crosstalk -- Memoryless Crosstalk Avoidance Codes -- CODEC Designs for Memoryless Crosstalk Avoidance Codes -- Memory-based Crosstalk Avoidance Codes -- Multi-valued Logic Crosstalk Avoidance Codes -- Summary of On-Chip Crosstalk Avoidance -- Off-Chip Crosstalk and Avoidance -- to Off-Chip Crosstalk -- Package Construction and Electrical Modeling -- Preliminaries and Terminology -- Analytical Model for Off-Chip Bus Performance -- Optimal Bus Sizing -- Bus Expansion Encoder -- Bus Stuttering Encoder -- Impedance Compensation -- Future Trends and Applications -- Summary of Off-Chip Crosstalk Avoidance |
| ctrlnum | (OCoLC)881658612 (DE-599)BVBBV041889574 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4419-0947-3 |
| format | Electronic eBook |
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| id | DE-604.BV041889574 |
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| indexdate | 2024-07-10T01:07:32Z |
| institution | BVB |
| isbn | 9781441909473 |
| language | English |
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| oclc_num | 881658612 |
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| physical | 1 Online-Ressource (XXIV, 240p. 600 illus., 300 illus. in color) |
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| publishDate | 2010 |
| publishDateSearch | 2010 |
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| publisher | Springer US |
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| spelling | Duan, Chunjie Verfasser aut On and Off-Chip Crosstalk Avoidance in VLSI Design by Chunjie Duan, Brock J. LaMeres, Sunil P. Khatri Boston, MA Springer US 2010 1 Online-Ressource (XXIV, 240p. 600 illus., 300 illus. in color) txt rdacontent c rdamedia cr rdacarrier On- and Off-Chip Crosstalk Avoidance in VLSI Design Chunjie Duan, Brock J. LaMeres and Sunil P. Khatri Deep Submicron (DSM) processes present many challenges to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is inter-wire crosstalk within on- and off-chip bus traces. Capacitive crosstalk in on-chip busses becomes significant with shrinking feature sizes of VLSI fabrication processes, while inductive cross-talk becomes a problem for busses with high off-chip data transfer rates. The presence of crosstalk greatly limits the speed and increases the power consumption of an IC design. This book presents approaches to avoid crosstalk in both on-chip as well as off-chip busses. These approaches allow the user to trade off the degree of crosstalk mitigation against the associated implementation overheads. In this way, a continuum of techniques is presented, which help improve the speed and power consumption of the bus interconnect. These techniques encode data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption. In particular, this book: Presents novel ways to combine chip and package design, reducing off-chip crosstalk so that VLSI systems can be designed to operate significantly faster; Provides a comprehensive set of bus crosstalk cancellation techniques, both memoryless and memory-based; Provides techniques to design extremely efficient CODECs for crosstalk cancellation; Provides crosstalk cancellation approaches for multi-valued busses; Offers a battery of approaches for a VLSI designer to use, depending on the amount of crosstalk their design can tolerate, and the amount of area overhead they can afford On-Chip Crosstalk and Avoidance -- of On-Chip Crosstalk Avoidance -- Preliminaries to On-chip Crosstalk -- Memoryless Crosstalk Avoidance Codes -- CODEC Designs for Memoryless Crosstalk Avoidance Codes -- Memory-based Crosstalk Avoidance Codes -- Multi-valued Logic Crosstalk Avoidance Codes -- Summary of On-Chip Crosstalk Avoidance -- Off-Chip Crosstalk and Avoidance -- to Off-Chip Crosstalk -- Package Construction and Electrical Modeling -- Preliminaries and Terminology -- Analytical Model for Off-Chip Bus Performance -- Optimal Bus Sizing -- Bus Expansion Encoder -- Bus Stuttering Encoder -- Impedance Compensation -- Future Trends and Applications -- Summary of Off-Chip Crosstalk Avoidance Engineering Computer aided design Systems engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Ingenieurwissenschaften LaMeres, Brock J. Sonstige oth Khatri, Sunil P. Sonstige oth Erscheint auch als Druckausgabe 978-1-4419-0946-6 https://doi.org/10.1007/978-1-4419-0947-3 Verlag Volltext |
| spellingShingle | Duan, Chunjie On and Off-Chip Crosstalk Avoidance in VLSI Design On-Chip Crosstalk and Avoidance -- of On-Chip Crosstalk Avoidance -- Preliminaries to On-chip Crosstalk -- Memoryless Crosstalk Avoidance Codes -- CODEC Designs for Memoryless Crosstalk Avoidance Codes -- Memory-based Crosstalk Avoidance Codes -- Multi-valued Logic Crosstalk Avoidance Codes -- Summary of On-Chip Crosstalk Avoidance -- Off-Chip Crosstalk and Avoidance -- to Off-Chip Crosstalk -- Package Construction and Electrical Modeling -- Preliminaries and Terminology -- Analytical Model for Off-Chip Bus Performance -- Optimal Bus Sizing -- Bus Expansion Encoder -- Bus Stuttering Encoder -- Impedance Compensation -- Future Trends and Applications -- Summary of Off-Chip Crosstalk Avoidance Engineering Computer aided design Systems engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Ingenieurwissenschaften |
| title | On and Off-Chip Crosstalk Avoidance in VLSI Design |
| title_auth | On and Off-Chip Crosstalk Avoidance in VLSI Design |
| title_exact_search | On and Off-Chip Crosstalk Avoidance in VLSI Design |
| title_full | On and Off-Chip Crosstalk Avoidance in VLSI Design by Chunjie Duan, Brock J. LaMeres, Sunil P. Khatri |
| title_fullStr | On and Off-Chip Crosstalk Avoidance in VLSI Design by Chunjie Duan, Brock J. LaMeres, Sunil P. Khatri |
| title_full_unstemmed | On and Off-Chip Crosstalk Avoidance in VLSI Design by Chunjie Duan, Brock J. LaMeres, Sunil P. Khatri |
| title_short | On and Off-Chip Crosstalk Avoidance in VLSI Design |
| title_sort | on and off chip crosstalk avoidance in vlsi design |
| topic | Engineering Computer aided design Systems engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Ingenieurwissenschaften |
| topic_facet | Engineering Computer aided design Systems engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Ingenieurwissenschaften |
| url | https://doi.org/10.1007/978-1-4419-0947-3 |
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