APA-Zitierstil (7. Ausg.)

Garg, R. (2010). Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations. Springer US. https://doi.org/10.1007/978-1-4419-0931-2

Chicago-Zitierstil (17. Ausg.)

Garg, Rajesh. Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations. Boston, MA: Springer US, 2010. https://doi.org/10.1007/978-1-4419-0931-2.

MLA-Zitierstil (9. Ausg.)

Garg, Rajesh. Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations. Springer US, 2010. https://doi.org/10.1007/978-1-4419-0931-2.