Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
2010
|
| Schlagworte: | |
| Online-Zugang: | BTU01 FHI01 FHN01 FHR01 Volltext |
| Beschreibung: | This book is motivated by the challenges faced in designing reliable integratedsystems using modern VLSI processes. The reliable operation of Integrated Circuits (ICs) has become increasingly difficult to achieve in the deep sub-micron (DSM) era. With continuously decreasing device feature sizes, combined with lower supply voltages and higher operating frequencies, the noise immunity of VLSI circuits is decreasing alarmingly. Thus, VLSI circuits are becoming more vulnerable to noise effects such as crosstalk, power supply variations and radiation-induced soft errors. This book describes the design of resilient VLSI circuits. It presents algorithms to analyze the detrimental effects of radiation particle strikes and processing variations on the electrical behavior of VLSI circuits, as well as circuit design techniques to mitigate the impact of these problems. Describes the state of the art in the areas of radiation tolerant circuit design and process variation tolerant circuit design; Presents analytical approaches to test efficiently the severity of electrical effects of radiation/process variations, as well as techniques to minimize the effects due to these two problems; Distills content oriented toward nuclear engineers into leading-edge algorithms and techniques that can be understood easily and applied by VLSI designers |
| Beschreibung: | 1 Online-Ressource |
| ISBN: | 9781441909312 |
| DOI: | 10.1007/978-1-4419-0931-2 |
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| 505 | 0 | |a Soft Errors -- Analytical Determination of Radiation-induced Pulse Width in Combinational Circuits -- Analytical Determination of the Radiation-induced Pulse Shape -- Modeling Dynamic Stability of SRAMs in the Presence of Radiation Particle Strikes -- 3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits -- Clamping Diode-based Radiation Tolerant Circuit Design Approach -- Split-output-based Radiation Tolerant Circuit Design Approach -- Process Variations -- Sensitizable Statistical Timing Analysis -- A Variation Tolerant Combinational Circuit Design Approach Using Parallel Gates -- Process Variation Tolerant Single-supply True Voltage Level Shifter -- Conclusions and Future Directions | |
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Datensatz im Suchindex
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| any_adam_object | |
| author | Garg, Rajesh |
| author_facet | Garg, Rajesh |
| author_role | aut |
| author_sort | Garg, Rajesh |
| author_variant | r g rg |
| building | Verbundindex |
| bvnumber | BV041889571 |
| collection | ZDB-2-ENG |
| contents | Soft Errors -- Analytical Determination of Radiation-induced Pulse Width in Combinational Circuits -- Analytical Determination of the Radiation-induced Pulse Shape -- Modeling Dynamic Stability of SRAMs in the Presence of Radiation Particle Strikes -- 3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits -- Clamping Diode-based Radiation Tolerant Circuit Design Approach -- Split-output-based Radiation Tolerant Circuit Design Approach -- Process Variations -- Sensitizable Statistical Timing Analysis -- A Variation Tolerant Combinational Circuit Design Approach Using Parallel Gates -- Process Variation Tolerant Single-supply True Voltage Level Shifter -- Conclusions and Future Directions |
| ctrlnum | (OCoLC)664677634 (DE-599)BVBBV041889571 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4419-0931-2 |
| format | Electronic eBook |
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| id | DE-604.BV041889571 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T01:07:32Z |
| institution | BVB |
| isbn | 9781441909312 |
| language | English |
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| physical | 1 Online-Ressource |
| psigel | ZDB-2-ENG |
| publishDate | 2010 |
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| publisher | Springer US |
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| spelling | Garg, Rajesh Verfasser aut Analysis and Design of Resilient VLSI Circuits Mitigating Soft Errors and Process Variations by Rajesh Garg, Sunil P. Khatri Boston, MA Springer US 2010 1 Online-Ressource txt rdacontent c rdamedia cr rdacarrier This book is motivated by the challenges faced in designing reliable integratedsystems using modern VLSI processes. The reliable operation of Integrated Circuits (ICs) has become increasingly difficult to achieve in the deep sub-micron (DSM) era. With continuously decreasing device feature sizes, combined with lower supply voltages and higher operating frequencies, the noise immunity of VLSI circuits is decreasing alarmingly. Thus, VLSI circuits are becoming more vulnerable to noise effects such as crosstalk, power supply variations and radiation-induced soft errors. This book describes the design of resilient VLSI circuits. It presents algorithms to analyze the detrimental effects of radiation particle strikes and processing variations on the electrical behavior of VLSI circuits, as well as circuit design techniques to mitigate the impact of these problems. Describes the state of the art in the areas of radiation tolerant circuit design and process variation tolerant circuit design; Presents analytical approaches to test efficiently the severity of electrical effects of radiation/process variations, as well as techniques to minimize the effects due to these two problems; Distills content oriented toward nuclear engineers into leading-edge algorithms and techniques that can be understood easily and applied by VLSI designers Soft Errors -- Analytical Determination of Radiation-induced Pulse Width in Combinational Circuits -- Analytical Determination of the Radiation-induced Pulse Shape -- Modeling Dynamic Stability of SRAMs in the Presence of Radiation Particle Strikes -- 3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits -- Clamping Diode-based Radiation Tolerant Circuit Design Approach -- Split-output-based Radiation Tolerant Circuit Design Approach -- Process Variations -- Sensitizable Statistical Timing Analysis -- A Variation Tolerant Combinational Circuit Design Approach Using Parallel Gates -- Process Variation Tolerant Single-supply True Voltage Level Shifter -- Conclusions and Future Directions Engineering Computer aided design Systems engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Ingenieurwissenschaften VLSI (DE-588)4117388-0 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 s VLSI (DE-588)4117388-0 s 1\p DE-604 Khatri, Sunil P. Sonstige oth Erscheint auch als Druckausgabe 978-1-4419-0930-5 https://doi.org/10.1007/978-1-4419-0931-2 Verlag Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Garg, Rajesh Analysis and Design of Resilient VLSI Circuits Mitigating Soft Errors and Process Variations Soft Errors -- Analytical Determination of Radiation-induced Pulse Width in Combinational Circuits -- Analytical Determination of the Radiation-induced Pulse Shape -- Modeling Dynamic Stability of SRAMs in the Presence of Radiation Particle Strikes -- 3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits -- Clamping Diode-based Radiation Tolerant Circuit Design Approach -- Split-output-based Radiation Tolerant Circuit Design Approach -- Process Variations -- Sensitizable Statistical Timing Analysis -- A Variation Tolerant Combinational Circuit Design Approach Using Parallel Gates -- Process Variation Tolerant Single-supply True Voltage Level Shifter -- Conclusions and Future Directions Engineering Computer aided design Systems engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Ingenieurwissenschaften VLSI (DE-588)4117388-0 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4027242-4 |
| title | Analysis and Design of Resilient VLSI Circuits Mitigating Soft Errors and Process Variations |
| title_auth | Analysis and Design of Resilient VLSI Circuits Mitigating Soft Errors and Process Variations |
| title_exact_search | Analysis and Design of Resilient VLSI Circuits Mitigating Soft Errors and Process Variations |
| title_full | Analysis and Design of Resilient VLSI Circuits Mitigating Soft Errors and Process Variations by Rajesh Garg, Sunil P. Khatri |
| title_fullStr | Analysis and Design of Resilient VLSI Circuits Mitigating Soft Errors and Process Variations by Rajesh Garg, Sunil P. Khatri |
| title_full_unstemmed | Analysis and Design of Resilient VLSI Circuits Mitigating Soft Errors and Process Variations by Rajesh Garg, Sunil P. Khatri |
| title_short | Analysis and Design of Resilient VLSI Circuits |
| title_sort | analysis and design of resilient vlsi circuits mitigating soft errors and process variations |
| title_sub | Mitigating Soft Errors and Process Variations |
| topic | Engineering Computer aided design Systems engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Ingenieurwissenschaften VLSI (DE-588)4117388-0 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| topic_facet | Engineering Computer aided design Systems engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Ingenieurwissenschaften VLSI Integrierte Schaltung |
| url | https://doi.org/10.1007/978-1-4419-0931-2 |
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