Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS): April 8 - 10, 2013, Karlovy Vary
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
Piscataway, N.J.
IEEE
2013
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| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | IEEE catalog number: CFP13DDE-PRT Includes bibliographical references and index |
| Beschreibung: | 300 S. zahlr. graph. Darst. |
| ISBN: | 9781467361330 |
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| adam_text | Table of Contents Keynote Talks Hardware-Software Co-Visualization: Developing Systems in the Holodeck 1 Drechsler, Rolf; Soeken, Mathias Approximate Computing for Energy-efficient Error-resilient Multimedia Systems 5 Roy, Kaushik Creating Options for 3D-SIC Testing 7 Marinissen, Erik Jan Embedded Tutorials Interpolation-Based Model Checking for Efficient Incremental Analysis of Software 8 Fedyukovich, Grigory; Hyvärinen, Antti E. J.; Sharygina, Natasha Cross-layer Resilient System Design 10 Tahoori, Mehdi Hardware Acceleration in Computer Networks 11 Kořenek, Jan Fault-based Attacks on Cryptographic Hardware 12 Polian, Ilia; Kreuzer, Martin Session 1A: Architecture Exploring Processor Parallelism: Estimation Methods and Optimization Strategies 18 Jordans, Roel; Corvino, Rosilde; Jozwiak, Lech; Corporaal, Henk On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggereď Real-Time Systems 24 Strnadel, Josef Area-Speed Efficient Architecture for GF(2m) Multipliers Dedicated for Cryptographic Applications. 30 Pamuła, Danuta; Hrynkiewicz, Edward Session IB: Advanced Testing On the On-line Functional Test of the Reorder Buffer Memory in Superscalar Processors 36 Di Carlo, Stefano; Sanchez, Ernesto; Senza Reorda, Matteo Fault Collapsing of Multi-Conditional Faults 42 Krenz-Bååth, René; Glowatz, Andreas; Hapke, Friedrich Efficient Automated Speedpath Debugging 48 Dehbashi, Mehdi; Fey, Görschwin Session 2A: System-Level Design A Static Analysis Approach to Data Race Detection in SystemC Designs 54 Moiseev, Mikhail;
Glukhikh, Mikhail; Zakharov, Alexey; Richter, Harald Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications 60 Finder, Alexander; Witte, Jan-Philipp; Fey, Görschwin Design of Stochastic Viterbi Decoders for Convolutional Codes Chen, Te-Hsuan; Hayes, John P 66
Session 2В: High Frequency Design lOGb/s Inverter Based Cascode Transimpedance Amplifier in 40nm CMOS Technology 72 Atef Mohamed; Chen, Hong; Zimmermann, Horst Ultra-High Bandwidth Fully-Differential Three-Stage Operational Amplifiers in 40nm Digital CMOS 76 Chen, Hong; Milovanovič, Vladimir; Giotta, Dario; Zimmermann, Horst A GHz Full-Division-Range Programmable Divider with Output Duty-Cycle Improved 82 Lo, Yu-hung; Tsai, Jhih-Wei; Liu, Han-Ymg; Yang, Wei-Bin Session ЗА: Image Processing An Area Efficient Hardware Architecture Design for H.264/AVC Intra Prediction Reconstruction Path based on Partial Reconfiguration 86 Orlandic, Milica; Svarstad, Kjetil Automatic Synthesis of Small AdaBoost Classifier in FPGA 92 Kadlcek, Filip; Fučík, Otto Session 3B: Robust Circuits A Low Jitter Delay-Locked-Loop Applied for DDR4 98 Tu, Yo-Hao; Cheng, Kuo-Hsing; Wei, Hsiang-Yun; Huang, Hong-Yi Power Analysis Methodology for Secure Circuits 102 Gomina, Kamil; Rigaud, Jean-Baptiste; Gendrier, Philippe; Candelier, Philippe; Tria, Assia Session 4A: Student Papers - RTL Design Towards Hardware Architecture for Memory Efficient ІРѵ4ЛРѵ6 Lookup in 100 Gbps Networks 108 Matoušek, Jiří; Skačan, Martin; Kořenek, Jan Extensible Open-Source Framework for Translating RTL VHDL IP Cores to SystemC 112 Syed, Saif Abrar; Jenihhin, Maksim; Raik, Jaan Multiobjective Evolution of Approximate Multiple Constant Multipliers 116 Petrlik, Jiri; Sekanina, Lukas Hardware Architecture for theFastPattern Matching 120 Kaštil, Jan; Košař, Vlastimil; Kořenek, Jan Session 4В: Student Papers - Robust Design Digital
Methods of Offset Compensation in 90nm CMOS Operational Amplifiers 124 Nagy, Gabriel; Arbet, Daniel; Stopjaková, Viera Frequency Injection Attack on a Random Number Generator 128 Buchoveckd, Simona; Hlaváč, Josef Embedded MicrocontrollerSystem for PilsenCUBEPicosatellite 131 Fiala, Pavel; Voborník, Aleš Proton Beam Characterization at Oslo Cyclotron Laboratory for Radiation Testing of Electronic Devices 135 Hasanbegovic, Amir; Aunet, Snorre Session 5A: Advanced Network and Bus Subsystems Enhanced Fault-Tolerant Network-on-Chip Architecture Using Hierarchical Agents Valinataj, Mojtaba; Liljeberg, Pasi; Plosila, Juha 141
A System-Level Overview and Comparison of Three High-Speed Serial Links: USB 3.0, PCI Express 2.0 and LLI 1.0 147 Saade, Julien; Petrot, Frederic; Picco, Andre; Huloux, Joel; Goulahsen, Abdelaziz A Multi-Credit Row Control Scheme for Asynchronous NoCs 153 Naqvi, Syed Rameez; Najvirt, Robert; Steininger, Andreas Session 5B: Calibration, Reliability, and Simulation Techniques An Indirect Technique for Estimating Reliability of Analog and Mixed-Signal Systems during Operational Life 159 Khan, Muhammad Aamir; Kerkhoff, Hans G. Intermediate Frequency Filter Calibration Method for Radio Frequency Receivers in Modem CMOS Technologies 165 Siwiec, Krzysztof; Koter, Aleksander; Pleskacz, Witold Numerical Method for DC Fault Analysis Simplification and Simulation Time Reduction 170 Brenkaš, Juraj; Stopjaková, Viera; Gyepes, Gábor Session 6A: Reconfiguration Relocation of Reconfigurable Moduleson Xilinx FPGA 175 Drahoňovský, Tomáš; Rozkovec, Martin; Novák, Ondřej On Performance Estimation of a Scalable VLIW Soft-Core in XILINX FPGAs 181 Pfeifer, Petr; Pliva, Zdenek; Schölzel, Mario; Koal, Tobias; Vierhaus, Heinrich T. On the Feasibility of Combining On-Line-Test and Self Repair for Logic Circuits 187 Koal, Tobias; Ulbricht, Markus; Engelke, Piet; Vierhaus, Heinrich T. Session 6B: Emerging Technologies Yield-Oriented Energy and Performance Model for Subthreshold Circuits with Vth Variations 193 Berge, Hans Kristian Otnes; Aunet, Snorre VeSFET as an Analog-Circuit Component 199 Kasprowicz, Dominik; Swacha, Bartosz Efficient Mixture Preparation on Digital Microfluidic Biochips 205 Kumar,
Srijan; Roy, Sudip; Chakrabarti, Partha P; Bhattacharya, Bhargab B.; Chakrabarty, Krishnendu Posters Composing Data-driven Circuits Using Handshake in the Clock-Synchronous Domain 211 Sykora, Jaroslav A Don’t Care Identification Method for Test Compaction 215 Yamazaki, Hiroshi; Wakazono, Motohiro; Hosokawa, Toshinori; Yoshimura, Masayoshi Test Pattem Decompression in Parallel Scan Chain Architecture 219 Chloupek, Martin; Jeniček, Jiri; Novak, Ondrej; Rozkovec, Martin Indoor Energy Harvesting Using Photovoltaic Cell for Battery Recharging 224 Huang, Hong-Υι; Mocorro, Chinet Otic; Pinoso, Julyver; Cheng, Kuo-Hsing Noise and Linearity Analysis of a Frequency to Voltage Converter 228 Michaelsen, Jorgen Andreas; Wisland, Dag T Energy-Aware Software Development for Embedded Systems in HW/SW Co-Design 232 Ehrlich, Paul; Radke, Stephan External Capacitorless Low Dropout Linear Regulator using Cascode Stmcture Huang, Hong-Υι; Chen, Cheng-Yu; Cheng, Kuo-Hsing 236
FPGA Based Time-of-Flight 3D Camera Characterization System 240 Seiten Johannes; Hoßauer, Michael; Davidovic, Milos; Zimmermann, Horst Error Resilient OBDDs 246 Bernasconi, Anna; Ciriani, Valentina; Lago, Lorenzo Design of S-band 0.35/im AlGaN/GaN LNA with Cascode Topology 250 Kao, H. L; Yeh, C. S.; Cho, C. L; Wang, B. W; Lee, R C.; Wei, B. H.; Chiu, H. C. Assertion Based Verification Using PSL-like Properties In Haskell 254 Uchevler, Bahram Najafi; Svarstad, Kjetil Reliability-aware Cross-Layer Custom InstructionScreening 258 J. Farahani, Bahareh; Azarpeyvand, Ali; Safari, Saeed; Fakhraie, Seid Mehdi Efficiency of Oscillation-based BIST in 90nm CMOS Active Analog Filters 263 Arbet, Daniel; Nagy, Gabriel; Stopjaková, Viera; Gyepes, Gábor FPGA Architecture for Fast Floating Point Matrix Inversion Using Uni-dimensional Systolic Array Based Structure 267 Hnilička, Ondřej Redundancy Algorithm for Embedded Memories with Block-Based Architecture 271 Krištofík, Stefan; Gramatová, Elena Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability 275 Šimková, Marcela; Kotásek, Zdeněk; Bolchini, Cristiana Fault-Tolerant Reconfigurable Low-PowerPseudorandomNumber Generator 279 Petrovič, Vladimir; Stamenkovic, Zoran; Stojcev, Mile; Nikolič, Tatjana; Jovanovič, Goran A New Method for Correcting Time and Soft Errors in Combinational Circuits 283 Sogomonyan, Egor S.; Weidling, Stefan; Goessel, Michael Student posters MBIST for LEON3 ProcessorCore Cache 287 Kincel, Andrej; Balaz, Marcel Fault Tolerant CAN Bus Control System Implemented into FPGA 289 Szurman,
Karel; Kastil, Jan; Straka, Martin; Kotasek, Zdenek Improved Design of the Uninterruptable Power Supply Unit for Powering of Network Devices 293 Pospisilik, Martin; Neumann, Petr Hybrid Mesh-Ring WirelessNetwork onChip for Multi-Core System 295 Wanas, Mohamed; Abd El Ghany, Mohamed; Hofmann, Klaus Novel Model Calibration Method Based on Differential Evolution Used for SCR Model Fitting 297 Napravnik, Tomas; Ziska, Přemysl; Jakovenko, Jiri Author Index 299
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| spelling | International Symposium on Design and Diagnostics of Electronic Circuits and Systems 16 2013 Karlovy Vary Verfasser (DE-588)1051496659 aut Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) April 8 - 10, 2013, Karlovy Vary Sekanina, Lukáš ; co-spons. by IEEE Computer Society Test Technology Technical Council ... 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems Piscataway, N.J. IEEE 2013 300 S. zahlr. graph. Darst. txt rdacontent n rdamedia nc rdacarrier IEEE catalog number: CFP13DDE-PRT Includes bibliographical references and index Integrated circuits Testing Congresses Integrated circuits Design Congresses Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Test (DE-588)4059549-3 gnd rswk-swf Design (DE-588)4011510-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift gnd-content Integrierte Schaltung (DE-588)4027242-4 s Test (DE-588)4059549-3 s DE-604 Design (DE-588)4011510-0 s Sekanina, Lukáš Sonstige oth Digitalisierung UB Passau - ADAM Catalogue Enrichment application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027325110&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) April 8 - 10, 2013, Karlovy Vary Integrated circuits Testing Congresses Integrated circuits Design Congresses Integrierte Schaltung (DE-588)4027242-4 gnd Test (DE-588)4059549-3 gnd Design (DE-588)4011510-0 gnd |
| subject_GND | (DE-588)4027242-4 (DE-588)4059549-3 (DE-588)4011510-0 (DE-588)1071861417 |
| title | Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) April 8 - 10, 2013, Karlovy Vary |
| title_alt | 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems |
| title_auth | Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) April 8 - 10, 2013, Karlovy Vary |
| title_exact_search | Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) April 8 - 10, 2013, Karlovy Vary |
| title_full | Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) April 8 - 10, 2013, Karlovy Vary Sekanina, Lukáš ; co-spons. by IEEE Computer Society Test Technology Technical Council ... |
| title_fullStr | Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) April 8 - 10, 2013, Karlovy Vary Sekanina, Lukáš ; co-spons. by IEEE Computer Society Test Technology Technical Council ... |
| title_full_unstemmed | Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) April 8 - 10, 2013, Karlovy Vary Sekanina, Lukáš ; co-spons. by IEEE Computer Society Test Technology Technical Council ... |
| title_short | Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) |
| title_sort | proceedings of the 2013 ieee 16th international symposium on design and diagnostics of electronic circuits and systems ddecs april 8 10 2013 karlovy vary |
| title_sub | April 8 - 10, 2013, Karlovy Vary |
| topic | Integrated circuits Testing Congresses Integrated circuits Design Congresses Integrierte Schaltung (DE-588)4027242-4 gnd Test (DE-588)4059549-3 gnd Design (DE-588)4011510-0 gnd |
| topic_facet | Integrated circuits Testing Congresses Integrated circuits Design Congresses Integrierte Schaltung Test Design Konferenzschrift |
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