Design for embedded image processing on FPGAs:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
Wiley
2011
|
| Schlagworte: | |
| Online-Zugang: | FHI01 FHN01 Volltext |
| Beschreibung: | "Introductory material will consider the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage will be given of a range of image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques will be illustrated with several example applications or case studies from projects or applications I have been involves with. Issues such as interfacing between the FPGA and peripheral devices will be covered briefly, as will designing the system in such a way that it can be more readily debugged and tuned"-- "The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation"-- Includes bibliographical references and index |
| Beschreibung: | 1 Online-Ressource (1 online resource) |
| ISBN: | 9780470828519 047082851X 1283175169 9781283175166 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV041874369 | ||
| 003 | DE-604 | ||
| 005 | 20141219 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 140523s2011 |||| o||u| ||||||eng d | ||
| 020 | |a 9780470828519 |c electronic bk. |9 978-0-470-82851-9 | ||
| 020 | |a 047082851X |c electronic bk. |9 0-470-82851-X | ||
| 020 | |a 1283175169 |9 1-283-17516-9 | ||
| 020 | |a 9781283175166 |9 978-1-283-17516-6 | ||
| 024 | 7 | |a 10.1002/9780470828519 |2 doi | |
| 035 | |a (OCoLC)739118465 | ||
| 035 | |a (DE-599)BVBBV041874369 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-Aug4 |a DE-861 |a DE-573 |a DE-92 | ||
| 082 | 0 | |a 621.39/9 |2 22 | |
| 100 | 1 | |a Bailey, Donald G., (Donald Graeme) |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Design for embedded image processing on FPGAs |c Donald G. Bailey |
| 264 | 1 | |a New York, NY |b Wiley |c 2011 | |
| 300 | |a 1 Online-Ressource (1 online resource) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a "Introductory material will consider the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage will be given of a range of image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques will be illustrated with several example applications or case studies from projects or applications I have been involves with. Issues such as interfacing between the FPGA and peripheral devices will be covered briefly, as will designing the system in such a way that it can be more readily debugged and tuned"-- | ||
| 500 | |a "The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation"-- | ||
| 500 | |a Includes bibliographical references and index | ||
| 650 | 4 | |a Electronic resource | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Microelectronics |2 bisacsh | |
| 650 | 7 | |a Embedded computer systems |2 fast | |
| 650 | 7 | |a Field programmable gate arrays |2 fast | |
| 650 | 4 | |a Embedded computer systems | |
| 650 | 4 | |a Field programmable gate arrays | |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Eingebettetes System |0 (DE-588)4396978-1 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
| 689 | 0 | 1 | |a Eingebettetes System |0 (DE-588)4396978-1 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 856 | 4 | 0 | |u https://onlinelibrary.wiley.com/doi/book/10.1002/9780470828519 |x Verlag |3 Volltext |
| 912 | |a ZDB-35-WIC |a ZDB-35-WEL | ||
| 940 | 1 | |q FRO_PDA_WIC | |
| 940 | 1 | |q UBG_PDA_WIC | |
| 940 | 1 | |q FHA_PDA_WIC_Kauf | |
| 940 | 1 | |q FHR_PDA_WIC | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-027318551 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 966 | e | |u https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6016259 |l FHI01 |p ZDB-35-WEL |x Aggregator |3 Volltext | |
| 966 | e | |u https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6016259 |l FHN01 |p ZDB-35-WEL |x Aggregator |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804152219527806976 |
|---|---|
| any_adam_object | |
| author | Bailey, Donald G., (Donald Graeme) |
| author_facet | Bailey, Donald G., (Donald Graeme) |
| author_role | aut |
| author_sort | Bailey, Donald G., (Donald Graeme) |
| author_variant | d g d g b dgdg dgdgb |
| building | Verbundindex |
| bvnumber | BV041874369 |
| collection | ZDB-35-WIC ZDB-35-WEL |
| ctrlnum | (OCoLC)739118465 (DE-599)BVBBV041874369 |
| dewey-full | 621.39/9 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/9 |
| dewey-search | 621.39/9 |
| dewey-sort | 3621.39 19 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03933nmm a2200589zc 4500</leader><controlfield tag="001">BV041874369</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20141219 </controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">140523s2011 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780470828519</subfield><subfield code="c">electronic bk.</subfield><subfield code="9">978-0-470-82851-9</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">047082851X</subfield><subfield code="c">electronic bk.</subfield><subfield code="9">0-470-82851-X</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1283175169</subfield><subfield code="9">1-283-17516-9</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781283175166</subfield><subfield code="9">978-1-283-17516-6</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1002/9780470828519</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)739118465</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV041874369</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-Aug4</subfield><subfield code="a">DE-861</subfield><subfield code="a">DE-573</subfield><subfield code="a">DE-92</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/9</subfield><subfield code="2">22</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Bailey, Donald G., (Donald Graeme)</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Design for embedded image processing on FPGAs</subfield><subfield code="c">Donald G. Bailey</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">New York, NY</subfield><subfield code="b">Wiley</subfield><subfield code="c">2011</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (1 online resource)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">"Introductory material will consider the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage will be given of a range of image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques will be illustrated with several example applications or case studies from projects or applications I have been involves with. Issues such as interfacing between the FPGA and peripheral devices will be covered briefly, as will designing the system in such a way that it can be more readily debugged and tuned"--</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">"The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation"--</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references and index</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic resource</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Microelectronics</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Embedded computer systems</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Field programmable gate arrays</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Embedded computer systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Field programmable gate arrays</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Eingebettetes System</subfield><subfield code="0">(DE-588)4396978-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Eingebettetes System</subfield><subfield code="0">(DE-588)4396978-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://onlinelibrary.wiley.com/doi/book/10.1002/9780470828519</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-35-WIC</subfield><subfield code="a">ZDB-35-WEL</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">FRO_PDA_WIC</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">UBG_PDA_WIC</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">FHA_PDA_WIC_Kauf</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">FHR_PDA_WIC</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-027318551</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6016259</subfield><subfield code="l">FHI01</subfield><subfield code="p">ZDB-35-WEL</subfield><subfield code="x">Aggregator</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6016259</subfield><subfield code="l">FHN01</subfield><subfield code="p">ZDB-35-WEL</subfield><subfield code="x">Aggregator</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV041874369 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T01:07:14Z |
| institution | BVB |
| isbn | 9780470828519 047082851X 1283175169 9781283175166 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027318551 |
| oclc_num | 739118465 |
| open_access_boolean | |
| owner | DE-Aug4 DE-861 DE-573 DE-92 |
| owner_facet | DE-Aug4 DE-861 DE-573 DE-92 |
| physical | 1 Online-Ressource (1 online resource) |
| psigel | ZDB-35-WIC ZDB-35-WEL FRO_PDA_WIC UBG_PDA_WIC FHA_PDA_WIC_Kauf FHR_PDA_WIC |
| publishDate | 2011 |
| publishDateSearch | 2011 |
| publishDateSort | 2011 |
| publisher | Wiley |
| record_format | marc |
| spelling | Bailey, Donald G., (Donald Graeme) Verfasser aut Design for embedded image processing on FPGAs Donald G. Bailey New York, NY Wiley 2011 1 Online-Ressource (1 online resource) txt rdacontent c rdamedia cr rdacarrier "Introductory material will consider the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage will be given of a range of image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques will be illustrated with several example applications or case studies from projects or applications I have been involves with. Issues such as interfacing between the FPGA and peripheral devices will be covered briefly, as will designing the system in such a way that it can be more readily debugged and tuned"-- "The bulk of the book will focus on the design process, and in particular how designing an FPGA implementation differs from a conventional software implementation"-- Includes bibliographical references and index Electronic resource TECHNOLOGY & ENGINEERING / Electronics / Microelectronics bisacsh Embedded computer systems fast Field programmable gate arrays fast Embedded computer systems Field programmable gate arrays Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Eingebettetes System (DE-588)4396978-1 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 s Eingebettetes System (DE-588)4396978-1 s 1\p DE-604 https://onlinelibrary.wiley.com/doi/book/10.1002/9780470828519 Verlag Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Bailey, Donald G., (Donald Graeme) Design for embedded image processing on FPGAs Electronic resource TECHNOLOGY & ENGINEERING / Electronics / Microelectronics bisacsh Embedded computer systems fast Field programmable gate arrays fast Embedded computer systems Field programmable gate arrays Field programmable gate array (DE-588)4347749-5 gnd Eingebettetes System (DE-588)4396978-1 gnd |
| subject_GND | (DE-588)4347749-5 (DE-588)4396978-1 |
| title | Design for embedded image processing on FPGAs |
| title_auth | Design for embedded image processing on FPGAs |
| title_exact_search | Design for embedded image processing on FPGAs |
| title_full | Design for embedded image processing on FPGAs Donald G. Bailey |
| title_fullStr | Design for embedded image processing on FPGAs Donald G. Bailey |
| title_full_unstemmed | Design for embedded image processing on FPGAs Donald G. Bailey |
| title_short | Design for embedded image processing on FPGAs |
| title_sort | design for embedded image processing on fpgas |
| topic | Electronic resource TECHNOLOGY & ENGINEERING / Electronics / Microelectronics bisacsh Embedded computer systems fast Field programmable gate arrays fast Embedded computer systems Field programmable gate arrays Field programmable gate array (DE-588)4347749-5 gnd Eingebettetes System (DE-588)4396978-1 gnd |
| topic_facet | Electronic resource TECHNOLOGY & ENGINEERING / Electronics / Microelectronics Embedded computer systems Field programmable gate arrays Field programmable gate array Eingebettetes System |
| url | https://onlinelibrary.wiley.com/doi/book/10.1002/9780470828519 |
| work_keys_str_mv | AT baileydonaldgdonaldgraeme designforembeddedimageprocessingonfpgas |