Parallelisation potential of image segmentation in hierarchical island structures on hardware-accelerated platforms in real-time applications:
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
Jülich
Forschungszentrum Jülich, Zentralbibliothek
2013
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| Schriftenreihe: | Schriften des Forschungszentrums Jülich: Reihe Information
30 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XIV, 211 S. Ill., graph. Darst. |
| ISBN: | 9783893369140 |
Internformat
MARC
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| 245 | 1 | 0 | |a Parallelisation potential of image segmentation in hierarchical island structures on hardware-accelerated platforms in real-time applications |c Sergey Suslov |
| 264 | 1 | |a Jülich |b Forschungszentrum Jülich, Zentralbibliothek |c 2013 | |
| 300 | |a XIV, 211 S. |b Ill., graph. Darst. | ||
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Datensatz im Suchindex
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| adam_text | TABLE OF CONTENTS
1 INTRODUCTION 1
2 FUNDAMENTALS AND RESEARCH BACKGROUND 7
2.1 SEGMENTATION IN IMAGE PROCESSING 7
2.1.1 OVERVIEW ON SEGMENTATION METHODS 7
2.1.2 GREY SCALE CODE METHOD 9
2.2 DIGITAL PLATFORMS 11
2.2.1 ALGORITHM IMPLEMENTATION 13
2.2.2 DEVICES WITH CONFIGURABLE STRUCTURE 14
2.2.2.1 SIMPLE PROGRAMMABLE LOGIC DEVICES 15
2.2.2.2 COMPLEX PROGRAMMABLE LOGIC DEVICES 15
2.2.2.3 APPLICATION-SPECIFIC INTEGRATION CIRCUITS 16
2.2.2.4 FIELD-PROGRAMMABLE GATE ARRAYS 18
2.2.2.5 VIRTEX II PRO ARCHITECTURE 20
2.2.3 GRAPHICS PROCESSING UNITS 21
2.2.3.1 GRAPHIC PIPELINE 21
2.2.3.2 PECULIARITIES OF GRAPHICS PROCESSING ORGANISATION 23
2.2.3.3 MODERN GPU ARCHITECTURE 24
2.2.3.4 GPU COMPUTING 27
3 METHODOLOGY 29
3.1 FPGA-SYSTEM DESIGN METHODOLOGY 29
3.1.1 GENERAL SYSTEM DESIGN CONCEPT 30
3.1.1.1 SPIRAL APPROACH TO SYSTEM DEVELOPMENT 30
HTTP://D-NB.INFO/1045853402
VI TABLE OF CONTENTS
3.1.1.2 THREE-PHASE VIEW ON SYSTEM DESIGN PROCESS 31
3.1.2 MODELLING 32
3.1.2.1 STATIC AND DYNAMIC MODELS 32
3.1.2.2 MODEL ACCURACY 33
3.1.2.3 PARTIAL MODEL REFINEMENT 34
3.1.2.4 TRANSACTION-LEVEL MODELING 34
3.1.2.5 MODELLING ANALYSIS 35
3.1.3 IMPLEMENTATION 36
3.1.3.1 REGISTER TRANSFER LEVEL 37
3.1.3.2 LANGUAGE-BASED DESCRIPTION 37
3.1.3.3 COMPONENT REUSE 38
3.1.4 VERIFICATION 38
3.1.4.1 FUNCTIONAL VERIFICATION 38
3.1.4.2 TIMING VERIFICATION 45
3.2 GPU IMPLEMENTATION OPTIMISATION 45
3.2.1 GLOBAL MEMORY THROUGHPUT OPTIMISATION 46
3.2.2 SHARED MEMORY 47
3.2.3 DYNAMIC BRANCHING 48
4 HARDWARE IMPLEMENTATION 49
4.1 FUNCTIONAL ANALYSIS 49
4.1.1 REFERENCE SOFTWARE IMPLEMENTATION 49
4.1.1.1 DATA STRUCTURE 49
4.1.1.2 IMPLEMENTATION OF THE DIFFERENT GSC PHASES 50
4.1.2 STUDY PREMISES 53
4.1.3 ALGORITHM ANALYSIS FOR COMPUTATION PARALLELISM 53
4.1.4 DATA ORGANISATION 58
4.1.5 FUNCTIONAL EXECUTABLE MODEL 59
4.2 ARCHITECTURAL MODEL 59
4.2.1 COMPUTATION PLATFORM 59
4.2.2 HARDWARE DATA-STRUCTURE LAYOUT 60
4.2.3 DATA-STREAM MODEL 63
4.2.3.1 LINKING 64
4.2.3.2 CODING 68
4.2.3.3 DOWNPROPAGATION AND RESULT IMAGE GENERATION 69
TABLE OF CONTENTS VIL
4.2.3.4 PERFORMANCE IMPROVEMENT STRATEGIES 72
4.2.4 APPLICATION MEMORY SPACE MAPPING 78
4.2.5 ARCHITECTURAL EXECUTABLE MODEL 79
4.2.5.1 CODING ALGORITHM 79
4.2.5.2 LINKING ALGORITHM 82
4.2.5.3 OVERLAP-LIST CREATION ALGORITHM 86
4.2.5.4 DOWNPROPAGATION PROCESS 88
4.2.5.5 SIMULATION RESULTS 89
4.2.6 PREIMPLEMENTATION RESOURCE ESTIMATION MODEL 91
4.2.7 ON-CHIP INFRASTRUCTURE 92
4.2.8 CLOCK DOMAINS 95
4.3 INTERFACE AND COMMUNICATION MODEL 95
4.3.1 SYSTEM INTERFACES 95
4.3.2 SYSTEM NETWORK TRAFFIC AND DATA BUFFERING SCHEME 97
4.3.3 INTERFACE TEMPORAL LOGIC AND BUS FUNCTIONAL EXECUTABLE MODELS 98
4.3.4 MODELLING RESULTS 99
4.4 REGISTER-TRANSFER LEVEL IMPLEMENTATION 103
4.4.1 APPLICATION-SPECIFIC BLOCKS 105
4.4.1.1 CODING UNIT 105
4.4.1.2 LINKING UNIT 105
4.4.1.3 LABELLING PROCESSORS 108
4.4.2 ON-CHIP SYSTEM INFRASTRUCTURE 112
4.4.2.1 EXPANSION BOARD INTERFACE UNIT 112
4.4.2.2 SWITCH MATRIX 113
4.4.2.3 MEMORY PERIPHERAL CONTROLLERS 113
4.4.3 LOW-LEVEL VERIFICATION ASPECTS 113
4.4.4 SYSTEM-ON-CHIP SYNTHESIS AND LAYOUT SUMMARY 115
5 GPU IMPLEMENTATION 117
5.1 OVERVIEW 117
5.1.1 FUNCTION PARTITIONING 117
5.1.2 GLOBAL MEMORY DATA-STRUCTURE LAYOUT 118
5.1.3 GENERAL OPTIMISATION STRATEGIES 121
5.2 KERNELS IMPLEMENTATION 122
5.2.1 REGION CODING 122
VIII TABLE OF CONTENTS
5.2.2 OVERLAP-LIST CREATION 128
5.2.3 LINKING KERNEL IMPLEMENTATION 133
5.2.4 DOWNPROPAGATION AND RESULT GENERATION 139
6 RESULTS COMPARISON 143
6.1 APPLICATION PERFORMANCE AND DATASET SCALABILITY 143
6.2 COMPARISON OF APPLICATION DEVELOPMENT FACTORS 146
6.2.1 IMPLEMENTATION EFFORTS 146
6.2.2 FUNCTIONAL MODIFIABILITY 148
7 SUMMARY 151
8 CONCLUSIONS AND OUTLOOK 157
8.1 CONCLUSIONS 157
8.2 OUTLOOK 159
8.2.1 PERFORMANCE ON PROSPECTIVE FPGA AND GPU PLATFORMS 159
8.2.2 FUTURE WORK 162
A APPENDIX 165
A.L VIRTEX II PRO ARCHITECTURE ELEMENTS 165
A. 1.1 INPUT/OUTPUT BLOCKS 165
A. 1.2 LOGIC RESOURCES 165
A.L.3 CLOCKING RESOURCES 167
A. 1.4 INTERCONNECTION SYSTEM 167
A.2 IMPLEMENTATION CALCULATIONS 169
A.2.1 OVERLAP-LIST RATIONALES 169
A.2.2 AVERAGE REGION FEATURE CALCULATION ERROR FOR SEQUENTIAL LINKING
169
A.3 TRAFFIC MODEL 170
A.4 HW-GSC PROFILING STATISTICS 173
A.5 HARDWARE RESOURCE MODEL 187
A.6 LABELLING PROCESSOR CACHE EFFICIENCY 196
A.7 INTERFACE DESCRIPTIONS 197
A.7.1 ZBT CONTROLLER CORE INTERFACE 197
A.7.2 SWITCH MATRIX INTERFACE 199
BIBLIOGRAPHY 201
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| discipline | Allgemeine Naturwissenschaft Informatik |
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| indexdate | 2024-07-10T01:01:21Z |
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| isbn | 9783893369140 |
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| physical | XIV, 211 S. Ill., graph. Darst. |
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| series2 | Schriften des Forschungszentrums Jülich: Reihe Information |
| spelling | Suslov, Sergej 1980- Verfasser (DE-588)1045164429 aut Parallelisation potential of image segmentation in hierarchical island structures on hardware-accelerated platforms in real-time applications Sergey Suslov Jülich Forschungszentrum Jülich, Zentralbibliothek 2013 XIV, 211 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Schriften des Forschungszentrums Jülich: Reihe Information 30 Zugl.: Mannheim, Univ., Diss., 2012 Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Grafikprozessor (DE-588)4582114-8 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Field programmable gate array (DE-588)4347749-5 s Grafikprozessor (DE-588)4582114-8 s DE-604 Schriften des Forschungszentrums Jülich: Reihe Information 30 (DE-604)BV035800087 30 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027071490&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Suslov, Sergej 1980- Parallelisation potential of image segmentation in hierarchical island structures on hardware-accelerated platforms in real-time applications Schriften des Forschungszentrums Jülich: Reihe Information Field programmable gate array (DE-588)4347749-5 gnd Grafikprozessor (DE-588)4582114-8 gnd |
| subject_GND | (DE-588)4347749-5 (DE-588)4582114-8 (DE-588)4113937-9 |
| title | Parallelisation potential of image segmentation in hierarchical island structures on hardware-accelerated platforms in real-time applications |
| title_auth | Parallelisation potential of image segmentation in hierarchical island structures on hardware-accelerated platforms in real-time applications |
| title_exact_search | Parallelisation potential of image segmentation in hierarchical island structures on hardware-accelerated platforms in real-time applications |
| title_full | Parallelisation potential of image segmentation in hierarchical island structures on hardware-accelerated platforms in real-time applications Sergey Suslov |
| title_fullStr | Parallelisation potential of image segmentation in hierarchical island structures on hardware-accelerated platforms in real-time applications Sergey Suslov |
| title_full_unstemmed | Parallelisation potential of image segmentation in hierarchical island structures on hardware-accelerated platforms in real-time applications Sergey Suslov |
| title_short | Parallelisation potential of image segmentation in hierarchical island structures on hardware-accelerated platforms in real-time applications |
| title_sort | parallelisation potential of image segmentation in hierarchical island structures on hardware accelerated platforms in real time applications |
| topic | Field programmable gate array (DE-588)4347749-5 gnd Grafikprozessor (DE-588)4582114-8 gnd |
| topic_facet | Field programmable gate array Grafikprozessor Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027071490&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV035800087 |
| work_keys_str_mv | AT suslovsergej parallelisationpotentialofimagesegmentationinhierarchicalislandstructuresonhardwareacceleratedplatformsinrealtimeapplications |