Models, Methods, and Tools for Complex Chip Design: Selected Contributions from FDL 2012
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
2014
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| Schriftenreihe: | Lecture Notes in Electrical Engineering
265 |
| Schlagworte: | |
| Online-Zugang: | BTU01 FHA01 FHI01 FHN01 FHR01 FKE01 FRO01 FWS01 FWS02 UBY01 Volltext Inhaltsverzeichnis Abstract |
| Beschreibung: | This book brings together a selection of the best papers from the fifteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in September 2012 at Vienna University of Technology, Vienna, Austria. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems. · Covers Assertion Based Design, Verification & Debug; · Includes language-based modeling and design techniques for embedded systems; · Covers design, modeling and verification of mixed physical domain and mixed signal systems that include significant analog parts in electrical and non-electrical domains; · Includes formal and semi-formal system level design methods for complex embedded systems based on the Unified Modelling Language (UML) and Model Driven Engineering (MDE) |
| Beschreibung: | 1 Online-Ressource (XV, 221 p.) 94 illus., 57 illus. in color |
| ISBN: | 9783319014180 |
| DOI: | 10.1007/978-3-319-01418-0 |
Internformat
MARC
| LEADER | 00000nmm a2200000zcb4500 | ||
|---|---|---|---|
| 001 | BV041470946 | ||
| 003 | DE-604 | ||
| 005 | 20160316 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 131210s2014 |||| o||u| ||||||eng d | ||
| 020 | |a 9783319014180 |9 978-3-319-01418-0 | ||
| 024 | 7 | |a 10.1007/978-3-319-01418-0 |2 doi | |
| 035 | |a (OCoLC)874381426 | ||
| 035 | |a (DE-599)BVBBV041470946 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-Aug4 |a DE-92 |a DE-634 |a DE-859 |a DE-898 |a DE-573 |a DE-861 |a DE-706 |a DE-863 |a DE-862 | ||
| 082 | 0 | |a 621.3815 |2 23 | |
| 100 | 1 | |a Haase, Jan |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Models, Methods, and Tools for Complex Chip Design |b Selected Contributions from FDL 2012 |c edited by Jan Haase |
| 264 | 1 | |c 2014 | |
| 300 | |a 1 Online-Ressource (XV, 221 p.) |b 94 illus., 57 illus. in color | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 490 | 1 | |a Lecture Notes in Electrical Engineering |v 265 | |
| 500 | |a This book brings together a selection of the best papers from the fifteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in September 2012 at Vienna University of Technology, Vienna, Austria. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems. · Covers Assertion Based Design, Verification & Debug; · Includes language-based modeling and design techniques for embedded systems; · Covers design, modeling and verification of mixed physical domain and mixed signal systems that include significant analog parts in electrical and non-electrical domains; · Includes formal and semi-formal system level design methods for complex embedded systems based on the Unified Modelling Language (UML) and Model Driven Engineering (MDE) | ||
| 505 | 0 | |a Formal Plausibility Checks for Environment -- Efficient Refinement Strategy Exploiting Component Properties in A CEGAR Process -- Formal Specification Level -- Power Estimation Methodology for SystemC -- SystemC Analysis for Nondeterminism Anomalies -- A Design and Verification Methodology for Mixed-Signal Systems Using SystemC-AMS -- Configurable Load Emulation Using FPGA and Power Amplifiers for Automotive Power ICs -- Model Based Design of Distributed Embedded Cyber Physical Systems -- Model-driven Methodology for the Development of Multi-level Executable Environments -- The Concept and Study of Grid Responsiveness -- Polynomial Metamodel-Based Fast Optimization of Nanoscale PLL Components -- Methodology and Example-Driven Interconnect Synthesis for Designing Heterogenous Coarse-Grain Reconfigurable Architectures | |
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Computer science | |
| 650 | 4 | |a Electronics | |
| 650 | 4 | |a Systems engineering | |
| 650 | 4 | |a Circuits and Systems | |
| 650 | 4 | |a Processor Architectures | |
| 650 | 4 | |a Electronics and Microelectronics, Instrumentation | |
| 650 | 4 | |a Informatik | |
| 650 | 4 | |a Ingenieurwissenschaften | |
| 830 | 0 | |a Lecture Notes in Electrical Engineering |v 265 |w (DE-604)BV042385829 |9 265 | |
| 856 | 4 | 0 | |u https://doi.org/10.1007/978-3-319-01418-0 |x Verlag |3 Volltext |
| 856 | 4 | 2 | |m Springer Fremddatenuebernahme |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=026917088&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 856 | 4 | 2 | |m Springer Fremddatenuebernahme |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=026917088&sequence=000003&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA |3 Abstract |
| 912 | |a ZDB-2-ENG | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-026917088 | ||
| 966 | e | |u https://doi.org/10.1007/978-3-319-01418-0 |l BTU01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-01418-0 |l FHA01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-01418-0 |l FHI01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-01418-0 |l FHN01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-01418-0 |l FHR01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-01418-0 |l FKE01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-01418-0 |l FRO01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-01418-0 |l FWS01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-01418-0 |l FWS02 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-01418-0 |l UBY01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
Datensatz im Suchindex
| DE-BY-FWS_katkey | 1015818 |
|---|---|
| _version_ | 1806174832850632704 |
| adam_text | MODELS, METHODS, AND TOOLS FOR COMPLEX CHIP DESIGN
/
: 2014
TABLE OF CONTENTS / INHALTSVERZEICHNIS
FORMAL PLAUSIBILITY CHECKS FOR ENVIRONMENT
EFFICIENT REFINEMENT STRATEGY EXPLOITING COMPONENT PROPERTIES IN A CEGAR
PROCESS
FORMAL SPECIFICATION LEVEL
POWER ESTIMATION METHODOLOGY FOR SYSTEMC
SYSTEMC ANALYSIS FOR NONDETERMINISM ANOMALIES
A DESIGN AND VERIFICATION METHODOLOGY FOR MIXED-SIGNAL SYSTEMS USING
SYSTEMC-AMS
CONFIGURABLE LOAD EMULATION USING FPGA AND POWER AMPLIFIERS FOR
AUTOMOTIVE POWER ICS
MODEL BASED DESIGN OF DISTRIBUTED EMBEDDED CYBER PHYSICAL SYSTEMS
MODEL-DRIVEN METHODOLOGY FOR THE DEVELOPMENT OF MULTI-LEVEL EXECUTABLE
ENVIRONMENTS
THE CONCEPT AND STUDY OF GRID RESPONSIVENESS
POLYNOMIAL METAMODEL-BASED FAST OPTIMIZATION OF NANOSCALE PLL COMPONENTS
METHODOLOGY AND EXAMPLE-DRIVEN INTERCONNECT SYNTHESIS FOR DESIGNING
HETEROGENOUS COARSE-GRAIN RECONFIGURABLE ARCHITECTURES
DIESES SCHRIFTSTUECK WURDE MASCHINELL ERZEUGT.
MODELS, METHODS, AND TOOLS FOR COMPLEX CHIP DESIGN
/
: 2014
ABSTRACT / INHALTSTEXT
THIS BOOK BRINGS TOGETHER A SELECTION OF THE BEST PAPERS FROM THE
FIFTEENTH EDITION OF THE FORUM ON SPECIFICATION AND DESIGN LANGUAGES
CONFERENCE (FDL), WHICH WAS HELD IN SEPTEMBER 2012 AT VIENNA UNIVERSITY
OF TECHNOLOGY, VIENNA, AUSTRIA. FDL IS A WELL-ESTABLISHED
INTERNATIONAL FORUM DEVOTED TO DISSEMINATION OF RESEARCH RESULTS,
PRACTICAL EXPERIENCES AND NEW IDEAS IN THE APPLICATION OF SPECIFICATION,
DESIGN AND VERIFICATION LANGUAGES TO THE DESIGN, MODELING AND
VERIFICATION OF INTEGRATED CIRCUITS, COMPLEX HARDWARE/SOFTWARE EMBEDDED
SYSTEMS, AND MIXED-TECHNOLOGY SYSTEMS. COVERS
ASSERTION BASED DESIGN, VERIFICATION & DEBUG;
INCLUDES LANGUAGE-BASED MODELING AND DESIGN TECHNIQUES FOR EMBEDDED
SYSTEMS; COVERS DESIGN, MODELING AND VERIFICATION OF
MIXED PHYSICAL DOMAIN AND MIXED SIGNAL SYSTEMS THAT INCLUDE SIGNIFICANT
ANALOG PARTS IN ELECTRICAL AND NON-ELECTRICAL DOMAINS;
INCLUDES FORMAL AND SEMI-FORMAL SYSTEM LEVEL DESIGN
METHODS FOR COMPLEX EMBEDDED SYSTEMS BASED ON THE UNIFIED MODELLING
LANGUAGE (UML) AND MODEL DRIVEN ENGINEERING (MDE)
DIESES SCHRIFTSTUECK WURDE MASCHINELL ERZEUGT.
|
| any_adam_object | 1 |
| author | Haase, Jan |
| author_facet | Haase, Jan |
| author_role | aut |
| author_sort | Haase, Jan |
| author_variant | j h jh |
| building | Verbundindex |
| bvnumber | BV041470946 |
| collection | ZDB-2-ENG |
| contents | Formal Plausibility Checks for Environment -- Efficient Refinement Strategy Exploiting Component Properties in A CEGAR Process -- Formal Specification Level -- Power Estimation Methodology for SystemC -- SystemC Analysis for Nondeterminism Anomalies -- A Design and Verification Methodology for Mixed-Signal Systems Using SystemC-AMS -- Configurable Load Emulation Using FPGA and Power Amplifiers for Automotive Power ICs -- Model Based Design of Distributed Embedded Cyber Physical Systems -- Model-driven Methodology for the Development of Multi-level Executable Environments -- The Concept and Study of Grid Responsiveness -- Polynomial Metamodel-Based Fast Optimization of Nanoscale PLL Components -- Methodology and Example-Driven Interconnect Synthesis for Designing Heterogenous Coarse-Grain Reconfigurable Architectures |
| ctrlnum | (OCoLC)874381426 (DE-599)BVBBV041470946 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-3-319-01418-0 |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>04952nmm a2200601zcb4500</leader><controlfield tag="001">BV041470946</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20160316 </controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">131210s2014 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9783319014180</subfield><subfield code="9">978-3-319-01418-0</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-3-319-01418-0</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)874381426</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV041470946</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-Aug4</subfield><subfield code="a">DE-92</subfield><subfield code="a">DE-634</subfield><subfield code="a">DE-859</subfield><subfield code="a">DE-898</subfield><subfield code="a">DE-573</subfield><subfield code="a">DE-861</subfield><subfield code="a">DE-706</subfield><subfield code="a">DE-863</subfield><subfield code="a">DE-862</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Haase, Jan</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Models, Methods, and Tools for Complex Chip Design</subfield><subfield code="b">Selected Contributions from FDL 2012</subfield><subfield code="c">edited by Jan Haase</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2014</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XV, 221 p.)</subfield><subfield code="b">94 illus., 57 illus. in color</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Lecture Notes in Electrical Engineering</subfield><subfield code="v">265</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">This book brings together a selection of the best papers from the fifteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in September 2012 at Vienna University of Technology, Vienna, Austria. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems. · Covers Assertion Based Design, Verification & Debug; · Includes language-based modeling and design techniques for embedded systems; · Covers design, modeling and verification of mixed physical domain and mixed signal systems that include significant analog parts in electrical and non-electrical domains; · Includes formal and semi-formal system level design methods for complex embedded systems based on the Unified Modelling Language (UML) and Model Driven Engineering (MDE)</subfield></datafield><datafield tag="505" ind1="0" ind2=" "><subfield code="a">Formal Plausibility Checks for Environment -- Efficient Refinement Strategy Exploiting Component Properties in A CEGAR Process -- Formal Specification Level -- Power Estimation Methodology for SystemC -- SystemC Analysis for Nondeterminism Anomalies -- A Design and Verification Methodology for Mixed-Signal Systems Using SystemC-AMS -- Configurable Load Emulation Using FPGA and Power Amplifiers for Automotive Power ICs -- Model Based Design of Distributed Embedded Cyber Physical Systems -- Model-driven Methodology for the Development of Multi-level Executable Environments -- The Concept and Study of Grid Responsiveness -- Polynomial Metamodel-Based Fast Optimization of Nanoscale PLL Components -- Methodology and Example-Driven Interconnect Synthesis for Designing Heterogenous Coarse-Grain Reconfigurable Architectures</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer science</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronics</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Systems engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Processor Architectures</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronics and Microelectronics, Instrumentation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Informatik</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Ingenieurwissenschaften</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Lecture Notes in Electrical Engineering</subfield><subfield code="v">265</subfield><subfield code="w">(DE-604)BV042385829</subfield><subfield code="9">265</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-3-319-01418-0</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Springer Fremddatenuebernahme</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=026917088&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Springer Fremddatenuebernahme</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=026917088&sequence=000003&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Abstract</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-026917088</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-01418-0</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-01418-0</subfield><subfield code="l">FHA01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-01418-0</subfield><subfield code="l">FHI01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-01418-0</subfield><subfield code="l">FHN01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-01418-0</subfield><subfield code="l">FHR01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-01418-0</subfield><subfield code="l">FKE01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-01418-0</subfield><subfield code="l">FRO01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-01418-0</subfield><subfield code="l">FWS01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-01418-0</subfield><subfield code="l">FWS02</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-01418-0</subfield><subfield code="l">UBY01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV041470946 |
| illustrated | Illustrated |
| indexdate | 2024-08-01T10:55:48Z |
| institution | BVB |
| isbn | 9783319014180 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-026917088 |
| oclc_num | 874381426 |
| open_access_boolean | |
| owner | DE-Aug4 DE-92 DE-634 DE-859 DE-898 DE-BY-UBR DE-573 DE-861 DE-706 DE-863 DE-BY-FWS DE-862 DE-BY-FWS |
| owner_facet | DE-Aug4 DE-92 DE-634 DE-859 DE-898 DE-BY-UBR DE-573 DE-861 DE-706 DE-863 DE-BY-FWS DE-862 DE-BY-FWS |
| physical | 1 Online-Ressource (XV, 221 p.) 94 illus., 57 illus. in color |
| psigel | ZDB-2-ENG |
| publishDate | 2014 |
| publishDateSearch | 2014 |
| publishDateSort | 2014 |
| record_format | marc |
| series | Lecture Notes in Electrical Engineering |
| series2 | Lecture Notes in Electrical Engineering |
| spellingShingle | Haase, Jan Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012 Lecture Notes in Electrical Engineering Formal Plausibility Checks for Environment -- Efficient Refinement Strategy Exploiting Component Properties in A CEGAR Process -- Formal Specification Level -- Power Estimation Methodology for SystemC -- SystemC Analysis for Nondeterminism Anomalies -- A Design and Verification Methodology for Mixed-Signal Systems Using SystemC-AMS -- Configurable Load Emulation Using FPGA and Power Amplifiers for Automotive Power ICs -- Model Based Design of Distributed Embedded Cyber Physical Systems -- Model-driven Methodology for the Development of Multi-level Executable Environments -- The Concept and Study of Grid Responsiveness -- Polynomial Metamodel-Based Fast Optimization of Nanoscale PLL Components -- Methodology and Example-Driven Interconnect Synthesis for Designing Heterogenous Coarse-Grain Reconfigurable Architectures Engineering Computer science Electronics Systems engineering Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation Informatik Ingenieurwissenschaften |
| title | Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012 |
| title_auth | Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012 |
| title_exact_search | Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012 |
| title_full | Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012 edited by Jan Haase |
| title_fullStr | Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012 edited by Jan Haase |
| title_full_unstemmed | Models, Methods, and Tools for Complex Chip Design Selected Contributions from FDL 2012 edited by Jan Haase |
| title_short | Models, Methods, and Tools for Complex Chip Design |
| title_sort | models methods and tools for complex chip design selected contributions from fdl 2012 |
| title_sub | Selected Contributions from FDL 2012 |
| topic | Engineering Computer science Electronics Systems engineering Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation Informatik Ingenieurwissenschaften |
| topic_facet | Engineering Computer science Electronics Systems engineering Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation Informatik Ingenieurwissenschaften |
| url | https://doi.org/10.1007/978-3-319-01418-0 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=026917088&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=026917088&sequence=000003&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV042385829 |
| work_keys_str_mv | AT haasejan modelsmethodsandtoolsforcomplexchipdesignselectedcontributionsfromfdl2012 |