Exploring Memory Hierarchy Design with Emerging Memory Technologies:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
2014
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| Schriftenreihe: | Lecture Notes in Electrical Engineering
267 |
| Schlagworte: | |
| Online-Zugang: | BTU01 FHA01 FHI01 FHN01 FHR01 FKE01 FRO01 FWS01 FWS02 UBY01 Volltext Inhaltsverzeichnis Abstract |
| Beschreibung: | This book equips readers with tools for computer architecture of high performance, low power, and high reliability memory hierarchy in computer systems based on emerging memory technologies, such as STTRAM, PCM, FBDRAM, etc. The techniques described offer advantages of high density, near-zero static power, and immunity to soft errors, which have the potential of overcoming the "memory wall." The authors discuss memory design from various perspectives: emerging memory technologies are employed in the memory hierarchy with novel architecture modification; hybrid memory structure is introduced to leverage advantages from multiple memory technologies; an analytical model named "Moguls" is introduced to explore quantitatively the optimization design of a memory hierarchy; finally, the vulnerability of the CMPs to radiation-based soft errors is improved by replacing different levels of on-chip memory with STT-RAMs. · Provides a holistic study of using emerging memory technologies in different levels of the memory hierarchy; · Equips readers with techniques for memory design with improved performance, energy consumption, and reliability; · Includes coverage of all memory levels, ranging from cache to storage; · Explains how to choose the proper memory technologies in different levels of the memory hierarchy |
| Beschreibung: | 1 Online-Ressource (VII, 122 p.) 71 illus., 57 illus. in color |
| ISBN: | 9783319006819 |
| DOI: | 10.1007/978-3-319-00681-9 |
Internformat
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| 500 | |a This book equips readers with tools for computer architecture of high performance, low power, and high reliability memory hierarchy in computer systems based on emerging memory technologies, such as STTRAM, PCM, FBDRAM, etc. The techniques described offer advantages of high density, near-zero static power, and immunity to soft errors, which have the potential of overcoming the "memory wall." The authors discuss memory design from various perspectives: emerging memory technologies are employed in the memory hierarchy with novel architecture modification; hybrid memory structure is introduced to leverage advantages from multiple memory technologies; an analytical model named "Moguls" is introduced to explore quantitatively the optimization design of a memory hierarchy; finally, the vulnerability of the CMPs to radiation-based soft errors is improved by replacing different levels of on-chip memory with STT-RAMs. · Provides a holistic study of using emerging memory technologies in different levels of the memory hierarchy; · Equips readers with techniques for memory design with improved performance, energy consumption, and reliability; · Includes coverage of all memory levels, ranging from cache to storage; · Explains how to choose the proper memory technologies in different levels of the memory hierarchy | ||
| 505 | 0 | |a Introduction -- Replacing Different Levels of the Memory Hierarchy with NVMs -- Moguls: a Model to Explore the Memory Hierarchy for Throughput Computing -- Exploring the Vulnerability of CMPs to Soft Errors with 3D Stacked Non-Volatile Memory | |
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Datensatz im Suchindex
| DE-BY-FWS_katkey | 1015589 |
|---|---|
| _version_ | 1806174832558080000 |
| adam_text | EXPLORING MEMORY HIERARCHY DESIGN WITH EMERGING MEMORY TECHNOLOGIES
/ SUN, GUANGYU
: 2014
TABLE OF CONTENTS / INHALTSVERZEICHNIS
INTRODUCTION
REPLACING DIFFERENT LEVELS OF THE MEMORY HIERARCHY WITH NVMS
MOGULS: A MODEL TO EXPLORE THE MEMORY HIERARCHY FOR THROUGHPUT COMPUTING
EXPLORING THE VULNERABILITY OF CMPS TO SOFT ERRORS WITH 3D STACKED
NON-VOLATILE MEMORY
DIESES SCHRIFTSTUECK WURDE MASCHINELL ERZEUGT.
EXPLORING MEMORY HIERARCHY DESIGN WITH EMERGING MEMORY TECHNOLOGIES
/ SUN, GUANGYU
: 2014
ABSTRACT / INHALTSTEXT
THIS BOOK EQUIPS READERS WITH TOOLS FOR COMPUTER ARCHITECTURE OF HIGH
PERFORMANCE, LOW POWER, AND HIGH RELIABILITY MEMORY HIERARCHY IN
COMPUTER SYSTEMS BASED ON EMERGING MEMORY TECHNOLOGIES, SUCH AS STTRAM,
PCM, FBDRAM, ETC. THE TECHNIQUES DESCRIBED OFFER ADVANTAGES OF HIGH
DENSITY, NEAR-ZERO STATIC POWER, AND IMMUNITY TO SOFT ERRORS, WHICH HAVE
THE POTENTIAL OF OVERCOMING THE “MEMORY WALL.” THE AUTHORS DISCUSS
MEMORY DESIGN FROM VARIOUS PERSPECTIVES: EMERGING MEMORY TECHNOLOGIES
ARE EMPLOYED IN THE MEMORY HIERARCHY WITH NOVEL ARCHITECTURE
MODIFICATION; HYBRID MEMORY STRUCTURE IS INTRODUCED TO LEVERAGE
ADVANTAGES FROM MULTIPLE MEMORY TECHNOLOGIES; AN ANALYTICAL MODEL NAMED
“MOGULS” IS INTRODUCED TO EXPLORE QUANTITATIVELY THE OPTIMIZATION
DESIGN OF A MEMORY HIERARCHY; FINALLY, THE VULNERABILITY OF THE CMPS TO
RADIATION-BASED SOFT ERRORS IS IMPROVED BY REPLACING DIFFERENT LEVELS OF
ON-CHIP MEMORY WITH STT-RAMS. PROVIDES A HOLISTIC
STUDY OF USING EMERGING MEMORY TECHNOLOGIES IN DIFFERENT LEVELS OF THE
MEMORY HIERARCHY; EQUIPS READERS WITH TECHNIQUES FOR
MEMORY DESIGN WITH IMPROVED PERFORMANCE, ENERGY CONSUMPTION, AND
RELIABILITY; INCLUDES COVERAGE OF ALL MEMORY LEVELS,
RANGING FROM CACHE TO STORAGE; EXPLAINS HOW TO CHOOSE
THE PROPER MEMORY TECHNOLOGIES IN DIFFERENT LEVELS OF THE MEMORY
HIERARCHY
DIESES SCHRIFTSTUECK WURDE MASCHINELL ERZEUGT.
|
| any_adam_object | 1 |
| author | Sun, Guangyu |
| author_facet | Sun, Guangyu |
| author_role | aut |
| author_sort | Sun, Guangyu |
| author_variant | g s gs |
| building | Verbundindex |
| bvnumber | BV041470914 |
| collection | ZDB-2-ENG |
| contents | Introduction -- Replacing Different Levels of the Memory Hierarchy with NVMs -- Moguls: a Model to Explore the Memory Hierarchy for Throughput Computing -- Exploring the Vulnerability of CMPs to Soft Errors with 3D Stacked Non-Volatile Memory |
| ctrlnum | (OCoLC)874381376 (DE-599)BVBBV041470914 |
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| dewey-ones | 621 - Applied physics |
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| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-3-319-00681-9 |
| format | Electronic eBook |
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| id | DE-604.BV041470914 |
| illustrated | Illustrated |
| indexdate | 2024-08-01T10:55:48Z |
| institution | BVB |
| isbn | 9783319006819 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-026917057 |
| oclc_num | 874381376 |
| open_access_boolean | |
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| owner_facet | DE-Aug4 DE-92 DE-634 DE-859 DE-898 DE-BY-UBR DE-573 DE-861 DE-706 DE-863 DE-BY-FWS DE-862 DE-BY-FWS |
| physical | 1 Online-Ressource (VII, 122 p.) 71 illus., 57 illus. in color |
| psigel | ZDB-2-ENG |
| publishDate | 2014 |
| publishDateSearch | 2014 |
| publishDateSort | 2014 |
| record_format | marc |
| series | Lecture Notes in Electrical Engineering |
| series2 | Lecture Notes in Electrical Engineering |
| spellingShingle | Sun, Guangyu Exploring Memory Hierarchy Design with Emerging Memory Technologies Lecture Notes in Electrical Engineering Introduction -- Replacing Different Levels of the Memory Hierarchy with NVMs -- Moguls: a Model to Explore the Memory Hierarchy for Throughput Computing -- Exploring the Vulnerability of CMPs to Soft Errors with 3D Stacked Non-Volatile Memory Engineering Computer science Systems engineering Circuits and Systems Processor Architectures Semiconductors Informatik Ingenieurwissenschaften |
| title | Exploring Memory Hierarchy Design with Emerging Memory Technologies |
| title_auth | Exploring Memory Hierarchy Design with Emerging Memory Technologies |
| title_exact_search | Exploring Memory Hierarchy Design with Emerging Memory Technologies |
| title_full | Exploring Memory Hierarchy Design with Emerging Memory Technologies by Guangyu Sun |
| title_fullStr | Exploring Memory Hierarchy Design with Emerging Memory Technologies by Guangyu Sun |
| title_full_unstemmed | Exploring Memory Hierarchy Design with Emerging Memory Technologies by Guangyu Sun |
| title_short | Exploring Memory Hierarchy Design with Emerging Memory Technologies |
| title_sort | exploring memory hierarchy design with emerging memory technologies |
| topic | Engineering Computer science Systems engineering Circuits and Systems Processor Architectures Semiconductors Informatik Ingenieurwissenschaften |
| topic_facet | Engineering Computer science Systems engineering Circuits and Systems Processor Architectures Semiconductors Informatik Ingenieurwissenschaften |
| url | https://doi.org/10.1007/978-3-319-00681-9 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=026917057&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=026917057&sequence=000003&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA |
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