Routing Algorithms in Networks-on-Chip:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
2014
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| Schlagworte: | |
| Online-Zugang: | BTU01 FHA01 FHI01 FHN01 FHR01 FKE01 FRO01 FWS01 FWS02 UBY01 Volltext |
| Beschreibung: | This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation. Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability. · Provides a comprehensive overview of routing algorithms for Networks-on-Chip and NoC-based, manycore systems; · Describes routing algorithms for NoC architectures at all abstraction levels, from the algorithmic level to actual implementation; · Discusses the impact on NoC routing algorithms of key design objectives, such as power dissipation, energy consumption, thermal aspects, reliability, and performance |
| Beschreibung: | 1 Online-Ressource (XIV, 410 p.) 219 illus., 97 illus. in color |
| ISBN: | 9781461482741 |
| DOI: | 10.1007/978-1-4614-8274-1 |
Internformat
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| 500 | |a This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation. Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability. · Provides a comprehensive overview of routing algorithms for Networks-on-Chip and NoC-based, manycore systems; · Describes routing algorithms for NoC architectures at all abstraction levels, from the algorithmic level to actual implementation; · Discusses the impact on NoC routing algorithms of key design objectives, such as power dissipation, energy consumption, thermal aspects, reliability, and performance | ||
| 505 | 0 | |a Part I Performance Improvement -- Basic Concepts on On-Chip Networks -- A Heuristic Framework for Designing and Exploring Deterministic Routing Algorithm for NoCs -- Run-Time Deadlock Detection -- The Abacus Turn Model -- Learning-based Routing Algorithms for on-Chip Networks -- Part II Multicast Communication -- Efficient and Deadlock-Free Tree-based Multicast Routing Method for Network-on-Chip -- Path-based Multicast Routing for 2D and 3D Mesh Networks -- Part III Fault Tolerance and Reliability -- Fault-Tolerant Routing Algorithms in Networks-on-Chip -- Reliable and Adaptive Algorithms for 2D and 3D Networks-on-Chip | |
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| 650 | 4 | |a Circuits and Systems | |
| 650 | 4 | |a Processor Architectures | |
| 650 | 4 | |a Electronics and Microelectronics, Instrumentation | |
| 650 | 4 | |a Informatik | |
| 650 | 4 | |a Ingenieurwissenschaften | |
| 700 | 1 | |a Daneshtalab, Masoud |e Sonstige |4 oth | |
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Datensatz im Suchindex
| DE-BY-FWS_katkey | 1016032 |
|---|---|
| _version_ | 1806174845476536320 |
| any_adam_object | |
| author | Palesi, Maurizio |
| author_facet | Palesi, Maurizio |
| author_role | aut |
| author_sort | Palesi, Maurizio |
| author_variant | m p mp |
| building | Verbundindex |
| bvnumber | BV041470887 |
| collection | ZDB-2-ENG |
| contents | Part I Performance Improvement -- Basic Concepts on On-Chip Networks -- A Heuristic Framework for Designing and Exploring Deterministic Routing Algorithm for NoCs -- Run-Time Deadlock Detection -- The Abacus Turn Model -- Learning-based Routing Algorithms for on-Chip Networks -- Part II Multicast Communication -- Efficient and Deadlock-Free Tree-based Multicast Routing Method for Network-on-Chip -- Path-based Multicast Routing for 2D and 3D Mesh Networks -- Part III Fault Tolerance and Reliability -- Fault-Tolerant Routing Algorithms in Networks-on-Chip -- Reliable and Adaptive Algorithms for 2D and 3D Networks-on-Chip |
| ctrlnum | (OCoLC)865039314 (DE-599)BVBBV041470887 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4614-8274-1 |
| format | Electronic eBook |
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| id | DE-604.BV041470887 |
| illustrated | Illustrated |
| indexdate | 2024-08-01T10:56:00Z |
| institution | BVB |
| isbn | 9781461482741 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-026917029 |
| oclc_num | 865039314 |
| open_access_boolean | |
| owner | DE-Aug4 DE-92 DE-634 DE-859 DE-898 DE-BY-UBR DE-573 DE-861 DE-706 DE-863 DE-BY-FWS DE-862 DE-BY-FWS |
| owner_facet | DE-Aug4 DE-92 DE-634 DE-859 DE-898 DE-BY-UBR DE-573 DE-861 DE-706 DE-863 DE-BY-FWS DE-862 DE-BY-FWS |
| physical | 1 Online-Ressource (XIV, 410 p.) 219 illus., 97 illus. in color |
| psigel | ZDB-2-ENG |
| publishDate | 2014 |
| publishDateSearch | 2014 |
| publishDateSort | 2014 |
| record_format | marc |
| spellingShingle | Palesi, Maurizio Routing Algorithms in Networks-on-Chip Part I Performance Improvement -- Basic Concepts on On-Chip Networks -- A Heuristic Framework for Designing and Exploring Deterministic Routing Algorithm for NoCs -- Run-Time Deadlock Detection -- The Abacus Turn Model -- Learning-based Routing Algorithms for on-Chip Networks -- Part II Multicast Communication -- Efficient and Deadlock-Free Tree-based Multicast Routing Method for Network-on-Chip -- Path-based Multicast Routing for 2D and 3D Mesh Networks -- Part III Fault Tolerance and Reliability -- Fault-Tolerant Routing Algorithms in Networks-on-Chip -- Reliable and Adaptive Algorithms for 2D and 3D Networks-on-Chip Engineering Computer science Electronics Systems engineering Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation Informatik Ingenieurwissenschaften |
| title | Routing Algorithms in Networks-on-Chip |
| title_auth | Routing Algorithms in Networks-on-Chip |
| title_exact_search | Routing Algorithms in Networks-on-Chip |
| title_full | Routing Algorithms in Networks-on-Chip edited by Maurizio Palesi, Masoud Daneshtalab |
| title_fullStr | Routing Algorithms in Networks-on-Chip edited by Maurizio Palesi, Masoud Daneshtalab |
| title_full_unstemmed | Routing Algorithms in Networks-on-Chip edited by Maurizio Palesi, Masoud Daneshtalab |
| title_short | Routing Algorithms in Networks-on-Chip |
| title_sort | routing algorithms in networks on chip |
| topic | Engineering Computer science Electronics Systems engineering Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation Informatik Ingenieurwissenschaften |
| topic_facet | Engineering Computer science Electronics Systems engineering Circuits and Systems Processor Architectures Electronics and Microelectronics, Instrumentation Informatik Ingenieurwissenschaften |
| url | https://doi.org/10.1007/978-1-4614-8274-1 |
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