Generating analog IC layouts with LAYGEN II:
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Heidelberg [u.a.]
Springer
2013
|
| Schriftenreihe: | SpringerBriefs in applied sciences and technology : Computational intelligence
|
| Schlagworte: | |
| Online-Zugang: | Inhaltstext Inhaltsverzeichnis |
| Beschreibung: | XI, 98 S. Ill., graph. Darst. |
| ISBN: | 9783642331459 |
Internformat
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Datensatz im Suchindex
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IMAGE 1
CONTENTS
1 INTRODUCTION 1
1.1 ANALOG IC DESIGN 1
1.2 THE ANALOG IC DESIGN AUTOMATION FLOW 3
1.3 ANALOG IC LAYOUT AUTOMATION 5
1.4 CONCLUSIONS 6
REFERENCES 6
2 STATE O F THE ART ON ANALOG LAYOUT AUTOMATION 9
2.1 PLACEMENT 9
2.1.1 LAYOUT CONSTRAINTS 10
2.1.2 CHIP FLOORPLAN REPRESENTATIONS 10
2.1.3 APPROACHES 15
2.2 LAYOUT GENERATION TOOLS 16
2.3 CLOSING THE GAP BETWEEN ELECTRICAL AND PHYSICAL DESIGN 17
2.3.1 LAYOUT-AWARE SIZING APPROACHES 19
2.4 COMMERCIAL TOOLS 21
2.5 CONCLUSIONS 24
REFERENCES 25
3 AUTOMATIC LAYOUT GENERATION 29
3.1 DESIGN FLOW BASED ON AUTOMATIC GENERATION 29
3.1.1 SIZING TASK 31
3.2 LAYOUT GENERATION DESIGN FLOW 32
3.3 TOOL ARCHITECTURE 33
3.3.1 GRAPHICAL USER INTERFACE 35
3.3.2 TECHNOLOGY DESIGN KIT 37
3.3.3 HIERARCHICAL HIGH LEVEL CELL DESCRIPTION 37
3.4 CONCLUSIONS 39
REFERENCES 39
I X
HTTP://D-NB.INFO/1024863883
IMAGE 2
X CONTENTS
4 PLACER 41
4.1 PLACER ARCHITECTURE 41
4.2 TEMPLATE 42
4.3 TEMPLATE-BASED GENERATION PROCEDURE 43
4.3.1 INSTANTIATION 45
4.3.2 PRE-PROCESSING 45
4.3.3 POST-PROCESSING 50
4.4 CONCLUSIONS 53
REFERENCES 54
5 ROUTER 55
5.1 ROUTER ARCHITECTURE 55
5.2 TEMPLATE 57
5.3 OPTIMIZATION-BASED GENERATION PROCEDURE 60
5.3.1 MULTIPLE CONTACTS 60
5.3.2 EVOLUTIONARY ALGORITHM 61
5.3.3 OPTIMIZATION PHASES 69
5.4 INTERNAL EVALUATION PROCEDURE 71
5.4.1 SHORT CIRCUIT CHECKER 71
5.4.2 DESIGN RULE CHECKER 72
5.4.3 ELECTRICAL RULE CHECKER 73
5.5 CONCLUSIONS 74
REFERENCES 75
6 RESULTS 77
6.1 CASE STUDY I: FULLY-DYNAMIC COMPARATOR 77
6.1.1 TEMPLATE 79
6.1.2 LAYOUT GENERATION 79
6.1.3 VALIDATION 83
6.2 CASE STUDY II: SINGLE-ENDED FOLDED CASCODE AMPLIFIER 85
6.2.1 TEMPLATE HIERARCHY 85
6.2.2 LAYOUT GENERATION 86
6.2.3 RETARGETING FOR DIFFERENT SIZES 87
6.2.4 RETARGETING FOR DIFFERENT TECHNOLOGY 91
6.3 CONCLUSIONS 92
REFERENCES 92
7 CONCLUSIONS AND FUTURE WORK 95
7.1 CONCLUSIONS 95
7.2 FUTURE WORK 96
REFERENCES 98 |
| any_adam_object | 1 |
| author | Martins, Ricardo M. F. Lourenço, Nuno C. C. Horta, Nuno C. G. |
| author_facet | Martins, Ricardo M. F. Lourenço, Nuno C. C. Horta, Nuno C. G. |
| author_role | aut aut aut |
| author_sort | Martins, Ricardo M. F. |
| author_variant | r m f m rmf rmfm n c c l ncc nccl n c g h ncg ncgh |
| building | Verbundindex |
| bvnumber | BV041257307 |
| classification_rvk | ZN 4904 |
| ctrlnum | (OCoLC)855546439 (DE-599)DNB1024863883 |
| dewey-full | 621.3815028553 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815028553 |
| dewey-search | 621.3815028553 |
| dewey-sort | 3621.3815028553 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| spelling | Martins, Ricardo M. F. Verfasser aut Generating analog IC layouts with LAYGEN II Ricardo M. F. Martins ; Nuno C. C. Lourenço ; Nuno C. G. Horta Heidelberg [u.a.] Springer 2013 XI, 98 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier SpringerBriefs in applied sciences and technology : Computational intelligence Layout Mikroelektronik (DE-588)4264372-7 gnd rswk-swf Template (DE-588)4265509-2 gnd rswk-swf Softwarewerkzeug (DE-588)4116526-3 gnd rswk-swf Analoge integrierte Schaltung (DE-588)4112519-8 gnd rswk-swf Evolutionärer Algorithmus (DE-588)4366912-8 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf Analoge integrierte Schaltung (DE-588)4112519-8 s Entwurfsautomation (DE-588)4312536-0 s Layout Mikroelektronik (DE-588)4264372-7 s Template (DE-588)4265509-2 s Evolutionärer Algorithmus (DE-588)4366912-8 s Softwarewerkzeug (DE-588)4116526-3 s DE-604 Lourenço, Nuno C. C. Verfasser aut Horta, Nuno C. G. Verfasser aut Erscheint auch als Online-Ausgabe 978-3-642-33146-6 X:MVB text/html http://deposit.dnb.de/cgi-bin/dokserv?id=4096305&prov=M&dok_var=1&dok_ext=htm Inhaltstext DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=026231213&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Martins, Ricardo M. F. Lourenço, Nuno C. C. Horta, Nuno C. G. Generating analog IC layouts with LAYGEN II Layout Mikroelektronik (DE-588)4264372-7 gnd Template (DE-588)4265509-2 gnd Softwarewerkzeug (DE-588)4116526-3 gnd Analoge integrierte Schaltung (DE-588)4112519-8 gnd Evolutionärer Algorithmus (DE-588)4366912-8 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
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| title | Generating analog IC layouts with LAYGEN II |
| title_auth | Generating analog IC layouts with LAYGEN II |
| title_exact_search | Generating analog IC layouts with LAYGEN II |
| title_full | Generating analog IC layouts with LAYGEN II Ricardo M. F. Martins ; Nuno C. C. Lourenço ; Nuno C. G. Horta |
| title_fullStr | Generating analog IC layouts with LAYGEN II Ricardo M. F. Martins ; Nuno C. C. Lourenço ; Nuno C. G. Horta |
| title_full_unstemmed | Generating analog IC layouts with LAYGEN II Ricardo M. F. Martins ; Nuno C. C. Lourenço ; Nuno C. G. Horta |
| title_short | Generating analog IC layouts with LAYGEN II |
| title_sort | generating analog ic layouts with laygen ii |
| topic | Layout Mikroelektronik (DE-588)4264372-7 gnd Template (DE-588)4265509-2 gnd Softwarewerkzeug (DE-588)4116526-3 gnd Analoge integrierte Schaltung (DE-588)4112519-8 gnd Evolutionärer Algorithmus (DE-588)4366912-8 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
| topic_facet | Layout Mikroelektronik Template Softwarewerkzeug Analoge integrierte Schaltung Evolutionärer Algorithmus Entwurfsautomation |
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