Structured computer organization:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boston, Mass. ; Munich [u.a.]
Pearson
2013
|
| Ausgabe: | 6. ed., internat. ed. |
| Schriftenreihe: | Always learning
|
| Schlagworte: | |
| Online-Zugang: | Ausführliche Beschreibung Inhaltsverzeichnis |
| Beschreibung: | Includes bibliographical references and index |
| Beschreibung: | XXII, 775 S. Ill., graph. Darst. 24 cm |
| ISBN: | 0273769243 9780273769248 9780273785019 |
Internformat
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| 245 | 1 | 0 | |a Structured computer organization |c Andrew S. Tanenbaum ; Todd Austin |
| 250 | |a 6. ed., internat. ed. | ||
| 264 | 1 | |a Boston, Mass. ; Munich [u.a.] |b Pearson |c 2013 | |
| 300 | |a XXII, 775 S. |b Ill., graph. Darst. |c 24 cm | ||
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| adam_text | CONTENTS
PREFACE xix
1 INTRODUCTION
1.1 STRUCTURED COMPUTER ORGANIZATION 2
1.1.1 Languages, Levels, and Virtual Machines 2
1.1.2 Contemporary Multilevel Machines 5
1.1.3 Evolution of Multilevel Machines 8
1.2 MILESTONES IN COMPUTER ARCHITECTURE 13
1.2.1 The Zeroth Generation—Mechanical Computers (1642-1945) 13
1.2.2 The First Generation—Vacuum Tubes (1945-1955) 16
1.2.3 The Second Generation—Transistors (1955-1965) 19
1.2.4 The Third Generation—Integrated Circuits (1965-1980) 21
1.2.5 The Fourth Generation—Very Large Scale Integration (1980-?) 23
1.2.6 The Fifth Generation—Low-Power and Invisible Computers 26
1.3 THE COMPUTER ZOO 28
1.3.1 Technological and Economic Forces 28
1.3.2 The Computer Spectrum 30
1.3.3 Disposable Computers 31
1.3.4 Microcontrollers 33
1.3.5 Mobile and Game Computers 35
1.3.6 Personalcomputers 36
1.3.7 Servers 36
1.3.8 Mainframes 3 8
vii
VIII
CONTENTS
1.4 EX A M PIAi COMPUTI{R FAMILIES 39
1.4.1 Introduction to the x86 Architecture 39
1.4.2 Introduction to the ARM Architecture 45
1.4.3 Introduction to the AVR Architecture 47
1.5 METRIC UNITS 49
1.6 OUTLINE OF THIS BOOK 50
2 COMPUTER SYSTEMS
2.1 PROCESSORS 55
2.1.1 CPU Organization 56
2.1.2 Instruction Execution 58
2.1.3 RISC versus CISC 62
2.1.4 Design Principles for Modern Computers 63
2.1.5 Instruction-Level Parallelism 65
2.1.6 Processor-Level Parallelism 69
2.2 PRIMARY MEMORY 73
2.2.1 Bits 74
2.2.2 Memory Addresses 74
2.2.3 Byte Ordering 76
2.2.4 Error-Correcting Codes 78
2.2.5 Cache Memory 82
2.2.6 Memory Packaging and Types 85
2.3 SECONDARY MEMORY 86
2.3.1 Memory Hierarchies 86
2.3.2 Magnetic Disks 87
2.3.3 IDE Disks 91
2.3.4 SCSI Disks 92
2.3.5 RAID 94
2.3.6 Solid-State Disks 97
2.3.7 CD-ROMs 99
2.3.8 CD-Recordables 103
2.3.9 CD-Rewritables 105
2.3.10 DVD 106
2.3.11 Blu-ray 108
CONTENTS
ix
2.4 INPUT/OUTPUT 108
2.4.1 Buses 108
2.4.2 Terminals 113
2.4.3 Mice 118
2.4.4 Game Controllers 120
2.4.5 Printers 122
2.4.6 Telecommunications Equipment 127
2.4.7 Digital Cameras 135
2.4.8 Character Codes 137
2.5 SUMMARY 142
3 THE DIGITAL LOGIC LEVEL
3.1 GATES AND BOOLEAN ALGEBRA 147
3.1.1 Gates 148
3.1.2 Boolean Algebra 150
3.1.3 Implementation of Boolean Functions 152
3.1.4 Circuit Equivalence 153
3.2 BASIC DIGITAL LOGIC CIRCUITS 158
3.2.1 Integrated Circuits 158
3.2.2 Combinational Circuits 159
3.2.3 Arithmetic Circuits 163
3.2.4 Clocks 168
3.3 MEMORY 169
3.3.1 Latches 169
3.3.2 Flip-Flops 172
3.3.3 Registers 174
3.3.4 Memory Organization 174
3.3.5 Memory Chips 178
3.3.6 RAMs and ROMs 180
3.4 CPU CHIPS AND BUSES 185
3.4.1 CPU Chips 185
3.4.2 Computer Buses 187
3.4.3 Bus Width 190
3.4.4 Bus Clocking 191
3.4.5 Bus Arbitration 196
3.4.6 Bus Operations 198
CONTENTS
3.5 EXAMPLE ( I’Ll (’HIPS 201
3.5.1 The Inicl Core i7 201
3.5.2 I’lic Texas Instruments OMAP4430 Syslem-on-a-Chip 208
3.5.3 The Almcl ATmega168 Microcontroller 212
3.0 EXAMPLE BUSHS 214
3.6.1 The PCI Bus 215
3.6.2 PCI Express 22.3
3.6.3 The Universal Serial Bus 228
3.7 INTERFACING 232
3.7.1 I/O Interlaces 232
3.7.2 Address Decoding 233
3.8 SUMMARY 2.35
4 THE MICROARCHITECTURE LEVEL
4.1 AN EXAMPLE MICROARCHITECTURE 243
4.1.1 The Data Path 244
4.1.2 Microinstructions 251
4.1.3 Microinstruction Control: The Mic-1 253
4.2 AN EXAMPLE ISA: IJVM 258
4.2.1 Stacks 258
4.2.2 The IJVM Memory Model 260
4.2.3 The IJVM Instruction Set 262
4.2.4 Compiling Java to IJVM 265
4.3 AN EXAMPLE IMPLEMENTATION 267
4.3.1 Microinstructions and Notation 267
4.3.2 Implementation of IJVM Using the Mic-1 271
4.4 DESIGN OF THE MICROARCHITECTURE LEVEL 283
4.4.1 Speed versus Cost 283
4.4.2 Reducing the Execution Path Length 285
4.4.3 A Design with Prefetching: The Mic-2 291
4.4.4 A Pipelined Design: The Mic-3 293
4.4.5 A Seven-Stage Pipeline: The Mic-4 300
CONTENTS
XI
4.5 IMPROVING PERFORMANCE 303
4.5.1 Cache Memory 304
4.5.2 Branch Prediction 310
4.5.3 Out-of-Order Execution and Register Renaming 315
4.5.4 Speculative Execution 320
4.6 EXAMPLES OF THE MICROARCHITECTURE LEVEL 32.3
4.6.1 The Microarchitecture of the Core i7 CPU 323
4.6.2 The Microarchitecture of the OMAP4430 CPU 329
4.6.3 The Microarchitecture of the ATmegal68 Microcontroller 334
4.7 COMPARISON OF THE 17, OMAP4430, AND ATMEGA168 336
4.8 SUMMARY 337
THE INSTRUCTION SET
5.1 OVERVIEW OF THE ISA LEVEL 345
5.1.1 Properties of the ISA Level 345
5.1.2 Memory Models 347
5.1.3 Registers 349
5.1.4 Instructions 351
5.1.5 Overview of the Core i7 ISA Level 351
5.1.6 Overview of the OMAP4430 ARM ISA Level 354
5.1.7 Overview of the ATmegal68 AVR ISA Level 356
5.2 DATATYPES 358
5.2.1 Numeric Data Types 358
5.2.2 Nonnumeric Data Types 359
5.2.3 Data Types on the Core i7 360
5.2.4 Data Types on the OMAP4430 ARM CPU 361
5.2.5 Data Types on the ATmegal 68 AVR CPU 361
5.3 INSTRUCTION FORMATS 362
5.3.1 Design Criteria for Instruction Formats 362
5.3.2 Expanding Opcodes 365
5.3.3 The Core i7 Instruction Formats 367
5.3.4 The OMAP4430 ARM CPU Instruction Formats 368
5.3.5 The ATmegal68 AVR Instruction Formats 370
xn
CONTENTS
5.4 ADDRESSING 371
5.4.1 Addressing Modes 371
5.4.2 Immedinle Addressing 372
5.4.3 I)ireel Addressing 372
5.4.4 Register Addressing 372
5.4.5 Register Indirect Addressing 373
5.4.6 Indexed Addressing 374
5.4.7 Based-Indexed Addressing 376
5.4.8 Slack Addressing 376
5.4.9 Addressing Modes for Branch Instructions 379
5.4.10 Orthogonality of Opcodes and Addressing Modes 380
5.4.1 I The Core ¡7 Addressing Modes 382
5.4.12 The OMAP4440 ARM CPU Addressing Modes 384
5.4.13 The ATmcga 168 AVR Addressing Modes 384
5.4.14 Discussion of Addressing Modes 385
5.5 INSTRUCTION TYPES 386
5.5.1 Data Movement Instructions 386
5.5.2 Dyadic Operations 387
5.5.3 Monadic Operations 388
5.5.4 Comparisons and Conditional Branches 390
5.5.5 Procedure Call Instructions 392
5.5.6 Loop Control 393
5.5.7 Input/Output 394
5.5.8 The Core i7 Instructions 397
5.5.9 The OMAP4430 ARM CPU Instructions 400
5.5.10 The ATmegal 68 AVR Instructions 402
5.5.11 Comparison of Instruction Sets 402
5.6 FLOW OF CONTROL 404
5.6.1 Sequential Flow of Control and Branches 405
5.6.2 Procedures 406
5.6.3 Coroutines 410
5.6.4 Traps 413
5.6.5 Interrupts 414
5.7 A DETAILED EXAMPLE: THE TOWERS OF HANOI 417
5.7.1 The Towers of Hanoi in Core i7 Assembly Language 418
5.7.2 The Towers of Hanoi in OMAP4430 ARM Assembly Language 418
CONTENTS
Xlll
5.8 THEIA-64 ARCHITECTURE AND THE ITANIUM 2 420
5.8.1 The Problem with the IA-32 ISA 421
5.8.2 The IA-64 Model: Explicitly Parallel Instruction Computing 423
5.8.3 Reducing Memory References 423
5.8.4 Instruction Scheduling 424
5.8.5 Reducing Conditional Branches: Predication 426
5.8.6 Speculative Loads 429
5.9 SUMMARY 430
6 THE OPERATING SYSTEM
6.1 VIRTUAL MEMORY 438
6.1.1 Paging 439
6.1.2 Implementation of Paging 441
6.1.3 Demand Paging and the Working-Set Model 443
6.1.4 Page-Replacement Policy 446
6.1.5 Page Size and Fragmentation 448
6.1.6 Segmentation 449
6.1.7 Implementation of Segmentation 452
6.1.8 Virtual Memory on the Core i7 455
6.1.9 Virtual Memory on the OMAP4430 ARM CPU 460
6.1.10 Virtual Memory and Caching 462
6.2 HARDWARE VIRTUALIZATION 463
6.2.1 Hardware Virtualization on the Core 17 464
6.3 OSM-LEVEL I/O INSTRUCTIONS 465
6.3.1 Files 465
6.3.2 Implementation of OSM-Level I/O Instructions 467
6.3.3 Directory Management Instructions 471
6.4 OSM-LEVEL INSTRUCTIONS FOR PARALLEL PROCESSING 471
6.4.1 Process Creation 473
6.4.2 Race Conditions 473
6.4.3 Process Synchronization Using Semaphores 478
6.5 EXAMPLE OPERATING SYSTEMS 480
6.5.1 Introduction 482
6.5.2 Examples of Virtual Memory 488
XIV
CONTENTS
(0.3 lixiimplcs of OS-LcvcI I/O 492
(0.4 I Examples of Process Management 503
(O SUMMARY 509
7 THE ASSEMBLY LANGUAGE LEVEL
7.1 INTRODUCTION TO ASSEMBLY LANGUAGE 518
7.1.1 What Is an Assembly Language? 518
7.1.2 Why Use Assembly Language? 519
7.1.3 Format of an Assembly Language Statement 520
7.1.4 Pseudoinstructions 522
7.2 MACROS 524
7.2.1 Macro Definition, Call, and Expansion 524
7.2.2 Macros with Parameters 526
7.2.3 Advanced Features 527
7.2.4 Implementation of a Macro Facility in an Assembler 528
7.3 THE ASSEMBLY PROCESS 529
7.3.1 Two-Pass Assemblers 529
7.3.2 Pass One 530
7.3.3 Pass Two 534
7.3.4 The Symbol Table 535
7.4 LINKING AND LOADING 536
7.4.1 Tasks Performed by the Linker 538
7.4.2 Structure of an Object Module 541
7.4.3 Binding Time and Dynamic Relocation 542
7.4.4 Dynamic Linking 545
7.5 SUMMARY 549
8 PARALLEL COMPUTER ARCHITECTURES
8.1 ON-CHIP PARALELLISM 554
8.1.1 Instruction-Level Parallelism 555
8.1.2 On-Chip Multithreading 562
8.1.3 Single-Chip Multiprocessors 568
CONTENTS
XV
8.2 COPROCESSORS 574
8.2.1 Network Processors 574
8.2.2 Graphics Processors 582
8.2.3 Cryptoprocessors 585
8.3 SHARED-MEMORY MULTIPROCESSORS 586
8.3.1 Multiprocessors vs. Multicomputers 586
8.3.2 Memory Semantics 593
8.3.3 UMA Symmetric Multiprocessor Architectures 598
8.3.4 NUMA Multiprocessors 606
8.3.4 COMA Multiprocessors 615
8.4 MESSAGE-PASSING MULTICOMPUTERS 616
7.4.1 Interconnection Networks 618
8.4.2 MPPs—Massively Parallel Processors 621
8.4.3 Cluster Computing 631
8.4.4 Communication Software for Multicomputers 636
8.4.5 Scheduling 639
8.4.6 Application-Level Shared Memory 640
8.4.7 Performance 646
8.5 GRID COMPUTING 652
8.6 SUMMARY 655
9 BIBLIOGRAPHY 659
A BINARY NUMBERS 669
A.l FINITE-PRECISION NUMBERS 669
A.2 RADIX NUMBER SYSTEMS 671
A.3 CONVERSION FROM ONE RADIX TO ANOTHER 673
A.4 NEGATIVE BINARY NUMBERS 675
A.5 BINARY ARITHMETIC 678
XVI
CONTENTS
B FLOATING-POINT NUMBERS
B.l PRINCIPLES OF FLOATING POINT 682
B.2 IEEE FLOATING-POINT STANDARD 754 684
C ASSEMBLY LANGUAGE PROGRAMMING
C.l OVERVIEW 692
C. 1.1 Assembly Language 692
C.1.2 A Small Assembly Language Program 693
C.2 THE 8088 PROCESSOR 694
C.2.1 The Processor Cycle 695
C.2.2 The General Registers 695
C.2.3 Pointer Registers 698
C.3 MEMORY AND ADDRESSING 699
C.3.1 Memory Organization and Segments 699
C.3.2 Addressing 701
C.4 THE 8088 INSTRUCTION SET 705
C.4.1 Move, Copy and Arithmetic 705
C.4.2 Logical, Bit and Shift Operations 708
C.4.3 Loop and Repetitive String Operations 708
C.4.4 Jump and Call Instructions 709
C.4.5 Subroutine Calls 710
C.4.6 System Calls and System Subroutines 712
C.4.7 Final Remarks on the Instruction Set 715
C.5 THE ASSEMBLER 715
C.5.1 Introduction 715
C.5.2 The ACK-Based Tutorial Assembler as88 716
C.5.3 Some Differences with Other 8088 Assemblers 720
C.6 THE TRACER 721
C.6.1 Tracer Commands 723
C.7 GETTING STARTED 725
CONTENTS
xvii
C.8 EXAMPLES 726
C.8.1 Hello World Example 726
C.8,2 General Registers Example 729
C.8.3 Call Command and Pointer Registers 730
C.8.4 Debugging an Array Print Program 734
C.8.5 String Manipulation and String Instructions 736
C.8.6 Dispatch Tables 740
C.8.7 Buffered and Random File Access 742
INDEX
747
|
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| genre | 1\p (DE-588)4123623-3 Lehrbuch gnd-content |
| genre_facet | Lehrbuch |
| id | DE-604.BV040916777 |
| illustrated | Illustrated |
| indexdate | 2025-02-20T06:44:37Z |
| institution | BVB |
| isbn | 0273769243 9780273769248 9780273785019 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-025895999 |
| oclc_num | 844041758 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM DE-83 DE-92 DE-634 DE-863 DE-BY-FWS DE-860 DE-473 DE-BY-UBG DE-2070s DE-11 DE-703 DE-573 DE-20 |
| owner_facet | DE-91G DE-BY-TUM DE-83 DE-92 DE-634 DE-863 DE-BY-FWS DE-860 DE-473 DE-BY-UBG DE-2070s DE-11 DE-703 DE-573 DE-20 |
| physical | XXII, 775 S. Ill., graph. Darst. 24 cm |
| publishDate | 2013 |
| publishDateSearch | 2013 |
| publishDateSort | 2013 |
| publisher | Pearson |
| record_format | marc |
| series2 | Always learning |
| spellingShingle | Tanenbaum, Andrew S. 1944- Austin, Todd Structured computer organization Betriebssystem (DE-588)4006216-8 gnd Datenverarbeitung (DE-588)4011152-0 gnd Computerarchitektur (DE-588)4048717-9 gnd Rechnerorganisation (DE-588)4177175-8 gnd Computer (DE-588)4070083-5 gnd |
| subject_GND | (DE-588)4006216-8 (DE-588)4011152-0 (DE-588)4048717-9 (DE-588)4177175-8 (DE-588)4070083-5 (DE-588)4123623-3 |
| title | Structured computer organization |
| title_auth | Structured computer organization |
| title_exact_search | Structured computer organization |
| title_full | Structured computer organization Andrew S. Tanenbaum ; Todd Austin |
| title_fullStr | Structured computer organization Andrew S. Tanenbaum ; Todd Austin |
| title_full_unstemmed | Structured computer organization Andrew S. Tanenbaum ; Todd Austin |
| title_short | Structured computer organization |
| title_sort | structured computer organization |
| topic | Betriebssystem (DE-588)4006216-8 gnd Datenverarbeitung (DE-588)4011152-0 gnd Computerarchitektur (DE-588)4048717-9 gnd Rechnerorganisation (DE-588)4177175-8 gnd Computer (DE-588)4070083-5 gnd |
| topic_facet | Betriebssystem Datenverarbeitung Computerarchitektur Rechnerorganisation Computer Lehrbuch |
| url | http://www.pearsoned.co.uk/bookshop/detail.asp?WT.oss=9780273769248&WT.oss_r=1&item=100000000460156 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=025895999&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT tanenbaumandrews structuredcomputerorganization AT austintodd structuredcomputerorganization |
Inhaltsverzeichnis
THWS Würzburg Teilbibliothek SHL, Raum I.2.11
| Signatur: |
1340 ST 150 T164(6) |
|---|---|
| Exemplar 1 | ausleihbar Verfügbar Bestellen |