UTLEON3: Exploring fine-grain multi-threading in FPGAs:
<p>This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-sta...
Gespeichert in:
Format: | Elektronisch E-Book |
---|---|
Sprache: | English |
Veröffentlicht: |
New York, NY [u.a.]
Springer
2013
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Schlagworte: | |
Online-Zugang: | BTU01 FHA01 FHI01 FHN01 FHR01 FKE01 FWS01 UBY01 Volltext Inhaltsverzeichnis Abstract |
Zusammenfassung: | <p>This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs. </p><ul><li>Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch;</li><li>Provides VHDL sources for the described processor;</li><li>Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines;</li><li>Includes programming by example in the micro-threaded assembly language.</li></ul><p> </p><p> </p> |
Beschreibung: | Introduction -- The LEON3 Processor -- Microthreaded Extensions -- The Basic UTLEON3 Architecture.- UTLEON3 Programming by Example -- UTLEON3 Implementation Details -- Execution Effieciency of the Microthread Pipeline.- Hardware Families of Threads -- I/O and Interrupt Handling in the Microthread Mode -- The IU3 Pipeline -- Excerpts from the LEON3 Instruction Set -- Relevant LEON3 Registers and Address Space Identifiers.- Scheduler Example -- Used Resources -- Tutorial |
Beschreibung: | 1 Online-Ressource (XVIII, 219 p. 122 illus) |
ISBN: | 9781461424109 |
DOI: | 10.1007/978-1-4614-2410-9 |
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520 | |a <p>This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs. </p><ul><li>Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch;</li><li>Provides VHDL sources for the described processor;</li><li>Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines;</li><li>Includes programming by example in the micro-threaded assembly language.</li></ul><p> </p><p> </p> | ||
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Datensatz im Suchindex
DE-BY-FWS_katkey | 923451 |
---|---|
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adam_text | UTLEON3: EXPLORING FINE-GRAIN MULTI-THREADING IN FPGAS
/ DANEK, MARTIN
: 2013
TABLE OF CONTENTS / INHALTSVERZEICHNIS
INTRODUCTION
THE LEON3 PROCESSOR
MICROTHREADED EXTENSIONS
THE BASIC UTLEON3ARCHITECTURE.-UTLEON3 PROGRAMMING BY EXAMPLE
UTLEON3 IMPLEMENTATION DETAILS
EXECUTION EFFIECIENCY OFTHE MICROTHREAD PIPELINE.-HARDWARE FAMILIES
OF THREADS
I/O AND INTERRUPT HANDLING IN THE MICROTHREAD MODE
THE IU3 PIPELINE
EXCERPTS FROM THE LEON3 INSTRUCTION SET
RELEVANT LEON3 REGISTERS AND ADDRESS SPACE IDENTIFIERS.-SCHEDULER
EXAMPLE
USED RESOURCES
TUTORIAL
DIESES SCHRIFTSTUECK WURDE MASCHINELL ERZEUGT.
UTLEON3: EXPLORING FINE-GRAIN MULTI-THREADING IN FPGAS
/ DANEK, MARTIN
: 2013
ABSTRACT / INHALTSTEXT
THIS BOOK DESCRIBES A SPECIFICATION, MICROARCHITECTURE, VHDL
IMPLEMENTATION AND EVALUATION OF A SPARC V8 CPU WITH FINE-GRAIN
MULTI-THREADING, CALLED MICRO-THREADING. THE CPU, NAMED UTLEON3, IS AN
ALTERNATIVE PLATFORM FOR EXPLORING CPU MULTI-THREADING THAT IS
COMPATIBLE WITH THE INDUSTRY-STANDARD GRLIB PACKAGE. THE PROCESSOR
MICROARCHITECTURE WAS DESIGNED TO MAP IN AN EFFICIENT WAY THE DATA-FLOW
SCHEME ON A CLASSICAL VON NEUMANN PIPELINED PROCESSING USED IN COMMON
PROCESSORS, WHILE RETAINING FULL BINARY COMPATIBILITY WITH EXISTING
LEGACY PROGRAMS. DESCRIBES AND DOCUMENTS A WORKING SPARC V8, WITH
FINE-GRAIN MULTITHREADING AND FAST CONTEXT SWITCH; PROVIDES VHDL SOURCES
FOR THE DESCRIBED PROCESSOR; DESCRIBES A LATENCY-TOLERANT FRAMEWORK FOR
COUPLING HARDWARE ACCELERATORS TO MICROTHREADED PROCESSOR PIPELINES;
INCLUDES PROGRAMMING BY EXAMPLE IN THE MICRO-THREADED ASSEMBLY LANGUAGE.
DIESES SCHRIFTSTUECK WURDE MASCHINELL ERZEUGT.
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isbn | 9781461424109 |
language | English |
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physical | 1 Online-Ressource (XVIII, 219 p. 122 illus) |
psigel | ZDB-2-ENG |
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publisher | Springer |
record_format | marc |
spellingShingle | UTLEON3: Exploring fine-grain multi-threading in FPGAs Informatik Ingenieurwissenschaften Engineering Computer science Electronics Systems engineering |
title | UTLEON3: Exploring fine-grain multi-threading in FPGAs |
title_auth | UTLEON3: Exploring fine-grain multi-threading in FPGAs |
title_exact_search | UTLEON3: Exploring fine-grain multi-threading in FPGAs |
title_full | UTLEON3: Exploring fine-grain multi-threading in FPGAs Martin Daněk ... |
title_fullStr | UTLEON3: Exploring fine-grain multi-threading in FPGAs Martin Daněk ... |
title_full_unstemmed | UTLEON3: Exploring fine-grain multi-threading in FPGAs Martin Daněk ... |
title_short | UTLEON3: Exploring fine-grain multi-threading in FPGAs |
title_sort | utleon3 exploring fine grain multi threading in fpgas |
topic | Informatik Ingenieurwissenschaften Engineering Computer science Electronics Systems engineering |
topic_facet | Informatik Ingenieurwissenschaften Engineering Computer science Electronics Systems engineering |
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