Computer arithmetic: algorithms and hardware implementations
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Berlin [u.a.]
Springer
2012
|
| Schlagworte: | |
| Online-Zugang: | Inhaltstext Inhaltsverzeichnis |
| Beschreibung: | Literaturangaben |
| Beschreibung: | VI, 267 S. graph. Darst. 24 cm |
| ISBN: | 9783642183140 |
Internformat
MARC
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Datensatz im Suchindex
| _version_ | 1809404181462646784 |
|---|---|
| adam_text |
IMAGE 1
CONTENTS
1 THE REPRESENTATION OF NUMBERS IN COMPUTING SYSTEMS 1
1.1 INFORMATION CLASSIFICATION 1
1.2 THE REPRESENTATION O F FIXED POINT NUMBERS 2
1.2.1 THE REPRESENTATION OF FIXED POINT BINARY NUMBERS . . . . 2
1.2.2 THE REPRESENTATION O F FIXED POINT DECIMAL NUMBERS . . . 11 1.3
THE REPRESENTATION O F FLOATING POINT NUMBERS 13
2 FUNCTIONAL ANALYSIS AND SYNTHESIS O F BINARY AND DECIMAL ADDING AND
SUBTRACTING DEVICES 21
2.1 SERIAL ADDERS 21
2.2 PARALLEL ADDERS AND SUBTRACTERS 25
2.2.1 BINARY ADDERS BASED ON SERIAL CARRY PROPAGATION 25
2.2.2 DECIMAL ADDERS BASED ON SERIAL CARRY PROPAGATION . . . . 31
2.2.3 SUBTRACTERS BASED ON SERIAL CARRY/BORROW PROPAGATION . . . 35
2.2.4 CARRY-LOOKAHEAD ADDERS 38
2.2.5 CARRY-SKIP ADDER 45
2.2.6 CARRY-SELECT ADDER 49
2.2.7 CONDITIONAL-SUM ADDER 53
2.2.8 CARRY-SAVE ADDER 57
2.2.9 BINARY ADDERS WITH PARITY CONTROL 58
3 FUNCTIONAL ANALYSIS AND SYNTHESIS O F BINARY MULTIPLICATION DEVICES .
67 3.1 BINARY MULTIPLICATION METHODS 67
3.2 SEQUENTIAL SIGN-MAGNITUDE BINARY MULTIPLIER 70
3.3 SEQUENTIAL TWO'S COMPLEMENT BINARY MULTIPLIER BASED ON ROBERTSON'S
PROCEDURE 78
3.4 SEQUENTIAL TWO'S COMPLEMENT BINARY MULTIPLIER BASED ON BOOTH'S
PROCEDURES 83
3.5 BINARY MULTIPLICATION PROCESS SPEEDUP BY INCREASING RADIX VALUE 99
3.6 BINARY MULTIPLICATION SPEEDUP USING A SINGLE CARRY-SAVE ADDER 104
3.7 BINARY MULTIPLICATION SPEEDUP BASED ON RADIX 4 AND A CARRY-SAVE
ADDER 108
V
HTTP://D-NB.INFO/1009117742
IMAGE 2
VI CONTENTS
3.8 ABOUT "PARALLELIZING" OF THE SEQUENTIAL DEVICES FOR BINARY
MULTIPLICATION 110
3.9 COMBINATIONAL ARRAY STRUCTURES FOR BINARY MULTIPLICATION 113 3.10
COMBINATIONAL TREE STRUCTURES FOR BINARY MULTIPLICATION 129 3.11 OTHER
BINARY MULTIPLICATION METHODS 137
4 FUNCTIONAL ANALYSIS AND SYNTHESIS O F BINARY DIVISION DEVICES . . . .
143 4.1 BINARY DIVISION METHODS 143
4.1.1 RESTORING DIVISION 145
4.1.2 NON-RESTORING DIVISION 147
4.2 SEQUENTIAL BINARY DIVIDER FOR UNSIGNED INTEGERS 149
4.3 COMBINATIONAL ARRAY STRUCTURES FOR BINARY DIVISION 154
4.3.1 COMBINATIONAL ARRAY STRUCTURE BASED ON NON-RESTORING DIVISION 154
4.3.2 COMBINATIONAL ARRAY STRUCTURE BASED ON RESTORING DIVISION 160
4.4 SRT PROCEDURES FOR BINARY DIVISION 163
4.4.1 RADIX 2 SRT PROCEDURE 163
4.4.2 RADIX 4 SRT PROCEDURE 173
4.5 BINARY DIVISION BASED ON FAST CONVERGENCE 185
4.5.1 THE NEWTON-RAPHSON METHOD 186
4.5.2 GOLDSCHMIDT'S METHOD 189
5 FUNCTIONAL ANALYSIS AND SYNTHESIS O F FLOATING POINT ARITHMETIC
DEVICES 195
5.1 CHARACTERISTICS OF THE FLOATING POINT OPERATION 195
5.1.1 CLASSIFICATION OF DATA PROCESSING UNITS 195
5.1.2 PROBLEMS REGARDING FLOATING POINT OPERATIONS 198
5.2 FLOATING POINT ADDITION AND SUBTRACTION 208
5.2.1 FLOATING POINT ADDITION AND SUBTRACTION WITHOUT ROUNDING 208 5.2.2
FLOATING POINT ADDITION AND SUBTRACTION WITH ROUNDING . . 211 5.2.3
SPEEDING UP THE FLOATING POINT ADDITION/SUBTRACTION PROCESS 220
5.3 FLOATING POINT MULTIPLICATION AND DIVISION 240
APPENDIX A HARDWARE DESCRIPTION ELEMENTS 247
APPENDIX B CONTROL UNITS SYNTHESIS ELEMENTS 251
REFERENCES 265 |
| any_adam_object | 1 |
| author | Vlăduţiu, Mircea |
| author_GND | (DE-588)1029441936 |
| author_facet | Vlăduţiu, Mircea |
| author_role | aut |
| author_sort | Vlăduţiu, Mircea |
| author_variant | m v mv |
| building | Verbundindex |
| bvnumber | BV040683392 |
| classification_rvk | ST 150 |
| ctrlnum | (OCoLC)724772909 (DE-599)DNB1009117742 |
| dewey-full | 004.22 004.0151 |
| dewey-hundreds | 000 - Computer science, information, general works |
| dewey-ones | 004 - Computer science |
| dewey-raw | 004.22 004.0151 |
| dewey-search | 004.22 004.0151 |
| dewey-sort | 14.22 |
| dewey-tens | 000 - Computer science, information, general works |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| illustrated | Illustrated |
| indexdate | 2024-09-06T00:24:55Z |
| institution | BVB |
| isbn | 9783642183140 |
| language | English |
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| oclc_num | 724772909 |
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| physical | VI, 267 S. graph. Darst. 24 cm |
| publishDate | 2012 |
| publishDateSearch | 2012 |
| publishDateSort | 2012 |
| publisher | Springer |
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| spelling | Vlăduţiu, Mircea Verfasser (DE-588)1029441936 aut Computer arithmetic algorithms and hardware implementations Mircea Vlăduţiu Berlin [u.a.] Springer 2012 VI, 267 S. graph. Darst. 24 cm txt rdacontent n rdamedia nc rdacarrier Literaturangaben Computerarithmetik (DE-588)4135485-0 gnd rswk-swf Computerarithmetik (DE-588)4135485-0 s DE-604 Erscheint auch als Online-Ausgabe 978-3-642-18315-7 X:MVB text/html http://deposit.dnb.de/cgi-bin/dokserv?id=3639518&prov=M&dok_var=1&dok_ext=htm Inhaltstext DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=025509739&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Vlăduţiu, Mircea Computer arithmetic algorithms and hardware implementations Computerarithmetik (DE-588)4135485-0 gnd |
| subject_GND | (DE-588)4135485-0 |
| title | Computer arithmetic algorithms and hardware implementations |
| title_auth | Computer arithmetic algorithms and hardware implementations |
| title_exact_search | Computer arithmetic algorithms and hardware implementations |
| title_full | Computer arithmetic algorithms and hardware implementations Mircea Vlăduţiu |
| title_fullStr | Computer arithmetic algorithms and hardware implementations Mircea Vlăduţiu |
| title_full_unstemmed | Computer arithmetic algorithms and hardware implementations Mircea Vlăduţiu |
| title_short | Computer arithmetic |
| title_sort | computer arithmetic algorithms and hardware implementations |
| title_sub | algorithms and hardware implementations |
| topic | Computerarithmetik (DE-588)4135485-0 gnd |
| topic_facet | Computerarithmetik |
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