Interlayer thermal management of high-performance microprocessor chip stacks:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
Göttingen
Cuvillier
2012
|
| Ausgabe: | 1. Aufl. |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XIV, 156 S. Ill., graph. Darst. |
| ISBN: | 9783954040346 |
Internformat
MARC
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| 264 | 1 | |a Göttingen |b Cuvillier |c 2012 | |
| 300 | |a XIV, 156 S. |b Ill., graph. Darst. | ||
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Datensatz im Suchindex
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|---|---|
| adam_text | IMAGE 1
CONTENTS
SUMMARY V
Z U S A M M E N F A S S U N G VII
ACKNOWLEDGEMENTS X
1 VERTICAL INTEGRATION O F H I G H - P E R F O R M A N C E P R O C E S S
O R - M E M O R Y S T A C K S : M O T I V A T I O N & C O N C E P T I O
N 1
1.1 DRIVING FORCES AND ENABLING TECHNOLOGIES 1
1.1.1 PERFORMANCE BENEFITS OF VERTICAL AREA ARRAY ELECTRICAL
INTERCONNECTS 1
1.1.2 ENABLING TECHNOLOGIES: VERTICAL INTERCONNECTS - SUBSTRATE THINNING
- ALIGNMENT & BONDING . . 3 1.1.3 VERTICAL INTEGRATION PRODUCT ROADMAP 6
1.2 THERMAL MANAGEMENT CONCEPTS AND LIMITATIONS 7
1.2.1 POWER DISSIPATION CHARACTERISTICS OF IC-DIES 7
1.2.2 THERMAL RESPONSE OF IC-DIES 8
1.2.3 ESTABLISHED HEAT REMOVAL CONCEPTS 9
1.2.4 BACK-SIDE HEAT REMOVAL LIMITS OF VERTICAL INTEGRATED CHIP STACKS
10
1.2.5 INTERLAYER THERMAL MANAGEMENT 12
1.3 CONVECTIVE INTERLAYER HEAT REMOVAL - A SCALABLE CONCEPT 12
1.3.1 IMPLEMENTATION CONCEPTS: VIA SEALING A N D PRESSURE BALANCED
PACKAGE 13
1.3.2 INTERNAL FLOW HEAT TRANSFER CHARACTERISTICS: A SENSITIVITY
ANALYSIS AT CONSTANT GEOMETRICAL RATIO 14 1.3.3 MODULAR HEAT A N D MASS
TRANSFER BUILDING BLOCKS 17
1.3.4 ELECTRO-THERMAL CO-DESIGN / OPTIMIZATION FRAMEWORK 22
1.4 SCOPE AND ORGANIZATION OF THE THESIS 22
2 MULTI-SCALE MODELING W I T H P O R O U S - M E D I A A P P R O A C H
FOR H E A T A N D M A S S T R A N S F E R DESIGN 2 5
2.1 DETAILED CONJUGATE HEAT A N D MASS TRANSFER 25
2.1.1 FLUID FLOW BASICS O F N E W T O N I A N VISCOUS MEDIA 2 5
2.1.2 HEAT CONDUCTION A N D ENERGY CONSERVATION 26
2.1.3 LIMITATIONS OF DETAILED CHIP STACK MODELING 27
2.2 MULTI-SCALE MODELING: HEAT A N D MASS TRANSFER IN POROUS MEDIA 27
2.2.1 VOLUME AVERAGING OF POROUS MEDIA 28
2.2.2 FROM D A R C Y FLOW TO THE EXTENDED NAVIER-STOKES EQUATION 29
2.2.3 HEAT TRANSFER THROUGH A POROUS MEDIUM 30
2.2.4 POROUS - SOLID DOMAIN INTERACTION 30
2.2.5 3D SOLID TO 2D POROUS MEDIA FIELD-COUPLING 32
2.3 PARAMETER EXTRACTION FROM EFFICIENT SUB-DOMAIN MODELING WITH
PERIODIC BOUNDARY CONDITIONS . . . 35 2.3.1 SUB-DOMAIN MODEL USING
PERIODIC BOUNDARY CONDITIONS 37
2.3.2 PARAMETER SET OF INDIVIDUAL HEAT TRANSFER GEOMETRIES IN SYMMETRY
DIRECTION 41
2.3.3 PARAMETER SET FOR PIN-FIN ARRAYS AT ARBITRARY ANGLE-OF-ATTACK 48
3 EUTECTIC BONDING, T E S T CAVITIES, A N D E X P E R I M E N T A L A P
P A R A T U S FOR C H A R A C T E R I Z A T I O N 6 1
3.1 EUTECTIC AUSN 80/20 THIN FILM BONDING: LOW THERMAL RESISTANCE, LEAK
L I G H T INTERFACE 61
3.1.1 SOLDER TECHNOLOGIES FOR STRUCTURAL A N D THERMAL INTERFACES 61
3.1.2 FORMIC ACID ASSISTED THERMO-COMPRESSION BONDING 64
3.1.3 THIN FILM SOLDER BOND-LINE FORMATION 66
3.1.4 THERMODYNAMIC STABILITY OF UNDER BUMP METALLIZATIONS 69
3.1.5 SOLDER PROCESS QUALIFICATION 72
3.2 WATER COOLANT COMPATIBLE MULTI-METAL LAYER SYSTEM 75
3.3 SINGLE-CAVITY, DOUBLE-SIDE HEATED TEST VEHICLE 78
3.3.1 TEST VEHICLE WITH UNIFORM POWER DISSIPATION A N D HEAT TRANSFER
GEOMETRY 78
3.3.2 TEST VEHICLE WITH NON-UNIFORM POWER DISSIPATION A N D HEAT
TRANSFER GEOMETRY 79
HTTP://D-NB.INFO/1021747009
IMAGE 2
CONTENTS
3.4 MULTI-CAVITY TEST VEHICLE: PYRAMID-CHIP-STACK 81
3.5 SINGLE-PHASE TEST LOOP WITH SPATIALLY RESOLVED INFRARED IMAGING 83
4 E X P E R I M E N T A L RESULTS A N D VALIDATION O F MODELING
FRAMEWORK 8 5
4.1 UNIFORM SINGLE CAVITY EXPERIMENT: UNIT-CELL SHAPE EFFICIENCY 85
4.1.1 EXPERIMENTAL SEQUENCE AND EXTRAPOLATION OF DATASETS 86
4.1.2 HYDRODYNAMIC CHARACTERISTICS OF UNIT-CELLS 88
4.1.3 HEAT TRANSFER CHARACTERISTICS OF UNIT-CELLS 92
4.1.4 FLOW TRANSITION AUGMENTED HEAT TRANSFER 95
4.1.5 PERFORMANCE AT PRESSURE OR PUMPING POWER CONSTRAINTS 95
4.2 NON-UNIFORM SINGLE CAVITY EXPERIMENT TO VALIDATE MULTI-SCALE CONCEPT
99
4.2.1 HYDRODYNAMIC AND SPATIALLY RESOLVED THERMAL MEASUREMENTS 100
4.2.2 FIELD-COUPLED POROUS MEDIA MODEL REPRESENTING NON-UNIFORM CAVITIES
102
4.2.3 VALIDATION OF MULTI-SCALE CONCEPT WITH DETAILED CONJUGATE HEAT A N
D MASS TRANSFER MODEL OF THE PARALLEL PLATE TEST VEHICLE 102
4.2.4 VALIDATION OF MULTI-SCALE MODELING CONCEPT WITH EXPERIMENTAL
RESULTS 104
4.3 THERMALLY COMMUNICATING FLUID CAVITIES: INTERLAYER COOLED PYRAMID
CHIP STACK I L L
4.3.1 FIELD-COUPLED POROUS MEDIA MODEL REPRESENTING PYRAMID-CHIP-STACK I
L L
4.3.2 VALIDATION OF MULTI-SCALE MODEING CONCEPT WITH EXPERIMENTAL
RESULTS 112
4.3.3 TIER-TO-TIE THERMAL CROSSTALK 113
4.3.4 BENCHMARKING OF FLUID DELIVERY ARCHITECTURE: TWO-PORT VS.
FOUR-PORT 116
5 INTERLAYER COOLING DESIGN-RULES, CONCLUSIONS A N D O U T L O O K 1 1 7
5.1 INTERLAYER COOLED CHIP STACKS: PERFORMANCE A N D CHARACTERISTICS 117
5.1.1 BENCHMARK: UNIFORM, TWO-PORT INTERLAYER COOLING VS. BACK-SIDE HEAT
REMOVAL 117
5.1.2 FLUID MANIFOLD DESIGN: PRESSURE PENALTY A N D MASS FLOW
MALDISTRIBUTION 118
5.1.3 CRITICAL HOT-SPOT DIMENSION: HOT-SPOT TEMPERATURE MITIGATION BY
HEAT SPREADING IN THIN D I E S L L 9 5.1.4 THERMAL TRANSIENTS: TIME
CONSTANT A N D RETARDATION 120
5.2 ADVANCED INTERLAYER COOLING: DESIGN-RULES A N D RECOMMENDATIONS 122
5.2.1 UNIT-CELL SHAPE MENU A N D INTERLAYER COOLING PERFORMANCE SCALING
AT UNIFORM HEAT FLUX . . . 122 5.2.2 POWER MAP AWARE HEAT REMOVAL: HEAT
TRANSFER STRUCTURE MODULATION - FLUID FOCUSING - FLUID DELIVERY
ARCHITECTURES - TIER-TO-TIER CROSSTALK 123
5.2.3 ELECTRO-THERMAL CO-DESIGN: INTERLAYER COOLING AWARE FLOORPLANRTING
124
5.2.4 INTERLAYER COOLING PERFORMANCE EVOLUTION 125
5.3 FUTURE RESEARCH AGENDA 126
5.3.1 INTERLAYER COOLING IMPLEMENTATION: RELIABLE PACKAGING TECHNOLOGY
126
5.3.2 ADVANCED HEAT AND MASS TRANSFER 127
5.3.3 EXTENDED MODELING FRAME WORK 127
A P O W E R M A P C O N T R A S T SPECIFIC P I N S H A P E O P T I M I Z
A T I O N 1 2 9
A.L ADVANCED PIN SHAPES 129
A.2 PIN SHAPE SELECTION WITH RESPECT TO POWER MAP CONTRAST 131
B I M P L E M E N T A T I O N O F P O R O U S - M E D I A A N D
FIELD-COUPLING: A N S Y S CFX 1 3 5
B.L DEFINITION FILE MANIPULATION: CFX COMMAND LINE 135
B.2 MASS TRANSPORT IN THE QUASI TWO-DIMENSIONAL POROUS DOMAIN 135
B.3 HEAT TRANSFER BY POROUS DOMAIN FIELD-COUPLING 137
C ABBREVIATIONS 1 3 9
D LIST O F S Y M B O L S 1 4 1
BIBLIOGRAPHY 1 4 5
LIST O F PUBLICATIONS 1 5 3
|
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 1. Aufl. |
| format | Thesis Book |
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| spelling | Brunschwiler, Thomas Verfasser aut Interlayer thermal management of high-performance microprocessor chip stacks von Thomas Brunschwiler 1. Aufl. Göttingen Cuvillier 2012 XIV, 156 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Zugl.: Berlin, Techn. Univ., Diss., 2012 Multichiptechnik (DE-588)4267925-4 gnd rswk-swf Mikroprozessor (DE-588)4039232-6 gnd rswk-swf Stapel (DE-588)4417888-8 gnd rswk-swf Wasserkühlung (DE-588)4189219-7 gnd rswk-swf Konvektionskühlung (DE-588)4339934-4 gnd rswk-swf Wärmeübertragung (DE-588)4064211-2 gnd rswk-swf Leistungsbewertung (DE-588)4167271-9 gnd rswk-swf Dreidimensionale Integration (DE-588)4218841-6 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Dreidimensionale Integration (DE-588)4218841-6 s Multichiptechnik (DE-588)4267925-4 s Stapel (DE-588)4417888-8 s Wärmeübertragung (DE-588)4064211-2 s Konvektionskühlung (DE-588)4339934-4 s Wasserkühlung (DE-588)4189219-7 s Mikroprozessor (DE-588)4039232-6 s Leistungsbewertung (DE-588)4167271-9 s DE-604 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=025311377&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Brunschwiler, Thomas Interlayer thermal management of high-performance microprocessor chip stacks Multichiptechnik (DE-588)4267925-4 gnd Mikroprozessor (DE-588)4039232-6 gnd Stapel (DE-588)4417888-8 gnd Wasserkühlung (DE-588)4189219-7 gnd Konvektionskühlung (DE-588)4339934-4 gnd Wärmeübertragung (DE-588)4064211-2 gnd Leistungsbewertung (DE-588)4167271-9 gnd Dreidimensionale Integration (DE-588)4218841-6 gnd |
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| title | Interlayer thermal management of high-performance microprocessor chip stacks |
| title_auth | Interlayer thermal management of high-performance microprocessor chip stacks |
| title_exact_search | Interlayer thermal management of high-performance microprocessor chip stacks |
| title_full | Interlayer thermal management of high-performance microprocessor chip stacks von Thomas Brunschwiler |
| title_fullStr | Interlayer thermal management of high-performance microprocessor chip stacks von Thomas Brunschwiler |
| title_full_unstemmed | Interlayer thermal management of high-performance microprocessor chip stacks von Thomas Brunschwiler |
| title_short | Interlayer thermal management of high-performance microprocessor chip stacks |
| title_sort | interlayer thermal management of high performance microprocessor chip stacks |
| topic | Multichiptechnik (DE-588)4267925-4 gnd Mikroprozessor (DE-588)4039232-6 gnd Stapel (DE-588)4417888-8 gnd Wasserkühlung (DE-588)4189219-7 gnd Konvektionskühlung (DE-588)4339934-4 gnd Wärmeübertragung (DE-588)4064211-2 gnd Leistungsbewertung (DE-588)4167271-9 gnd Dreidimensionale Integration (DE-588)4218841-6 gnd |
| topic_facet | Multichiptechnik Mikroprozessor Stapel Wasserkühlung Konvektionskühlung Wärmeübertragung Leistungsbewertung Dreidimensionale Integration Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=025311377&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT brunschwilerthomas interlayerthermalmanagementofhighperformancemicroprocessorchipstacks |