Fundamentals of digital logic with VHDL design:
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Buch |
Sprache: | English |
Veröffentlicht: |
Boston, Mass [u.a.]
McGraw-Hill
2009
|
Ausgabe: | 3. ed. [International student ed.] |
Schriftenreihe: | McGraw-Hill series in electrical and computer engineering
|
Schlagworte: | |
Online-Zugang: | Inhaltsverzeichnis |
Beschreibung: | Auf der CD-ROM-Beil.: Altera Quartus II Version 7.1. |
Beschreibung: | XX, 939 S. Ill., graph. Darst. 1 CD-ROM (12 cm) |
Format: | . - der CD-ROM-Beil.: Pentium III or later (faster processor is recommended) |
ISBN: | 9780071284288 0071268804 9780071268806 9780071287654 9780073529530 9780077221430 9780077210724 |
Internformat
MARC
LEADER | 00000nam a2200000 c 4500 | ||
---|---|---|---|
001 | BV040327454 | ||
003 | DE-604 | ||
005 | 20120914 | ||
007 | t | ||
008 | 120723s2009 ad|| |||| 00||| eng d | ||
020 | |a 9780071284288 |9 978-0-07-128428-8 | ||
020 | |a 0071268804 |9 0-07-126880-4 | ||
020 | |a 9780071268806 |9 978-0-07-126880-6 | ||
020 | |a 9780071287654 |9 978-0-07-128765-4 | ||
020 | |a 9780073529530 |9 978-0-07-352953-0 | ||
020 | |a 9780077221430 |9 978-0-07-722143-0 | ||
020 | |a 9780077210724 |c (CDROM) |9 978-0-07-721072-4 | ||
035 | |a (OCoLC)553865425 | ||
035 | |a (DE-599)GBV612941507 | ||
040 | |a DE-604 |b ger | ||
041 | 0 | |a eng | |
049 | |a DE-91G | ||
082 | 0 | |a 621.39/5 | |
084 | |a DAT 195f |2 stub | ||
084 | |a ELT 453f |2 stub | ||
100 | 1 | |a Brown, Stephen |e Verfasser |4 aut | |
245 | 1 | 0 | |a Fundamentals of digital logic with VHDL design |c Stephen Brown and Zvonko Vranesic |
246 | 1 | 3 | |a Altera Quartus II Version 7.1 |
250 | |a 3. ed. [International student ed.] | ||
264 | 1 | |a Boston, Mass [u.a.] |b McGraw-Hill |c 2009 | |
300 | |a XX, 939 S. |b Ill., graph. Darst. |e 1 CD-ROM (12 cm) | ||
336 | |b txt |2 rdacontent | ||
337 | |b n |2 rdamedia | ||
338 | |b nc |2 rdacarrier | ||
490 | 0 | |a McGraw-Hill series in electrical and computer engineering | |
500 | |a Auf der CD-ROM-Beil.: Altera Quartus II Version 7.1. | ||
538 | |a . - der CD-ROM-Beil.: Pentium III or later (faster processor is recommended) | ||
650 | 0 | 7 | |a Logischer Entwurf |0 (DE-588)4168051-0 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Digitaltechnik |0 (DE-588)4012303-0 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Logische Schaltung |0 (DE-588)4131023-8 |2 gnd |9 rswk-swf |
689 | 0 | 0 | |a Digitaltechnik |0 (DE-588)4012303-0 |D s |
689 | 0 | 1 | |a Logischer Entwurf |0 (DE-588)4168051-0 |D s |
689 | 0 | |5 DE-604 | |
689 | 1 | 0 | |a VHDL |0 (DE-588)4254792-1 |D s |
689 | 1 | |5 DE-604 | |
689 | 2 | 0 | |a Logische Schaltung |0 (DE-588)4131023-8 |D s |
689 | 2 | |8 1\p |5 DE-604 | |
700 | 1 | |a Vranesic, Zvonko |e Verfasser |4 aut | |
856 | 4 | |m DE-601 |q pdf/application |u http://www.gbv.de/dms/bowker/toc/9780077221430.pdf |3 Inhaltsverzeichnis | |
999 | |a oai:aleph.bib-bvb.de:BVB01-025181950 | ||
883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk |
Datensatz im Suchindex
_version_ | 1804149357841219584 |
---|---|
any_adam_object | |
author | Brown, Stephen Vranesic, Zvonko |
author_facet | Brown, Stephen Vranesic, Zvonko |
author_role | aut aut |
author_sort | Brown, Stephen |
author_variant | s b sb z v zv |
building | Verbundindex |
bvnumber | BV040327454 |
classification_tum | DAT 195f ELT 453f |
ctrlnum | (OCoLC)553865425 (DE-599)GBV612941507 |
dewey-full | 621.39/5 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
dewey-raw | 621.39/5 |
dewey-search | 621.39/5 |
dewey-sort | 3621.39 15 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Informatik Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
edition | 3. ed. [International student ed.] |
format | Book |
fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02268nam a2200589 c 4500</leader><controlfield tag="001">BV040327454</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20120914 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">120723s2009 ad|| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780071284288</subfield><subfield code="9">978-0-07-128428-8</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0071268804</subfield><subfield code="9">0-07-126880-4</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780071268806</subfield><subfield code="9">978-0-07-126880-6</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780071287654</subfield><subfield code="9">978-0-07-128765-4</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780073529530</subfield><subfield code="9">978-0-07-352953-0</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780077221430</subfield><subfield code="9">978-0-07-722143-0</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780077210724</subfield><subfield code="c">(CDROM)</subfield><subfield code="9">978-0-07-721072-4</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)553865425</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBV612941507</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 195f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 453f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Brown, Stephen</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Fundamentals of digital logic with VHDL design</subfield><subfield code="c">Stephen Brown and Zvonko Vranesic</subfield></datafield><datafield tag="246" ind1="1" ind2="3"><subfield code="a">Altera Quartus II Version 7.1</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">3. ed. [International student ed.]</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, Mass [u.a.]</subfield><subfield code="b">McGraw-Hill</subfield><subfield code="c">2009</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XX, 939 S.</subfield><subfield code="b">Ill., graph. Darst.</subfield><subfield code="e">1 CD-ROM (12 cm)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">McGraw-Hill series in electrical and computer engineering</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Auf der CD-ROM-Beil.: Altera Quartus II Version 7.1.</subfield></datafield><datafield tag="538" ind1=" " ind2=" "><subfield code="a">. - der CD-ROM-Beil.: Pentium III or later (faster processor is recommended)</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitaltechnik</subfield><subfield code="0">(DE-588)4012303-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logische Schaltung</subfield><subfield code="0">(DE-588)4131023-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Digitaltechnik</subfield><subfield code="0">(DE-588)4012303-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Logische Schaltung</subfield><subfield code="0">(DE-588)4131023-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Vranesic, Zvonko</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="m">DE-601</subfield><subfield code="q">pdf/application</subfield><subfield code="u">http://www.gbv.de/dms/bowker/toc/9780077221430.pdf</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-025181950</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield></record></collection> |
id | DE-604.BV040327454 |
illustrated | Illustrated |
indexdate | 2024-07-10T00:21:45Z |
institution | BVB |
isbn | 9780071284288 0071268804 9780071268806 9780071287654 9780073529530 9780077221430 9780077210724 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-025181950 |
oclc_num | 553865425 |
open_access_boolean | |
owner | DE-91G DE-BY-TUM |
owner_facet | DE-91G DE-BY-TUM |
physical | XX, 939 S. Ill., graph. Darst. 1 CD-ROM (12 cm) |
publishDate | 2009 |
publishDateSearch | 2009 |
publishDateSort | 2009 |
publisher | McGraw-Hill |
record_format | marc |
series2 | McGraw-Hill series in electrical and computer engineering |
spelling | Brown, Stephen Verfasser aut Fundamentals of digital logic with VHDL design Stephen Brown and Zvonko Vranesic Altera Quartus II Version 7.1 3. ed. [International student ed.] Boston, Mass [u.a.] McGraw-Hill 2009 XX, 939 S. Ill., graph. Darst. 1 CD-ROM (12 cm) txt rdacontent n rdamedia nc rdacarrier McGraw-Hill series in electrical and computer engineering Auf der CD-ROM-Beil.: Altera Quartus II Version 7.1. . - der CD-ROM-Beil.: Pentium III or later (faster processor is recommended) Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Digitaltechnik (DE-588)4012303-0 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Digitaltechnik (DE-588)4012303-0 s Logischer Entwurf (DE-588)4168051-0 s DE-604 VHDL (DE-588)4254792-1 s Logische Schaltung (DE-588)4131023-8 s 1\p DE-604 Vranesic, Zvonko Verfasser aut DE-601 pdf/application http://www.gbv.de/dms/bowker/toc/9780077221430.pdf Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Brown, Stephen Vranesic, Zvonko Fundamentals of digital logic with VHDL design Logischer Entwurf (DE-588)4168051-0 gnd Digitaltechnik (DE-588)4012303-0 gnd VHDL (DE-588)4254792-1 gnd Logische Schaltung (DE-588)4131023-8 gnd |
subject_GND | (DE-588)4168051-0 (DE-588)4012303-0 (DE-588)4254792-1 (DE-588)4131023-8 |
title | Fundamentals of digital logic with VHDL design |
title_alt | Altera Quartus II Version 7.1 |
title_auth | Fundamentals of digital logic with VHDL design |
title_exact_search | Fundamentals of digital logic with VHDL design |
title_full | Fundamentals of digital logic with VHDL design Stephen Brown and Zvonko Vranesic |
title_fullStr | Fundamentals of digital logic with VHDL design Stephen Brown and Zvonko Vranesic |
title_full_unstemmed | Fundamentals of digital logic with VHDL design Stephen Brown and Zvonko Vranesic |
title_short | Fundamentals of digital logic with VHDL design |
title_sort | fundamentals of digital logic with vhdl design |
topic | Logischer Entwurf (DE-588)4168051-0 gnd Digitaltechnik (DE-588)4012303-0 gnd VHDL (DE-588)4254792-1 gnd Logische Schaltung (DE-588)4131023-8 gnd |
topic_facet | Logischer Entwurf Digitaltechnik VHDL Logische Schaltung |
url | http://www.gbv.de/dms/bowker/toc/9780077221430.pdf |
work_keys_str_mv | AT brownstephen fundamentalsofdigitallogicwithvhdldesign AT vranesiczvonko fundamentalsofdigitallogicwithvhdldesign AT brownstephen alteraquartusiiversion71 AT vranesiczvonko alteraquartusiiversion71 |