Digital design: principles and practices
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Upper Saddle River, N.J.
Pearson/Prentice Hall
2007
|
| Ausgabe: | 4. ed., internat. ed. |
| Schriftenreihe: | Pearson international edition
|
| Schlagworte: | |
| Beschreibung: | Includes index. - Set ISBN and publication date of package from web pages. - Accompanied by Xilinx student ed. (2 CD-ROMS) and Active-HDL version 6.3 student ed. CD-ROM. |
| Beschreibung: | XXIV, 802 S. graph. Darst. 24 cm. + 3 CD-ROMs (12 cm) |
| ISBN: | 9780132016117 0132016117 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV040268274 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t | ||
| 008 | 120621s2007 d||| |||| 00||| eng d | ||
| 020 | |a 9780132016117 |9 978-0-13-201611-7 | ||
| 020 | |a 0132016117 |9 0-13-201611-7 | ||
| 035 | |a (OCoLC)699689704 | ||
| 035 | |a (DE-599)BVBBV040268274 | ||
| 040 | |a DE-604 |b ger |e rakwb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-898 | ||
| 084 | |a ZN 5600 |0 (DE-625)157468: |2 rvk | ||
| 100 | 1 | |a Wakerly, John F. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Digital design |b principles and practices |c John F. Wakerly ; Verilog adaptation by Jong Ching Chuen, Chang Chip Hong |
| 250 | |a 4. ed., internat. ed. | ||
| 264 | 1 | |a Upper Saddle River, N.J. |b Pearson/Prentice Hall |c 2007 | |
| 300 | |a XXIV, 802 S. |b graph. Darst. |c 24 cm. + |e 3 CD-ROMs (12 cm) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Pearson international edition | |
| 500 | |a Includes index. - Set ISBN and publication date of package from web pages. - Accompanied by Xilinx student ed. (2 CD-ROMS) and Active-HDL version 6.3 student ed. CD-ROM. | ||
| 650 | 4 | |a Digital integrated circuits / Design and construction | |
| 650 | 0 | 7 | |a Digitalschaltung |0 (DE-588)4012295-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Logischer Entwurf |0 (DE-588)4168051-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Computer |0 (DE-588)4070083-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Logische Schaltung |0 (DE-588)4131023-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Digitaltechnik |0 (DE-588)4012303-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Digitale integrierte Schaltung |0 (DE-588)4113313-4 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Digitaltechnik |0 (DE-588)4012303-0 |D s |
| 689 | 0 | 1 | |a Logische Schaltung |0 (DE-588)4131023-8 |D s |
| 689 | 0 | 2 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 689 | 1 | 0 | |a Digitalschaltung |0 (DE-588)4012295-5 |D s |
| 689 | 1 | 1 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
| 689 | 1 | |8 2\p |5 DE-604 | |
| 689 | 2 | 0 | |a Digitalschaltung |0 (DE-588)4012295-5 |D s |
| 689 | 2 | 1 | |a Logischer Entwurf |0 (DE-588)4168051-0 |D s |
| 689 | 2 | |8 3\p |5 DE-604 | |
| 689 | 3 | 0 | |a Computer |0 (DE-588)4070083-5 |D s |
| 689 | 3 | 1 | |a Logische Schaltung |0 (DE-588)4131023-8 |D s |
| 689 | 3 | |8 4\p |5 DE-604 | |
| 689 | 4 | 0 | |a Digitale integrierte Schaltung |0 (DE-588)4113313-4 |D s |
| 689 | 4 | |8 5\p |5 DE-604 | |
| 700 | 1 | |a Chuen, Jong Ching |e Sonstige |4 oth | |
| 700 | 1 | |a Hong, Chang Chip |e Sonstige |4 oth | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-025123900 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 3\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 4\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 5\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
Datensatz im Suchindex
| _version_ | 1804149272272175104 |
|---|---|
| any_adam_object | |
| author | Wakerly, John F. |
| author_facet | Wakerly, John F. |
| author_role | aut |
| author_sort | Wakerly, John F. |
| author_variant | j f w jf jfw |
| building | Verbundindex |
| bvnumber | BV040268274 |
| classification_rvk | ZN 5600 |
| ctrlnum | (OCoLC)699689704 (DE-599)BVBBV040268274 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 4. ed., internat. ed. |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02965nam a2200673 c 4500</leader><controlfield tag="001">BV040268274</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">120621s2007 d||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780132016117</subfield><subfield code="9">978-0-13-201611-7</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0132016117</subfield><subfield code="9">0-13-201611-7</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)699689704</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV040268274</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-898</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 5600</subfield><subfield code="0">(DE-625)157468:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Wakerly, John F.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Digital design</subfield><subfield code="b">principles and practices</subfield><subfield code="c">John F. Wakerly ; Verilog adaptation by Jong Ching Chuen, Chang Chip Hong</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">4. ed., internat. ed.</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Upper Saddle River, N.J.</subfield><subfield code="b">Pearson/Prentice Hall</subfield><subfield code="c">2007</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXIV, 802 S.</subfield><subfield code="b">graph. Darst.</subfield><subfield code="c">24 cm. +</subfield><subfield code="e">3 CD-ROMs (12 cm)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">Pearson international edition</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes index. - Set ISBN and publication date of package from web pages. - Accompanied by Xilinx student ed. (2 CD-ROMS) and Active-HDL version 6.3 student ed. CD-ROM.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Digital integrated circuits / Design and construction</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitalschaltung</subfield><subfield code="0">(DE-588)4012295-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Computer</subfield><subfield code="0">(DE-588)4070083-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logische Schaltung</subfield><subfield code="0">(DE-588)4131023-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitaltechnik</subfield><subfield code="0">(DE-588)4012303-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitale integrierte Schaltung</subfield><subfield code="0">(DE-588)4113313-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Digitaltechnik</subfield><subfield code="0">(DE-588)4012303-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Logische Schaltung</subfield><subfield code="0">(DE-588)4131023-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Digitalschaltung</subfield><subfield code="0">(DE-588)4012295-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Digitalschaltung</subfield><subfield code="0">(DE-588)4012295-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2="1"><subfield code="a">Logischer Entwurf</subfield><subfield code="0">(DE-588)4168051-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="8">3\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="3" ind2="0"><subfield code="a">Computer</subfield><subfield code="0">(DE-588)4070083-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2="1"><subfield code="a">Logische Schaltung</subfield><subfield code="0">(DE-588)4131023-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="3" ind2=" "><subfield code="8">4\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="4" ind2="0"><subfield code="a">Digitale integrierte Schaltung</subfield><subfield code="0">(DE-588)4113313-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="4" ind2=" "><subfield code="8">5\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Chuen, Jong Ching</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Hong, Chang Chip</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-025123900</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">3\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">4\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">5\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield></record></collection> |
| id | DE-604.BV040268274 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T00:20:23Z |
| institution | BVB |
| isbn | 9780132016117 0132016117 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-025123900 |
| oclc_num | 699689704 |
| open_access_boolean | |
| owner | DE-898 DE-BY-UBR |
| owner_facet | DE-898 DE-BY-UBR |
| physical | XXIV, 802 S. graph. Darst. 24 cm. + 3 CD-ROMs (12 cm) |
| publishDate | 2007 |
| publishDateSearch | 2007 |
| publishDateSort | 2007 |
| publisher | Pearson/Prentice Hall |
| record_format | marc |
| series2 | Pearson international edition |
| spelling | Wakerly, John F. Verfasser aut Digital design principles and practices John F. Wakerly ; Verilog adaptation by Jong Ching Chuen, Chang Chip Hong 4. ed., internat. ed. Upper Saddle River, N.J. Pearson/Prentice Hall 2007 XXIV, 802 S. graph. Darst. 24 cm. + 3 CD-ROMs (12 cm) txt rdacontent n rdamedia nc rdacarrier Pearson international edition Includes index. - Set ISBN and publication date of package from web pages. - Accompanied by Xilinx student ed. (2 CD-ROMS) and Active-HDL version 6.3 student ed. CD-ROM. Digital integrated circuits / Design and construction Digitalschaltung (DE-588)4012295-5 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Computer (DE-588)4070083-5 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Digitaltechnik (DE-588)4012303-0 gnd rswk-swf Digitale integrierte Schaltung (DE-588)4113313-4 gnd rswk-swf Digitaltechnik (DE-588)4012303-0 s Logische Schaltung (DE-588)4131023-8 s Schaltungsentwurf (DE-588)4179389-4 s 1\p DE-604 Digitalschaltung (DE-588)4012295-5 s 2\p DE-604 Logischer Entwurf (DE-588)4168051-0 s 3\p DE-604 Computer (DE-588)4070083-5 s 4\p DE-604 Digitale integrierte Schaltung (DE-588)4113313-4 s 5\p DE-604 Chuen, Jong Ching Sonstige oth Hong, Chang Chip Sonstige oth 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 5\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Wakerly, John F. Digital design principles and practices Digital integrated circuits / Design and construction Digitalschaltung (DE-588)4012295-5 gnd Logischer Entwurf (DE-588)4168051-0 gnd Computer (DE-588)4070083-5 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Logische Schaltung (DE-588)4131023-8 gnd Digitaltechnik (DE-588)4012303-0 gnd Digitale integrierte Schaltung (DE-588)4113313-4 gnd |
| subject_GND | (DE-588)4012295-5 (DE-588)4168051-0 (DE-588)4070083-5 (DE-588)4179389-4 (DE-588)4131023-8 (DE-588)4012303-0 (DE-588)4113313-4 |
| title | Digital design principles and practices |
| title_auth | Digital design principles and practices |
| title_exact_search | Digital design principles and practices |
| title_full | Digital design principles and practices John F. Wakerly ; Verilog adaptation by Jong Ching Chuen, Chang Chip Hong |
| title_fullStr | Digital design principles and practices John F. Wakerly ; Verilog adaptation by Jong Ching Chuen, Chang Chip Hong |
| title_full_unstemmed | Digital design principles and practices John F. Wakerly ; Verilog adaptation by Jong Ching Chuen, Chang Chip Hong |
| title_short | Digital design |
| title_sort | digital design principles and practices |
| title_sub | principles and practices |
| topic | Digital integrated circuits / Design and construction Digitalschaltung (DE-588)4012295-5 gnd Logischer Entwurf (DE-588)4168051-0 gnd Computer (DE-588)4070083-5 gnd Schaltungsentwurf (DE-588)4179389-4 gnd Logische Schaltung (DE-588)4131023-8 gnd Digitaltechnik (DE-588)4012303-0 gnd Digitale integrierte Schaltung (DE-588)4113313-4 gnd |
| topic_facet | Digital integrated circuits / Design and construction Digitalschaltung Logischer Entwurf Computer Schaltungsentwurf Logische Schaltung Digitaltechnik Digitale integrierte Schaltung |
| work_keys_str_mv | AT wakerlyjohnf digitaldesignprinciplesandpractices AT chuenjongching digitaldesignprinciplesandpractices AT hongchangchip digitaldesignprinciplesandpractices |