Logic circuit design: selected methods
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Berlin [u.a.]
Springer
2012
|
| Schlagworte: | |
| Online-Zugang: | Inhaltstext Inhaltsverzeichnis |
| Beschreibung: | Literaturangaben |
| Beschreibung: | XIV, 258 S. graph. Darst. |
| ISBN: | 3642276563 9783642276569 |
Internformat
MARC
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| 100 | 1 | |a Vingron, Shimon Peter |d 1936- |e Verfasser |0 (DE-588)125011407 |4 aut | |
| 245 | 1 | 0 | |a Logic circuit design |b selected methods |c Shimon P. Vingron |
| 264 | 1 | |a Berlin [u.a.] |b Springer |c 2012 | |
| 300 | |a XIV, 258 S. |b graph. Darst. | ||
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Datensatz im Suchindex
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| adam_text |
IMAGE 1
CONTENTS
PART I COMBINATIONAL CIRCUITS
1 LOGIC VARIABLES AND EVENTS 3
1.1 SPECIFYING A CIRCUIT IN PLAIN PROSE 3
1.2 ANALOGUE AND BINARY TIMING DIAGRAMS 4
1.3 EVENTS GRAPH AND EVENTS TABLE* 7
1.4 LOGIC VARIABLES AND LOGIC FORMULAS* 9
1.5 DRAWING THE LOGIC CIRCUIT 11
2 SWITCHING DEVICES 13
2.1 PNEUMATIC VALVES 13
2.2 ELECTRIC RELAYS 17
2.3 CMOS TRANSISTORS 22
3 ELEMENTARY LOGIC FUNCTIONS 27
3.1 LOGIC FUNCTIONS 27
3.2 BASIC GATES 30
3.3 USING AND, OR AND NOT 33
3.4 BASIC LAWS 34
3.5 SINGLE-VARIABLE FORMULAS 35
3.6 COMMUTATIVE AND ASSOCIATIVE LAWS* 36
3.7 DISTRIBUTIVE LAWS* 37
3.8 GENERALISED DEMORGAN THEOREMS 39
4 NORMAL FORMS 41
4.1 MINTERMS AND MAX TERMS 41
4.2 CANONICAL NORMAL FORMS 4 3
4.3 USING CANONICAL NORMAL FORMS 44
4.4 ZHEGALKIN NORMAL FORM 4 6
4.5 DUAL ZHEGALKIN NORMAL FORM 48
X I
HTTP://D-NB.INFO/1018094679
IMAGE 2
X I I C O N T E N T S
5 KARNAUGH MAPS 51
5.1 HOW TO DRAW A KARNAUGH MAP 51
5.2 KARNAUGH SET AND CONJUNCTIVE TERM 53
5.3 PROVING AND DEVELOPING THEOREMS 57
5.4 EVALUATING KARNAUGH MAPS 59
5.5 KARNAUGH TREES AND MAP-ENTERED VARIABLES 63
6 ADJACENCY AND CONSENSUS 67
6.1 ADJACENT K-SETS AND THEIR CONSENSUS* 67
6.2 FORMALISING ADJACENCY 7 0
6.3 FORMALISING CONSENSUS 72
6.4 WHEN IS ONE K-SET A SUBSET O F ANOTHER? 73
7 ALGEBRAIC MINIMISATION 75
7.1 FINDING THE FULL COVER* 75
7.2 FINDING MINIMAL COVERS* 78
7.3 MINIMISATION CONSIDERING DON'T CARES* 81
8 DESIGN BY COMPOSITION* 85
8.1 THE BASIC CONCEPT 85
8.2 CATENATION 86
8.3 VISUALISING THE COMPOSITION PROBLEM 88
8.4 CHOOSING A GENERIC FUNCTION 89
8.5 COMPOSING A CIRCUIT: EXAMPLE 1 91
8.6 COMPOSING A CIRCUIT: EXAMPLE 2 95
8.7 COMPOSING A CIRCUIT: EXAMPLE 3 95
PART II LATCHES
9 BASIC THEORY O F LATCHES* 99
9.1 WHAT IS A LATCH? 99
9.2 THE MEMORY FUNCTION 101
9.3 INTRODUCING INCLUSIONS AND EXCLUSIONS 104
9.4 BASIC MEMORY EVALUATION-FORMULAS 106
9.5 GENERALISED MEMORY EVALUATION-FORMULAS 108
10 DESIGNING FEEDBACK LATCHES* I L L
10.1 FEEDBACK EVALUATION-FORMULAS I L L
10.2 DESIGN AND MEMORISATION HAZARDS 113
10.3 DELAYED FEEDBACK 117
10.4 PRE-ESTABLISHED FEEDBACK 120
10.5 MINIMISATION 122
11 ELEMENTARY LATCHES 125
11.1 CLASSIFICATION O F ELEMENTARY LATCHES 125
11.2 SYMBOLS FOR ELEMENTARY LATCHES* 128
11.3 PREDOMINANTLY MEMORISING LATCHES* 130
IMAGE 3
CONTENTS X I I I
11.4 PREDOMINANTLY SETTING AND RESETTING* 131
11.5 ECCLES-JORDAN LATCHES-THE PRINCIPLE 134
11.6 ECCLES-JORDAN LATCHES-THEIR SYMBOLS* 136
11.7 STANDARD SYMBOLS FOR LATCHES 138
12 LATCH COMPOSITION* 141
12.1 PRINCIPLE O F LATCH COMPOSITION 142
12.2 D-LATCH DESIGNS 146
12.3 PSR-LATCHES USING NAND OR NOR-GATES 150
12.4 SYNCHRONOUS LATCH-INPUTS 153
PART III ASYNCHRONOUS CIRCUITS
13 WORD-RECOGNITION TREE* 157
13.1 PRIORITY-AND 157
13.2 TWO-HAND SAFETY CIRCUIT 161
13.3 D-FLIPFLOP AND T-FLIPFLOP 163
13.4 JK-FLIPFLOP 166
14 HUFFMAN'S FLOW TABLE 169
14.1 MOORE-TYPE SEQUENTIAL AUTOMATON 169
14.2 PRIMITIVE FLOW-TABLE 172
14.3 SPECIFYING PRIORITY-AND CIRCUITS 173
14.4 SAMPLING AND SYNCHRONISING 175
14.5 PASSED-SAMPLE PROBLEM 178
14.6 EXPANDED TWO-HAND SAFETY PROBLEM 182
14.7 FROM FLOW TABLE TO EVENTS GRAPH 184
15 STATE-ENCODING BY ITERATIVE CATENATION* 1 87
15.1 CATENATION: FROM MOORE TO MEALY 187
15.2 ITERATIVE CATENATION 189
15.3 EXPANDED PRIORITY-AND 190
15.4 TWO-HAND SAFETY CIRCUITS 192
15.5 D-LATCH AND D-FLIPFLOP 193
15.6 PASSED-SAMPLE CIRCUIT 195
15.7 INCOMPLETELY SPECIFIED FLOW TABLES 199
16 CIRCUIT ANALYSIS 203
16.1 ANALYSING A CIRCUIT'S EXTERNAL BEHAVIOUR 203
16.2 FORMALISTIC ANALYSIS O F STATE TRANSITIONS 206
16.3 REALISTIC ANALYSIS AND ESSENTIAL HAZARDS 208
16.4 AVOIDING ESSENTIAL HAZARDS 214
17 STATE REDUCTION* 217
17.1 MERGING TOWARD A MOORE FLOW TABLE 218
17.2 MERGING TOWARD A MEALY FLOW TABLE 220
IMAGE 4
XIV C O N T E N T S
17.3 MERGING INCOMPLETELY SPECIFIED TABLES 222
17.4 MEALY-TYPE SEQUENTIAL AUTOMATON 224
18 VERIFYING A LOGIC DESIGN* 227
18.1 END-NODES AND THEIR EVENT GRAPHS 227
18.2 VERIFICATION TREE AND VERIFICATION GRAPH 229
18.3 VERIFICATION TABLE 234
18.4 VERIFICATION GRAPH FOR THE JK-FLIPFLOP 237
18.5 VERIFICATION GRAPH FOR THE D-LATCH 238
18.6 VERIFICATION GRAPH FOR THE D-FLIPFLOP 239
GLOSSARY 245
BIBLIOGRAPHY 251
INDEX 253 |
| any_adam_object | 1 |
| author | Vingron, Shimon Peter 1936- |
| author_GND | (DE-588)125011407 |
| author_facet | Vingron, Shimon Peter 1936- |
| author_role | aut |
| author_sort | Vingron, Shimon Peter 1936- |
| author_variant | s p v sp spv |
| building | Verbundindex |
| bvnumber | BV040261493 |
| classification_rvk | ZN 4904 ZN 5400 |
| ctrlnum | (OCoLC)794527920 (DE-599)DNB1018094679 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| institution | BVB |
| isbn | 3642276563 9783642276569 |
| language | English |
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| physical | XIV, 258 S. graph. Darst. |
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| spelling | Vingron, Shimon Peter 1936- Verfasser (DE-588)125011407 aut Logic circuit design selected methods Shimon P. Vingron Berlin [u.a.] Springer 2012 XIV, 258 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Literaturangaben Asynchrones Schaltwerk (DE-588)4271581-7 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Latch (DE-588)4219389-8 gnd rswk-swf Schaltnetz (DE-588)4052053-5 gnd rswk-swf Schaltungstheorie (DE-588)4179392-4 gnd rswk-swf Schaltnetz (DE-588)4052053-5 s Latch (DE-588)4219389-8 s Asynchrones Schaltwerk (DE-588)4271581-7 s Schaltungstheorie (DE-588)4179392-4 s Logischer Entwurf (DE-588)4168051-0 s DE-604 Erscheint auch als Online-Ausgabe 978-3-642-27657-6 X:MVB text/html http://deposit.dnb.de/cgi-bin/dokserv?id=3941220&prov=M&dok_var=1&dok_ext=htm Inhaltstext DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=025117266&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Vingron, Shimon Peter 1936- Logic circuit design selected methods Asynchrones Schaltwerk (DE-588)4271581-7 gnd Logischer Entwurf (DE-588)4168051-0 gnd Latch (DE-588)4219389-8 gnd Schaltnetz (DE-588)4052053-5 gnd Schaltungstheorie (DE-588)4179392-4 gnd |
| subject_GND | (DE-588)4271581-7 (DE-588)4168051-0 (DE-588)4219389-8 (DE-588)4052053-5 (DE-588)4179392-4 |
| title | Logic circuit design selected methods |
| title_auth | Logic circuit design selected methods |
| title_exact_search | Logic circuit design selected methods |
| title_full | Logic circuit design selected methods Shimon P. Vingron |
| title_fullStr | Logic circuit design selected methods Shimon P. Vingron |
| title_full_unstemmed | Logic circuit design selected methods Shimon P. Vingron |
| title_short | Logic circuit design |
| title_sort | logic circuit design selected methods |
| title_sub | selected methods |
| topic | Asynchrones Schaltwerk (DE-588)4271581-7 gnd Logischer Entwurf (DE-588)4168051-0 gnd Latch (DE-588)4219389-8 gnd Schaltnetz (DE-588)4052053-5 gnd Schaltungstheorie (DE-588)4179392-4 gnd |
| topic_facet | Asynchrones Schaltwerk Logischer Entwurf Latch Schaltnetz Schaltungstheorie |
| url | http://deposit.dnb.de/cgi-bin/dokserv?id=3941220&prov=M&dok_var=1&dok_ext=htm http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=025117266&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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