Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV040239071 | ||
| 003 | DE-604 | ||
| 005 | 20120618 | ||
| 007 | t | ||
| 008 | 120606s2003 a||| |||| 00||| eng d | ||
| 010 | |a 2002032433 | ||
| 020 | |a 0471429767 |9 0-471-42976-7 | ||
| 035 | |a (OCoLC)796270585 | ||
| 035 | |a (DE-599)BSZ108088901 | ||
| 040 | |a DE-604 |b ger | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-29T | ||
| 050 | 0 | |a TK7868.D5L42 2003 | |
| 100 | 1 | |a Lee, Weng Fook |e Verfasser |0 (DE-588)136005950 |4 aut | |
| 245 | 1 | 0 | |a Verilog coding for logic synthesis |c Weng Fook Lee |
| 264 | 1 | |a Hoboken, NJ |b Wiley |c 2003 | |
| 300 | |a XXVI, 309 S. |b Ill. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Digital electronics | |
| 650 | 4 | |a Logic circuits / Computer-aided design | |
| 650 | 4 | |a Verilog Computer hardware description language | |
| 856 | 4 | 2 | |m V:DE-576;X:wiley |q image/jpeg |u http://swbplus.bsz-bw.de/bsz108088901cov.htm |3 Cover |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-025095300 | ||
Datensatz im Suchindex
| _version_ | 1804149229901316096 |
|---|---|
| any_adam_object | |
| author | Lee, Weng Fook |
| author_GND | (DE-588)136005950 |
| author_facet | Lee, Weng Fook |
| author_role | aut |
| author_sort | Lee, Weng Fook |
| author_variant | w f l wf wfl |
| building | Verbundindex |
| bvnumber | BV040239071 |
| callnumber-first | T - Technology |
| callnumber-label | TK7868 |
| callnumber-raw | TK7868.D5L42 2003 |
| callnumber-search | TK7868.D5L42 2003 |
| callnumber-sort | TK 47868 D5 L42 42003 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| ctrlnum | (OCoLC)796270585 (DE-599)BSZ108088901 |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01013nam a2200325 c 4500</leader><controlfield tag="001">BV040239071</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20120618 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">120606s2003 a||| |||| 00||| eng d</controlfield><datafield tag="010" ind1=" " ind2=" "><subfield code="a">2002032433</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0471429767</subfield><subfield code="9">0-471-42976-7</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)796270585</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BSZ108088901</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-29T</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7868.D5L42 2003</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Lee, Weng Fook</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)136005950</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Verilog coding for logic synthesis</subfield><subfield code="c">Weng Fook Lee</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Hoboken, NJ</subfield><subfield code="b">Wiley</subfield><subfield code="c">2003</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXVI, 309 S.</subfield><subfield code="b">Ill.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Digital electronics</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic circuits / Computer-aided design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Verilog Computer hardware description language</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">V:DE-576;X:wiley</subfield><subfield code="q">image/jpeg</subfield><subfield code="u">http://swbplus.bsz-bw.de/bsz108088901cov.htm</subfield><subfield code="3">Cover</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-025095300</subfield></datafield></record></collection> |
| id | DE-604.BV040239071 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T00:19:43Z |
| institution | BVB |
| isbn | 0471429767 |
| language | English |
| lccn | 2002032433 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-025095300 |
| oclc_num | 796270585 |
| open_access_boolean | |
| owner | DE-29T |
| owner_facet | DE-29T |
| physical | XXVI, 309 S. Ill. |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | Wiley |
| record_format | marc |
| spelling | Lee, Weng Fook Verfasser (DE-588)136005950 aut Verilog coding for logic synthesis Weng Fook Lee Hoboken, NJ Wiley 2003 XXVI, 309 S. Ill. txt rdacontent n rdamedia nc rdacarrier Digital electronics Logic circuits / Computer-aided design Verilog Computer hardware description language V:DE-576;X:wiley image/jpeg http://swbplus.bsz-bw.de/bsz108088901cov.htm Cover |
| spellingShingle | Lee, Weng Fook Verilog coding for logic synthesis Digital electronics Logic circuits / Computer-aided design Verilog Computer hardware description language |
| title | Verilog coding for logic synthesis |
| title_auth | Verilog coding for logic synthesis |
| title_exact_search | Verilog coding for logic synthesis |
| title_full | Verilog coding for logic synthesis Weng Fook Lee |
| title_fullStr | Verilog coding for logic synthesis Weng Fook Lee |
| title_full_unstemmed | Verilog coding for logic synthesis Weng Fook Lee |
| title_short | Verilog coding for logic synthesis |
| title_sort | verilog coding for logic synthesis |
| topic | Digital electronics Logic circuits / Computer-aided design Verilog Computer hardware description language |
| topic_facet | Digital electronics Logic circuits / Computer-aided design Verilog Computer hardware description language |
| url | http://swbplus.bsz-bw.de/bsz108088901cov.htm |
| work_keys_str_mv | AT leewengfook verilogcodingforlogicsynthesis |