Parallel computer organization and design:
"Teaching fundamental design concepts and the challenges of emerging technology, this textbook prepares students for a career designing the computer systems of the future. In-depth coverage of complexity, power, reliability and performance, coupled with treatment of parallelism at all levels, i...
Gespeichert in:
Hauptverfasser: | , , |
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Format: | Buch |
Sprache: | English |
Veröffentlicht: |
Cambridge [u.a.]
Cambridge Univ. Press
2012
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Schlagworte: | |
Online-Zugang: | Inhaltsverzeichnis |
Zusammenfassung: | "Teaching fundamental design concepts and the challenges of emerging technology, this textbook prepares students for a career designing the computer systems of the future. In-depth coverage of complexity, power, reliability and performance, coupled with treatment of parallelism at all levels, including ILP and TLP, provides the state-of-the-art training that students need. The whole gamut of parallel architecture design options is explained, from core microarchitecture to chip multiprocessors to large-scale multiprocessor systems. All the chapters are self-contained, yet concise enough that the material can be taught in a single semester, making it perfect for use in senior undergraduate and graduate computer architecture courses. The book is also teeming with practical examples to aid the learning process, showing concrete applications of definitions. With simple models and codes used throughout, all material is made open to a broad range of computer engineering/science students with only a basic knowledge of hardware and software"-- |
Beschreibung: | Includes index Machine generated contents note: 1. Introduction; 2. Impact of technology; 3. Processor microarchitecture; 4. Memory hierarchies; 5. Multiprocessor systems; 6. Interconnection networks; 7. Coherence, synchronization, and memory consistency; 8. Chip multiprocessors; 9. Quantitative evaluations |
Beschreibung: | XVII, 542 S. graph. Darst. |
Internformat
MARC
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245 | 1 | 0 | |a Parallel computer organization and design |c Michel Dubois ; Murali Annavaram ; Per Stenström |
264 | 1 | |a Cambridge [u.a.] |b Cambridge Univ. Press |c 2012 | |
300 | |a XVII, 542 S. |b graph. Darst. | ||
336 | |b txt |2 rdacontent | ||
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338 | |b nc |2 rdacarrier | ||
500 | |a Includes index | ||
500 | |a Machine generated contents note: 1. Introduction; 2. Impact of technology; 3. Processor microarchitecture; 4. Memory hierarchies; 5. Multiprocessor systems; 6. Interconnection networks; 7. Coherence, synchronization, and memory consistency; 8. Chip multiprocessors; 9. Quantitative evaluations | ||
520 | |a "Teaching fundamental design concepts and the challenges of emerging technology, this textbook prepares students for a career designing the computer systems of the future. In-depth coverage of complexity, power, reliability and performance, coupled with treatment of parallelism at all levels, including ILP and TLP, provides the state-of-the-art training that students need. The whole gamut of parallel architecture design options is explained, from core microarchitecture to chip multiprocessors to large-scale multiprocessor systems. All the chapters are self-contained, yet concise enough that the material can be taught in a single semester, making it perfect for use in senior undergraduate and graduate computer architecture courses. The book is also teeming with practical examples to aid the learning process, showing concrete applications of definitions. With simple models and codes used throughout, all material is made open to a broad range of computer engineering/science students with only a basic knowledge of hardware and software"-- | ||
650 | 4 | |a Parallel computers | |
650 | 4 | |a Computer organization | |
650 | 7 | |a COMPUTERS / Computer Engineering |2 bisacsh | |
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650 | 0 | 7 | |a Parallelverarbeitung |0 (DE-588)4075860-6 |2 gnd |9 rswk-swf |
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689 | 0 | 2 | |a Paralleles Programm |0 (DE-588)4552796-9 |D s |
689 | 0 | |5 DE-604 | |
700 | 1 | |a Annavaram, Murali |e Verfasser |0 (DE-588)1032515651 |4 aut | |
700 | 1 | |a Stenström, Per |d 1957- |e Verfasser |0 (DE-588)173921027 |4 aut | |
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999 | |a oai:aleph.bib-bvb.de:BVB01-024825377 |
Datensatz im Suchindex
_version_ | 1804148945156308992 |
---|---|
adam_text | CONTENTS
Preface
page
χι
Introduction
і
1.1
What is computer architecture?
2
1.2
Components of a parallel architecture
5
1.3
Parallelism in architectures
13
1.4
Performance
17
1.5
Technological challenges
26
Exercises
30
Impact of technology
36
2.1
Chapter overview
36
2.2
Basic laws of electricity
37
2.3
The MOSFET transistor and CMOS inverter
39
2.4
Technology scaling
43
2.5
Power and energy
45
2.6
Reliability
54
Exercises
71
Processor microarchitecture
74
3.1
Chapter overview
74
3.2
Instruction set architecture
75
3.3
Statically scheduled pipelines
91
3.4
Dynamically scheduled pipelines
111
3.5
VLIW microarchitectures
140
3.6
EPIC microarchitectures
157
3.7
Vector microarchitectures
158
Exercises
165
Memory hierarchies
193
4.1
Chapter overview
193
4.2
The pyramid of memory levels
194
4.3
Cache hierarchy
198
4.4
Virtual memory
212
Exercises
224
viii Contents
5
Multiprocessor systems
232
5.1
Chapter overview
232
5.2
Parallel-programming model abstractions
233
5.3
Message-passing multiprocessor systems
239
5.4
Bus-based shared-memory systems
246
5.5
Scalable shared-memory systems
276
5.6
Cache-only shared-memory systems
293
Exercises
298
6
Interconnection networks
309
6.1
Chapter overview
309
6.2
Design space of interconnection networks
311
6.3
Switching strategies
ЗІ9
6.4
Topologies
322
6.5
Routing techniques
330
6.6
Switch architecture
337
Exercises
339
7
Coherence, synchronization, and memory consistency
342
7.1
Chapter overview
342
7.2
Background
344
7.3
Coherence and store atomicity
350
7.4
Sequential consistency
375
7.5
Synchronization
388
7.6
Relaxed memory-consistency models
398
7.7
Speculative violations of memory orders
411
Exercises
415
8
Chip multiprocessors
425
8.1
Chapter overview
425
8.2
Rationale behind CMPs
426
8.3
Core multi-threading
429
8.4
Chip multiprocessor architectures
446
8.5
Programming models
459
Exercises 4g2
Э
Quantitative evaluations
488
9.1
Chapter overview 4gg
9.2
Taxonomy of simulators 49Q
9.3
Integrating simulators
49g
9.4
Multiprocessor simulators 5OO
Contents ix
9.5 Power and
thermal simulations
508
9.6
Workload sampling
510
9.7
Workload characterization
514
Exercises
516
Index
521
|
any_adam_object | 1 |
author | Dubois, Michel 1953- Annavaram, Murali Stenström, Per 1957- |
author_GND | (DE-588)1025902491 (DE-588)1032515651 (DE-588)173921027 |
author_facet | Dubois, Michel 1953- Annavaram, Murali Stenström, Per 1957- |
author_role | aut aut aut |
author_sort | Dubois, Michel 1953- |
author_variant | m d md m a ma p s ps |
building | Verbundindex |
bvnumber | BV039967761 |
classification_rvk | ST 151 |
ctrlnum | (OCoLC)785854248 (DE-599)BVBBV039967761 |
dewey-full | 005.275 |
dewey-hundreds | 000 - Computer science, information, general works |
dewey-ones | 005 - Computer programming, programs, data, security |
dewey-raw | 005.275 |
dewey-search | 005.275 |
dewey-sort | 15.275 |
dewey-tens | 000 - Computer science, information, general works |
discipline | Informatik |
format | Book |
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id | DE-604.BV039967761 |
illustrated | Illustrated |
indexdate | 2024-07-10T00:15:11Z |
institution | BVB |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-024825377 |
oclc_num | 785854248 |
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owner_facet | DE-29T DE-83 DE-473 DE-BY-UBG DE-Aug4 DE-11 DE-20 |
physical | XVII, 542 S. graph. Darst. |
publishDate | 2012 |
publishDateSearch | 2012 |
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publisher | Cambridge Univ. Press |
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spelling | Dubois, Michel 1953- Verfasser (DE-588)1025902491 aut Parallel computer organization and design Michel Dubois ; Murali Annavaram ; Per Stenström Cambridge [u.a.] Cambridge Univ. Press 2012 XVII, 542 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Includes index Machine generated contents note: 1. Introduction; 2. Impact of technology; 3. Processor microarchitecture; 4. Memory hierarchies; 5. Multiprocessor systems; 6. Interconnection networks; 7. Coherence, synchronization, and memory consistency; 8. Chip multiprocessors; 9. Quantitative evaluations "Teaching fundamental design concepts and the challenges of emerging technology, this textbook prepares students for a career designing the computer systems of the future. In-depth coverage of complexity, power, reliability and performance, coupled with treatment of parallelism at all levels, including ILP and TLP, provides the state-of-the-art training that students need. The whole gamut of parallel architecture design options is explained, from core microarchitecture to chip multiprocessors to large-scale multiprocessor systems. All the chapters are self-contained, yet concise enough that the material can be taught in a single semester, making it perfect for use in senior undergraduate and graduate computer architecture courses. The book is also teeming with practical examples to aid the learning process, showing concrete applications of definitions. With simple models and codes used throughout, all material is made open to a broad range of computer engineering/science students with only a basic knowledge of hardware and software"-- Parallel computers Computer organization COMPUTERS / Computer Engineering bisacsh Verteilte Programmierung (DE-588)4421492-3 gnd rswk-swf Parallelverarbeitung (DE-588)4075860-6 gnd rswk-swf Paralleles Programm (DE-588)4552796-9 gnd rswk-swf Parallelverarbeitung (DE-588)4075860-6 s Verteilte Programmierung (DE-588)4421492-3 s Paralleles Programm (DE-588)4552796-9 s DE-604 Annavaram, Murali Verfasser (DE-588)1032515651 aut Stenström, Per 1957- Verfasser (DE-588)173921027 aut Digitalisierung UB Bamberg application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=024825377&sequence=000004&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
spellingShingle | Dubois, Michel 1953- Annavaram, Murali Stenström, Per 1957- Parallel computer organization and design Parallel computers Computer organization COMPUTERS / Computer Engineering bisacsh Verteilte Programmierung (DE-588)4421492-3 gnd Parallelverarbeitung (DE-588)4075860-6 gnd Paralleles Programm (DE-588)4552796-9 gnd |
subject_GND | (DE-588)4421492-3 (DE-588)4075860-6 (DE-588)4552796-9 |
title | Parallel computer organization and design |
title_auth | Parallel computer organization and design |
title_exact_search | Parallel computer organization and design |
title_full | Parallel computer organization and design Michel Dubois ; Murali Annavaram ; Per Stenström |
title_fullStr | Parallel computer organization and design Michel Dubois ; Murali Annavaram ; Per Stenström |
title_full_unstemmed | Parallel computer organization and design Michel Dubois ; Murali Annavaram ; Per Stenström |
title_short | Parallel computer organization and design |
title_sort | parallel computer organization and design |
topic | Parallel computers Computer organization COMPUTERS / Computer Engineering bisacsh Verteilte Programmierung (DE-588)4421492-3 gnd Parallelverarbeitung (DE-588)4075860-6 gnd Paralleles Programm (DE-588)4552796-9 gnd |
topic_facet | Parallel computers Computer organization COMPUTERS / Computer Engineering Verteilte Programmierung Parallelverarbeitung Paralleles Programm |
url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=024825377&sequence=000004&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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