Design for manufacturability and statistical design: a constructive approach
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| Main Authors: | , , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
New York
Springer
2008
|
| Series: | Integrated Circuits and Systems
|
| Subjects: | |
| Online Access: | Cover Kapitel#1 Einführung/Vorwort#1 Inhaltstext http://digitool.hbz-nrw.de:1801/webclient/DeliveryManager?pid=2345745&custom%5Fatt%5F2=simple%5Fviewer Inhaltsverzeichnis |
| Physical Description: | XIV, 310 S. Ill., graph. Darst. |
| ISBN: | 0387309284 9780387309286 |
Staff View
MARC
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Record in the Search Index
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| adam_text | Contents
1 INTRODUCTION 1
1.1 RISE OF LAYOUT CONTEXT DEPENDENCE 2
1.2 VARIABILITY AND UNCERTAINTY 3
1.3 CHARACTERIZATION VS. MODELING 5
1.4 MODEL TO HARDWARE MATCHING 6
1.5 DESIGN FOR MANUFACTURABILITY
VS. STATISTICAL DESIGN 6
Part I Sources of Variability
2 FRONT END VARIABILITY 11
2.1 INTRODUCTION 11
2.2 VARIABILITY OF GATE LENGTH 15
2.2.1 Gate Length Variability: Overview 15
2.2.2 Contributions of Photolithography 17
2.2.3 Impact of Etch 22
2.2.4 Line Edge Roughness 22
2.2.5 Models of Lgate Spatial Correlation 24
2.3 GATE WIDTH VARIABILITY 26
2.4 THRESHOLD VOLTAGE VARIABILITY 27
2.5 THIN FILM THICKNESS 32
2.6 LATTICE STRESS 35
2.7 VARIABILITY IN EMERGING DEVICES 36
2.8 PHYSICAL VARIATIONS DUE TO AGING
AND WEAROUT 39
2.9 SUMMARY 40
3 BACK END VARIABILITY 43
3.1 INTRODUCTION 43
3.2 COPPER CMP 44
3.3 COPPER ELECTROPLATING 47
xii Contents
3.4 MULTILEVEL COPPER INTERCONNECT VARIATION ... 50
3.5 INTERCONNECT LITHOGRAPHY AND ETCH
VARIATION 52
3.6 DIELECTRIC VARIATION 53
3.7 BARRIER METAL DEPOSITION 54
3.8 COPPER AND VIA RESISTIVITY 55
3.9 COPPER LINE EDGE ROUGHNESS 56
3.10 CARBON NANOTUBE INTERCONNECTS 56
3.11 SUMMARY 57
4 ENVIRONMENTAL VARIABILITY 59
4.1 INTRODUCTION 59
4.2 IMPACT OF ENVIRONMENTAL VARIABILITY 60
4.3 ANALYSIS OF VOLTAGE VARIABILITY 65
4.3.1 Power Grid Analysis 66
4.3.2 Estimation of Power Variability 69
4.4 SYSTEMATIC ANALYSIS OF TEMPERATURE
VARIABILITY 72
4.5 OTHER SOURCES OF VARIABILITY 80
4.6 SUMMARY 80
Part II Variability Characterization and Analysis
5 TEST STRUCTURES FOR VARIABILITY 83
5.1 TEST STRUCTURES: CLASSIFICATION AND FIGURES
OF MERIT 83
5.2 CHARACTERIZATION USING SHORT
LOOP FLOWS 85
5.3 TRANSISTOR TEST STRUCTURES 90
5.4 DIGITAL TEST STRUCTURES 93
5.5 SUMMARY 96
6 STATISTICAL FOUNDATIONS OF DATA ANALYSIS
AND MODELING 97
6.1 A BRIEF PROBABILITY PRIMER 98
6.2 EMPIRICAL MOMENT ESTIMATION 100
6.3 ANALYSIS OF VARIANCE AND ADDITIVE MODELS 102
6.4 CASE STUDIES: ANOVA FOR GATE LENGTH
VARIABILITY 105
6.5 DECOMPOSITION OF VARIANCE INTO SPATIAL
SIGNATURES 109
6.6 SPATIAL STATISTICS: DATA ANALYSIS
AND MODELING 113
6.6.1 Measurements and Data Analysis 113
6.6.2 Modeling of Spatial Variability 116
6.7 SUMMARY 119
Contents xiii
Part III Design Techniques for Systematic Manufacturability
Problems
7 LITHOGRAPHY ENHANCEMENT TECHNIQUES 123
7.1 FUNDAMENTALS OF LITHOGRAPHY 124
7.2 PROCESS WINDOW ANALYSIS 129
7.3 OPTICAL PROXIMITY CORRECTION AND SRAFS 133
7.4 SUBRESOLUTION ASSIST FEATURES 136
7.5 PHASE SHIFT MASKING 138
7.6 NON-CONVENTIONAL ILLUMINATION AND IMPACT
ON DESIGN 144
7.7 NOMINAL AND ACROSS PROCESS WINDOW
HOT SPOT ANALYSIS 145
7.8 TIMING ANALYSIS UNDER SYSTEMATIC VARIABILITY 147
7.9 SUMMARY 149
8 ENSURING INTERCONNECT PLANARITY 151
8.1 OVERVIEW OF DUMMY FILL 152
8.2 DUMMY FILL CONCEPT 155
8.3 ALGORITHMS FOR METAL FILL 155
8.4 DUMMY FILL FOR STI CMP AND OTHER PROCESSES .. 159
8.5 SUMMARY 159
Part IV Statistical Circuit Design
9 STATISTICAL CIRCUIT ANALYSIS 163
9.1 CIRCUIT PARAMETERIZATION AND SIMULATION 163
9.1.1 Introduction to Circuit Simulation 163
9.1.2 MOSFET Devices and Models 165
9.1.3 MOSFET Device Characterization 167
9.1.4 Statistical Device Characterization 170
9.1.5 Principal Component Analysis 171
9.2 WORST-CASE ANALYSIS 175
9.2.1 Worst-Case Analysis for Unbounded Parameters 176
9.2.2 Worst-Case Analysis Algorithm 177
9.2.3 Corner-Based Algorithm 179
9.2.4 Worst-Case Analysis Example 179
9.3 STATISTICAL CIRCUIT ANALYSIS 185
9.3.1 A Brief SRAM Tutorial 185
9.3.2 Monte Carlo Analysis 187
9.3.3 Response-Surface Analysis 189
9.3.4 Variance Reduction and Stratified Sampling
Analysis 192
xiv Contents
9.4 SUMMARY 195
10 STATISTICAL STATIC TIMING ANALYSIS 197
10.1 BASICS OF STATIC TIMING ANALYSIS 198
10.2 IMPACT OF VARIABILITY ON TRADITIONAL STATIC
TIMING VERIFICATION 201
10.2.1 Increased Design Conservatism 201
10.2.2 Cost of Full Coverage and Danger of Missing Timing
Violations 203
10.3 STATISTICAL TIMING EVALUATION 206
10.3.1 Problem Formulation and Challenges of SSTA 207
10.3.2 Block-Based Timing Algorithms 209
10.3.3 Path-Based Timing Algorithms 217
10.3.4 Parameter Space Techniques 223
10.3.5 Monte Carlo SSTA 226
10.4 STATISTICAL GATE LIBRARY CHARACTERIZATION ... 230
10.5 SUMMARY 233
11 LEAKAGE VARIABILITY AND JOINT PARAMETRIC
YIELD 235
11.1 LEAKAGE VARIABILITY MODELING 235
11.2 JOINT POWER AND TIMING PARAMETRIC YIELD
ESTIMATION 240
11.3 SUMMARY 245
12 PARAMETRIC YIELD OPTIMIZATION 247
12.1 LIMITATIONS OF TRADITIONAL OPTIMIZATION
FOR YIELD IMPROVEMENT 247
12.2 STATISTICAL TIMING YIELD OPTIMIZATION 254
12.2.1 Statistical Circuit Tuning 254
12.2.2 Linear Programming under Uncertainty 259
12.3 TECHNIQUES FOR TIMING AND POWER YIELD
IMPROVEMENT 266
12.4 SUMMARY 272
13 CONCLUSIONS 273
A APPENDIX: PROJECTING VARIABILITY 275
References 285
Index 303
|
| any_adam_object | 1 |
| author | Orshansky, Michael Nassif, Sani R. Boning, Duane S. |
| author_facet | Orshansky, Michael Nassif, Sani R. Boning, Duane S. |
| author_role | aut aut aut |
| author_sort | Orshansky, Michael |
| author_variant | m o mo s r n sr srn d s b ds dsb |
| building | Verbundindex |
| bvnumber | BV039807841 |
| classification_rvk | ZN 4900 |
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| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| spelling | Orshansky, Michael Verfasser aut Design for manufacturability and statistical design a constructive approach Michael Orshansky ; Sani Nassif ; Duane Boning New York Springer 2008 XIV, 310 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Integrated Circuits and Systems Electronic circuit design Fertigung (DE-588)4016899-2 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf CMOS (DE-588)4010319-5 gnd rswk-swf CMOS (DE-588)4010319-5 s Integrierte Schaltung (DE-588)4027242-4 s Fertigung (DE-588)4016899-2 s DE-604 Nassif, Sani R. Verfasser aut Boning, Duane S. Verfasser aut Erscheint auch als Online-Ausgabe 978-0-387-69011-7 V:DE-576;X:springer image/jpeg http://swbplus.bsz-bw.de/bsz272348694cov.htm Cover V:DE-576;X:springer application/pdf http://swbplus.bsz-bw.de/bsz272348694kap.htm Kapitel#1 V:DE-576;X:springer application/pdf http://swbplus.bsz-bw.de/bsz272348694vor.htm Einführung/Vorwort#1 text/html http://deposit.dnb.de/cgi-bin/dokserv?id=2813504&prov=M&dok%5Fvar=1&dok%5Fext=htm Inhaltstext http://digitool.hbz-nrw.de:1801/webclient/DeliveryManager?pid=2345745&custom%5Fatt%5F2=simple%5Fviewer Verlag HBZ Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=024668190&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Orshansky, Michael Nassif, Sani R. Boning, Duane S. Design for manufacturability and statistical design a constructive approach Electronic circuit design Fertigung (DE-588)4016899-2 gnd Integrierte Schaltung (DE-588)4027242-4 gnd CMOS (DE-588)4010319-5 gnd |
| subject_GND | (DE-588)4016899-2 (DE-588)4027242-4 (DE-588)4010319-5 |
| title | Design for manufacturability and statistical design a constructive approach |
| title_auth | Design for manufacturability and statistical design a constructive approach |
| title_exact_search | Design for manufacturability and statistical design a constructive approach |
| title_full | Design for manufacturability and statistical design a constructive approach Michael Orshansky ; Sani Nassif ; Duane Boning |
| title_fullStr | Design for manufacturability and statistical design a constructive approach Michael Orshansky ; Sani Nassif ; Duane Boning |
| title_full_unstemmed | Design for manufacturability and statistical design a constructive approach Michael Orshansky ; Sani Nassif ; Duane Boning |
| title_short | Design for manufacturability and statistical design |
| title_sort | design for manufacturability and statistical design a constructive approach |
| title_sub | a constructive approach |
| topic | Electronic circuit design Fertigung (DE-588)4016899-2 gnd Integrierte Schaltung (DE-588)4027242-4 gnd CMOS (DE-588)4010319-5 gnd |
| topic_facet | Electronic circuit design Fertigung Integrierte Schaltung CMOS |
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