A primer on memory consistency and cache coherence:
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
[San Rafael, Calif.]
Morgan & Claypool
2011
|
| Schriftenreihe: | Synthesis lectures on computer architecture
16 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XIII, 195 S. graph. Darst. |
| ISBN: | 9781608455645 |
Internformat
MARC
| LEADER | 00000nam a22000002cb4500 | ||
|---|---|---|---|
| 001 | BV037482750 | ||
| 003 | DE-604 | ||
| 005 | 20140124 | ||
| 007 | t | ||
| 008 | 110620s2011 d||| |||| 00||| eng d | ||
| 020 | |a 9781608455645 |c pbk |9 978-1-608-45564-5 | ||
| 035 | |a (OCoLC)734083517 | ||
| 035 | |a (DE-599)BSZ345776410 | ||
| 040 | |a DE-604 |b ger | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-473 |a DE-Aug4 |a DE-634 |a DE-91G |a DE-29T | ||
| 084 | |a ST 175 |0 (DE-625)143603: |2 rvk | ||
| 084 | |a DAT 406f |2 stub | ||
| 084 | |a DAT 212f |2 stub | ||
| 100 | 1 | |a Sorin, Daniel J. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a A primer on memory consistency and cache coherence |c Daniel J. Sorin, Mark D. Hill and David A. Wood |
| 264 | 1 | |a [San Rafael, Calif.] |b Morgan & Claypool |c 2011 | |
| 300 | |a XIII, 195 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Synthesis lectures on computer architecture |v 16 | |
| 650 | 0 | 7 | |a Pufferspeicher |0 (DE-588)4176324-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Konsistenz |g Informatik |0 (DE-588)4214306-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Speicher |g Informatik |0 (DE-588)4077653-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Speicher |g Informatik |0 (DE-588)4077653-0 |D s |
| 689 | 0 | 1 | |a Konsistenz |g Informatik |0 (DE-588)4214306-8 |D s |
| 689 | 0 | 2 | |a Pufferspeicher |0 (DE-588)4176324-5 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Hill, Mark D. |e Verfasser |4 aut | |
| 700 | 1 | |a Wood, David A. |e Verfasser |4 aut | |
| 776 | 0 | 8 | |i Erscheint auch als |n Online-Ausgabe |z 978-1-608-45565-2 |
| 830 | 0 | |a Synthesis lectures on computer architecture |v 16 |w (DE-604)BV023068349 |9 16 | |
| 856 | 4 | 2 | |m Digitalisierung UB Bamberg |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=022634292&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-022634292 | ||
Datensatz im Suchindex
| _version_ | 1804145794195914752 |
|---|---|
| adam_text | Preface
.......................................................................................................................ix
1.
Introduction
to Consistency and Coherence
.........................................................1
1.1
Consistency (a.k.a., Memory Consistency, Memory Consistency Model,
or Memory Model)
..............................................................................................2
1.2
Coherence (a.k.a., Cache Coherence)
..................................................................4
1.3
A Consistency and Coherence Quiz
....................................................................6
1.4
What this Primer Does Not Do
..........................................................................6
2.
Coherence Basics
................................................................................................9
2.1
Baseline System Model
.......................................................................................9
2.2
The Problem: How Incoherence Could Possibly Occur
....................................10
2.3
Defining Coherence
..........................................................................................11
2.3.1
Maintaining the Coherence Invariants
..................................................13
2.3.2
The Granularity of Coherence
..............................................................13
2.3.3
The Scope of Coherence
.......................................................................15
2.4
References
..........................................................................................................15
3.
Memory Consistency Motivation and Sequential Consistency
............................17
3.1
Problems with Shared Memory Behavior
..........................................................17
3.2
What Is a Memory Consistency Model?
...........................................................20
3.3
Consistency vs. Coherence
................................................................................21
3.4
Basic Idea of Sequential Consistency (SC)
........................................................22
3.5
A Little SC Formalism
......................................................................................24
3.6
Naive SC Implementations
...............................................................................26
3.7
A Basic SC Implementation with Cache Coherence
.........................................27
3.8
Optimized SC Implementations with Cache Coherence
..................................29
3.9
Atomic Operations with SC
..............................................................................32
3.10
Putting it All Together: MIPS R10000
.............................................................33
A PRIMER ON MEMORY CONSISTENCY AND CACHE COHERENCE
3.11
Further Reading Regarding SC
.........................................................................34
3.12
References
..........................................................................................................35
4.
Total Store Order and the x86 Memory Model
....................................................37
4.1
Motivation
ѓогТЅО/хбб
...................................................................................37
4.2
Basic Idea of TSO/X86
......................................................................................38
4.3
A Little TSO Formalism and an x86 Conjecture
..............................................42
4.4
Implementing
ТЅО/хбб
....................................................................................45
4.5
Atomic Instructions and Fences with TSO
.......................................................46
4.5.1
Atomic Instructions
...............................................................................46
4.5.2
Fences
....................................................................................................47
4.6
Further Reading RegardingTSO
......................................................................47
4.7
Comparing SC and TSO
...................................................................................48
4.8
References
..........................................................................................................49
5.
Relaxed Memory Consistency
............................................................................51
5.1
Motivation
.........................................................................................................51
5.1.1
Opportunities to Reorder Memory Operations
.....................................52
5.1.2
Opportunities to Exploit Reordering
....................................................53
5.2
An Example Relaxed Consistency Model
(XC)................................................55
5.2.1
The Basic Idea of the
XC
Model
...........................................................55
5.2.2
Examples Using Fences under
XC.........................................................56
5.2.3
Formalizing
XC.....................................................................................57
5.2.4
Examples Showing
XC
Operating Correctly
.........................................59
5.3
Implementing
XC.............................................................................................61
5.3.1
Atomic Instructions with
XC................................................................62
5.3.2
Fences with
XC.....................................................................................64
5.3.3
A Caveat
................................................................................................64
5.4
Sequential Consistency for Data-Race-Free Programs
.....................................64
5.5
Some Relaxed Model Concepts
.........................................................................68
5.5.1
Release Consistency
...............................................................................68
5.5.2
Causality and Write Atomicity
..............................................................69
5.6
A Relaxed Memory Model Case Study: IBM Power
........................................70
5.7
Further Reading and Commercial Relaxed Memory Models
............................74
5.7.1
Academic Literature
..............................................................................74
5.7.2
Commercial Models
..............................................................................74
CONTENTS
5.8
Comparing
Memory Models.............................................................................75
5.8.1
How Do Relaxed Memory Models Relate to Each Other and
TSOandSC?
........................................................................................75
5.8.2
How Good Are Relaxed Models?
..........................................................76
5.9
High-Level Language Models
..........................................................................76
5.10
References
..........................................................................................................79
6.
Coherence Protocols
.........................................................................................83
6.1
The Big Picture
.................................................................................................83
6.2
Specifying Coherence Protocols
........................................................................85
6.3
Example of a Simple Coherence Protocol
.........................................................86
6.4
Overview of Coherence Protocol Design Space
................................................88
6.4.1
States
.....................................................................................................88
6.4.2
Transactions
...........................................................................................92
6.4.3
Major Protocol Design Options
............................................................95
6.5
References
..........................................................................................................97
7.
Snooping Coherence Protocols
..........................................................................99
7.1
Introduction to Snooping
..................................................................................99
7.2
Baseline Snooping Protocol
.............................................................................103
7.2.1
High-Level Protocol Specification
......................................................104
7.2.2
Simple Snooping System Model: Atomic Requests,
Atomic Transactions
............................................................................104
7.2.3
Baseline Snooping System Model: Non-Atomic Requests,
Atomic Transactions
............................................................................109
7.2.4
Running Example
................................................................................113
7.2.5
Protocol Simplifications
.......................................................................114
7.3
Adding the Exclusive State
..............................................................................115
7.3.1
Motivation
...........................................................................................115
7.3.2
Getting to the Exclusive State
.............................................................115
7.3.3
High-Level Specification of Protocol
..................................................116
7.3.4
Detailed Specification
..........................................................................118
7.3.5
Running Example
................................................................................119
7.4
Adding the Owned State
.................................................................................119
7.4.1
Motivation
...........................................................................................119
7.4.2
High-Level Protocol Specification
......................................................121
xii
A PRIMER ON MEMORY CONSISTENCY AND CACHE COHERENCE
7.4.3
Detailed Protocol Specification
...........................................................121
7.4.4
Running Example
................................................................................122
7.5
Non-
Atomic Bus
.............................................................................................123
7.5.1
Motivation
...........................................................................................124
7.5.2
In-Order vs. Out-of-Order Responses
................................................124
7.5.3
Non-Atomic System Model
................................................................124
7.5.4
An MSI Protocol with a Split-Transaction Bus
..................................126
7.5.5
An Optimized, Non-Stalling MSI Protocol with a
Split-Transaction Bus
..........................................................................130
7.6
Optimizations to the Bus Interconnection Network
.......................................132
7.6.1
Separate Non-Bus Network for Data Responses
.................................132
7.6.2
Logical Bus for Coherence Requests
...................................................133
7.7
Case Studies
....................................................................................................133
7.7.1
Sun Starfire
ЕЮ000
............................................................................133
7.7.2
IBM Power5
........................................................................................135
7.8
Discussion and the Future of Snooping
...........................................................137
7.9
References
........................................................................................................138
8.
Directory Coherence Protocols
........................................................................139
8.1
Introduction to Directory Protocols
................................................................139
8.2
Baseline Directory System
...............................................................................141
8.2.1
Directory System Model
.....................................................................141
8.2.2
High-level Protocol Specification
........................................................142
8.2.3
Avoiding Deadlock
..............................................................................144
8.2.4
Detailed Protocol Specification
...........................................................146
8.2.5
Protocol Operation
..............................................................................147
8.2.6
Protocol Simplifications
.......................................................................149
8.3
Adding the Exclusive State
..............................................................................150
8.3.1
High-Level Protocol Specification
......................................................150
8.3.2
Detailed Protocol Specification
...........................................................152
8.4
Adding the Owned State
.................................................................................153
8.4.1
High-Level Protocol Specification
.....................................................153
8.4.2
Detailed Protocol Specification
.........................................................155
8.5
Representing Directory State
..........................................................................156
8.5.1
Coarse Directory
................................................................................157
8.5.2
Limited Pointer Directory
..................................................................157
CONTENTS xiii
8.6 Directory
Organization...................................................................................
158
8.6.1 Directory Cache
Backed by DRAM
...................................................159
8.6.2
Inclusive
Directory Caches..................................................................160
8.6.3 Null Directory Cache
(with no backing store)
.....................................163
8.7
Performance and Scalability Optimizations
.....................................................163
8.7.1
Distributed Directories
........................................................................163
8.7.2
Non-Stalling Directory Protocols
........................................................164
8.7.3
Interconnection Networks without Point-to-Point Ordering
..............166
8.7.4
Silent vs. Non-Silent Evictions of Blocks in State
S
...........................168
8.8
Case Studies
....................................................................................................169
8.8.1
SGI Origin
2000.................................................................................169
8.8.2
Coherent
HyperTransport...................................................................171
8.8.3 HyperTransport
Assist
.........................................................................172
8.8.4
Intel QPI
.............................................................................................173
8.9
Discussion and the Future of Directory Protocols
...........................................175
8.10
References
........................................................................................................175
9.
Advanced Topics in Coherence
........................................................................177
9.1
System Models
................................................................................................177
9.1.1
Instruction Caches
...............................................................................177
9.1.2
Translation Lookaside Buffers (TLBs)
................................................178
9.1.3
Virtual Caches
.....................................................................................179
9.1.4
Write-Through Caches
.......................................................................180
9.1.5
Coherent Direct Memory Access (DMA)
...........................................180
9.1.6
Multi-Level Caches and Hierarchical Coherence Protocols
...............181
9.2
Performance Optimizations
.............................................................................184
9.2.1
Migratory Sharing Optimization
........................................................184
9.2.2
False Sharing Optimizations
...............................................................185
9.3
Maintaining Liveness
......................................................................................186
9.3.1
Deadlock
.............................................................................................186
9.3.2
Livelock
...............................................................................................189
9.3.3
Starvation
............................................................................................192
9.4
Token Coherence
.............................................................................................193
9.5
The Future of Coherence
................................................................................193
9.6
References
........................................................................................................193
Author Biographies
..................................................................................................195
|
| any_adam_object | 1 |
| author | Sorin, Daniel J. Hill, Mark D. Wood, David A. |
| author_facet | Sorin, Daniel J. Hill, Mark D. Wood, David A. |
| author_role | aut aut aut |
| author_sort | Sorin, Daniel J. |
| author_variant | d j s dj djs m d h md mdh d a w da daw |
| building | Verbundindex |
| bvnumber | BV037482750 |
| classification_rvk | ST 175 |
| classification_tum | DAT 406f DAT 212f |
| ctrlnum | (OCoLC)734083517 (DE-599)BSZ345776410 |
| discipline | Informatik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01893nam a22004452cb4500</leader><controlfield tag="001">BV037482750</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20140124 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">110620s2011 d||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781608455645</subfield><subfield code="c">pbk</subfield><subfield code="9">978-1-608-45564-5</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)734083517</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BSZ345776410</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-473</subfield><subfield code="a">DE-Aug4</subfield><subfield code="a">DE-634</subfield><subfield code="a">DE-91G</subfield><subfield code="a">DE-29T</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 175</subfield><subfield code="0">(DE-625)143603:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 406f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 212f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Sorin, Daniel J.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">A primer on memory consistency and cache coherence</subfield><subfield code="c">Daniel J. Sorin, Mark D. Hill and David A. Wood</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">[San Rafael, Calif.]</subfield><subfield code="b">Morgan & Claypool</subfield><subfield code="c">2011</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XIII, 195 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Synthesis lectures on computer architecture</subfield><subfield code="v">16</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Pufferspeicher</subfield><subfield code="0">(DE-588)4176324-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Konsistenz</subfield><subfield code="g">Informatik</subfield><subfield code="0">(DE-588)4214306-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Speicher</subfield><subfield code="g">Informatik</subfield><subfield code="0">(DE-588)4077653-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Speicher</subfield><subfield code="g">Informatik</subfield><subfield code="0">(DE-588)4077653-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Konsistenz</subfield><subfield code="g">Informatik</subfield><subfield code="0">(DE-588)4214306-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">Pufferspeicher</subfield><subfield code="0">(DE-588)4176324-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Hill, Mark D.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Wood, David A.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Online-Ausgabe</subfield><subfield code="z">978-1-608-45565-2</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Synthesis lectures on computer architecture</subfield><subfield code="v">16</subfield><subfield code="w">(DE-604)BV023068349</subfield><subfield code="9">16</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Digitalisierung UB Bamberg</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=022634292&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-022634292</subfield></datafield></record></collection> |
| id | DE-604.BV037482750 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T23:25:06Z |
| institution | BVB |
| isbn | 9781608455645 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-022634292 |
| oclc_num | 734083517 |
| open_access_boolean | |
| owner | DE-473 DE-BY-UBG DE-Aug4 DE-634 DE-91G DE-BY-TUM DE-29T |
| owner_facet | DE-473 DE-BY-UBG DE-Aug4 DE-634 DE-91G DE-BY-TUM DE-29T |
| physical | XIII, 195 S. graph. Darst. |
| publishDate | 2011 |
| publishDateSearch | 2011 |
| publishDateSort | 2011 |
| publisher | Morgan & Claypool |
| record_format | marc |
| series | Synthesis lectures on computer architecture |
| series2 | Synthesis lectures on computer architecture |
| spelling | Sorin, Daniel J. Verfasser aut A primer on memory consistency and cache coherence Daniel J. Sorin, Mark D. Hill and David A. Wood [San Rafael, Calif.] Morgan & Claypool 2011 XIII, 195 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Synthesis lectures on computer architecture 16 Pufferspeicher (DE-588)4176324-5 gnd rswk-swf Konsistenz Informatik (DE-588)4214306-8 gnd rswk-swf Speicher Informatik (DE-588)4077653-0 gnd rswk-swf Speicher Informatik (DE-588)4077653-0 s Konsistenz Informatik (DE-588)4214306-8 s Pufferspeicher (DE-588)4176324-5 s DE-604 Hill, Mark D. Verfasser aut Wood, David A. Verfasser aut Erscheint auch als Online-Ausgabe 978-1-608-45565-2 Synthesis lectures on computer architecture 16 (DE-604)BV023068349 16 Digitalisierung UB Bamberg application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=022634292&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Sorin, Daniel J. Hill, Mark D. Wood, David A. A primer on memory consistency and cache coherence Synthesis lectures on computer architecture Pufferspeicher (DE-588)4176324-5 gnd Konsistenz Informatik (DE-588)4214306-8 gnd Speicher Informatik (DE-588)4077653-0 gnd |
| subject_GND | (DE-588)4176324-5 (DE-588)4214306-8 (DE-588)4077653-0 |
| title | A primer on memory consistency and cache coherence |
| title_auth | A primer on memory consistency and cache coherence |
| title_exact_search | A primer on memory consistency and cache coherence |
| title_full | A primer on memory consistency and cache coherence Daniel J. Sorin, Mark D. Hill and David A. Wood |
| title_fullStr | A primer on memory consistency and cache coherence Daniel J. Sorin, Mark D. Hill and David A. Wood |
| title_full_unstemmed | A primer on memory consistency and cache coherence Daniel J. Sorin, Mark D. Hill and David A. Wood |
| title_short | A primer on memory consistency and cache coherence |
| title_sort | a primer on memory consistency and cache coherence |
| topic | Pufferspeicher (DE-588)4176324-5 gnd Konsistenz Informatik (DE-588)4214306-8 gnd Speicher Informatik (DE-588)4077653-0 gnd |
| topic_facet | Pufferspeicher Konsistenz Informatik Speicher Informatik |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=022634292&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV023068349 |
| work_keys_str_mv | AT sorindanielj aprimeronmemoryconsistencyandcachecoherence AT hillmarkd aprimeronmemoryconsistencyandcachecoherence AT wooddavida aprimeronmemoryconsistencyandcachecoherence |