SystemVerilog for verification: a guide to learning the testbench language features
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
Springer
2010
|
| Ausgabe: | 2. ed. |
| Schlagworte: | |
| Beschreibung: | XXXVI, 429 S. Ill., graph. Darst. 235 mm x 155 mm |
| ISBN: | 9781441945617 |
Internformat
MARC
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|---|---|---|---|
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| 003 | DE-604 | ||
| 005 | 20110705 | ||
| 007 | t | ||
| 008 | 110615s2010 ad|| |||| 00||| eng d | ||
| 020 | |a 9781441945617 |9 978-1-4419-4561-7 | ||
| 035 | |a (OCoLC)734078825 | ||
| 035 | |a (DE-599)BVBBV037473776 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91 | ||
| 050 | 0 | |a TK7885.7 | |
| 082 | 0 | |a 621.39/2 |2 22 | |
| 084 | |a ST 250 |0 (DE-625)143626: |2 rvk | ||
| 084 | |a ZN 4010 |0 (DE-625)157337: |2 rvk | ||
| 084 | |a ZN 4030 |0 (DE-625)157339: |2 rvk | ||
| 084 | |a DAT 190f |2 stub | ||
| 100 | 1 | |a Spear, Chris |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a SystemVerilog for verification |b a guide to learning the testbench language features |c Chris Spear |
| 250 | |a 2. ed. | ||
| 264 | 1 | |a New York, NY |b Springer |c 2010 | |
| 300 | |a XXXVI, 429 S. |b Ill., graph. Darst. |c 235 mm x 155 mm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Integrated circuits |x Verification | |
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 0 | |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-022625465 | ||
Datensatz im Suchindex
| _version_ | 1804145783263461376 |
|---|---|
| any_adam_object | |
| author | Spear, Chris |
| author_facet | Spear, Chris |
| author_role | aut |
| author_sort | Spear, Chris |
| author_variant | c s cs |
| building | Verbundindex |
| bvnumber | BV037473776 |
| callnumber-first | T - Technology |
| callnumber-label | TK7885 |
| callnumber-raw | TK7885.7 |
| callnumber-search | TK7885.7 |
| callnumber-sort | TK 47885.7 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 250 ZN 4010 ZN 4030 |
| classification_tum | DAT 190f |
| ctrlnum | (OCoLC)734078825 (DE-599)BVBBV037473776 |
| dewey-full | 621.39/2 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/2 |
| dewey-search | 621.39/2 |
| dewey-sort | 3621.39 12 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 2. ed. |
| format | Book |
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| id | DE-604.BV037473776 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T23:24:56Z |
| institution | BVB |
| isbn | 9781441945617 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-022625465 |
| oclc_num | 734078825 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM |
| owner_facet | DE-91 DE-BY-TUM |
| physical | XXXVI, 429 S. Ill., graph. Darst. 235 mm x 155 mm |
| publishDate | 2010 |
| publishDateSearch | 2010 |
| publishDateSort | 2010 |
| publisher | Springer |
| record_format | marc |
| spelling | Spear, Chris Verfasser aut SystemVerilog for verification a guide to learning the testbench language features Chris Spear 2. ed. New York, NY Springer 2010 XXXVI, 429 S. Ill., graph. Darst. 235 mm x 155 mm txt rdacontent n rdamedia nc rdacarrier Integrated circuits Verification Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd rswk-swf VERILOG (DE-588)4268385-3 s DE-604 |
| spellingShingle | Spear, Chris SystemVerilog for verification a guide to learning the testbench language features Integrated circuits Verification Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4268385-3 |
| title | SystemVerilog for verification a guide to learning the testbench language features |
| title_auth | SystemVerilog for verification a guide to learning the testbench language features |
| title_exact_search | SystemVerilog for verification a guide to learning the testbench language features |
| title_full | SystemVerilog for verification a guide to learning the testbench language features Chris Spear |
| title_fullStr | SystemVerilog for verification a guide to learning the testbench language features Chris Spear |
| title_full_unstemmed | SystemVerilog for verification a guide to learning the testbench language features Chris Spear |
| title_short | SystemVerilog for verification |
| title_sort | systemverilog for verification a guide to learning the testbench language features |
| title_sub | a guide to learning the testbench language features |
| topic | Integrated circuits Verification Verilog (Computer hardware description language) VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Integrated circuits Verification Verilog (Computer hardware description language) VERILOG |
| work_keys_str_mv | AT spearchris systemverilogforverificationaguidetolearningthetestbenchlanguagefeatures |