Design of digital systems and devices:
Gespeichert in:
| Weitere Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Berlin [u.a.]
Springer
2011
|
| Schriftenreihe: | Lecture notes in electrical engineering
79 |
| Schlagworte: | |
| Online-Zugang: | Inhaltstext Inhaltsverzeichnis |
| Beschreibung: | XVII, 365 S. graph. Darst. |
| ISBN: | 3642175449 9783642175442 |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV037345912 | ||
| 003 | DE-604 | ||
| 005 | 20110603 | ||
| 007 | t | ||
| 008 | 110418s2011 d||| |||| 00||| eng d | ||
| 015 | |a 10N44 |2 dnb | ||
| 016 | 7 | |a 1007904240 |2 DE-101 | |
| 020 | |a 3642175449 |9 3-642-17544-9 | ||
| 020 | |a 9783642175442 |9 978-3-642-17544-2 | ||
| 035 | |a (OCoLC)707101445 | ||
| 035 | |a (DE-599)DNB1007904240 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-634 |a DE-83 | ||
| 082 | 0 | |a 621.395 |2 22/ger | |
| 082 | 0 | |a 621.392 |2 22/ger | |
| 084 | |a ZN 5600 |0 (DE-625)157468: |2 rvk | ||
| 084 | |a 621.3 |2 sdnb | ||
| 245 | 1 | 0 | |a Design of digital systems and devices |c Marian Adamski ... (eds.) |
| 264 | 1 | |a Berlin [u.a.] |b Springer |c 2011 | |
| 300 | |a XVII, 365 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Lecture notes in electrical engineering |v 79 | |
| 650 | 0 | 7 | |a Testen |0 (DE-588)4367264-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a UML |0 (DE-588)4469781-8 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Fehlersimulation |0 (DE-588)4234819-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Digitaltechnik |0 (DE-588)4012303-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Fehlererkennung |0 (DE-588)4133764-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a CAD |0 (DE-588)4069794-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Digitales System |0 (DE-588)4012300-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Logiksynthese |0 (DE-588)4348178-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Programmierbare logische Anordnung |0 (DE-588)4076369-9 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Digitalschaltung |0 (DE-588)4012295-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Fehlertoleranz |0 (DE-588)4123192-2 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Systementwurf |0 (DE-588)4261480-6 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)4143413-4 |a Aufsatzsammlung |2 gnd-content | |
| 689 | 0 | 0 | |a Digitales System |0 (DE-588)4012300-5 |D s |
| 689 | 0 | 1 | |a Systementwurf |0 (DE-588)4261480-6 |D s |
| 689 | 0 | 2 | |a CAD |0 (DE-588)4069794-0 |D s |
| 689 | 0 | 3 | |a UML |0 (DE-588)4469781-8 |D s |
| 689 | 0 | 4 | |a Programmierbare logische Anordnung |0 (DE-588)4076369-9 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Digitalschaltung |0 (DE-588)4012295-5 |D s |
| 689 | 1 | 1 | |a Logiksynthese |0 (DE-588)4348178-4 |D s |
| 689 | 1 | 2 | |a Programmierbare logische Anordnung |0 (DE-588)4076369-9 |D s |
| 689 | 1 | |5 DE-604 | |
| 689 | 2 | 0 | |a Digitaltechnik |0 (DE-588)4012303-0 |D s |
| 689 | 2 | 1 | |a Testen |0 (DE-588)4367264-4 |D s |
| 689 | 2 | 2 | |a Fehlersimulation |0 (DE-588)4234819-5 |D s |
| 689 | 2 | 3 | |a Fehlererkennung |0 (DE-588)4133764-5 |D s |
| 689 | 2 | 4 | |a Fehlertoleranz |0 (DE-588)4123192-2 |D s |
| 689 | 2 | |5 DE-604 | |
| 700 | 1 | |a Adamski, Marian |4 edt | |
| 776 | 0 | 8 | |i Erscheint auch als |n Online-Ausgabe |z 978-3-642-17545-9 |
| 830 | 0 | |a Lecture notes in electrical engineering |v 79 |w (DE-604)BV022422356 |9 79 | |
| 856 | 4 | |q text/html |u http://deposit.dnb.de/cgi-bin/dokserv?id=3554082&prov=M&dok_var=1&dok_ext=htm |3 Inhaltstext | |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=022499505&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-022499505 | |
Datensatz im Suchindex
| _version_ | 1805095849248686080 |
|---|---|
| adam_text |
IMAGE 1
CONTENTS
ABOUT THE EDITORS XI
FOREWORD XIII
PART I: SYSTEM DESIGN
1 DIGITAL SYSTEM DESIGN 3
1.1 MAIN PROCESSOR UNITS AND INSTRUCTION SETS 3
1.1.1 MAIN UNITS 3
1.1.2 INSTRUCTION SET AND INSTRUCTION FORMATS 5
1.1.3 ADDRESSING MODES 6
1.2 ASMS FOR PROCESSOR INSTRUCTIONS 8
1.3 DATA PATH DESIGN 15
1.3.1 COMBINED FUNCTIONAL ASM 15
1.3.2 PROCESS TABLE AND CONNECTION GRAPH 19
1.3.3 GRAPH OF INCOMPATIBILITY. MAIN MUXES AND DIRECT CONNECTIONS 24
1.4 CONTROL UNIT DESIGN 28
1.4.1 TRANSFORMATION OF FUNCTIONAL ASM INTO STRUCTURAL ASM 28 1.4.2
SYNTHESIS THE FINITE STATE MACHINE (FSM) FROM ASM 32 1.4.3 SYNTHESIS OF
CONTROL UNIT (FSM) FOR PROCESSOR 34
1.4.4 ENCODING OF INPUTS OF MUXES 38
1.5 CONCLUSIONS 39
REFERENCES 41
2 RECTANGULAR FUNCTION II(X) AND ITS APPLICATION FOR DESCRIPTION OF SOME
LOGICAL DEVICES OPERATION 43
2.1 INTRODUCTION 43
2.2 LOGIC OPERATIONS ON RECTANGULAR FUNCTIONS 44
A. LOGIC SUM 44
B. LOGIC PRODUCT 44
C. NEGATION 45
BIBLIOGRAFISCHE INFORMATIONEN HTTP://D-NB.INFO/1007904240
DIGITALISIERT DURCH
IMAGE 2
VI CONTENTS
D. EX-OR (LOGIC INEQUALITY) 45
E. BINARY COUNTERS 46
2.3 UTILIZATION OF THE RECTANGULAR FUNCTIONS IT(X) FOR ANALYSIS OF PULSE
OR FREQUENCY MULTIPLYING 47
2.4 UTILIZING THE FUNCTION II(X) FOR HARMONIC ANALYSIS OF DIGITAL SINE
WAVE GENERATOR 49
2.4.1 DIGITAL SINE WAVE GENERATOR BASED ON DIGITAL INTEGRATORS 49 2.4.2
DIGITAL SINE WAVE GENERATOR BASED ON ROM 52
2.5 CONCLUSIONS 56
REFERENCES 57
3 DESIGN AND APPLICATION OF THE PLD-BASED RECONFIGURABLE DEVICES 59 3.1
INTRODUCTION 59
3.2 EVOLUTION OF COMPUTER SYSTEMS 61
3.3 ARCHITECTURE AND STRUCTURE OF PLD-BASED COMPUTER SYSTEMS 63 3.4
ADAPTIVE LOGICAL NETWORK (ALN) 67
3.5 PROBLEM-ORIENTED STRUCTURES OF DIGITAL DEVICES 70
3.5.1 FUNCTIONAL BLOCKS WITH A FLOATING POINT 70
3.5.2 FUNCTIONAL BLOCKS FOR MULTIPLICATION OF MATRIXES 75 3.5.3
DESIGNING AND REALIZATION OF MEDIAN FILTERS 76
3.5.4 HEMMING ADDER REALIZATION 84
3.6. VERIFICATION OF PROJECTS BY MEANS OF STANDS 85
3.7 RECONFIGURABLE PROCESSORS 88
3.8 CONCLUSIONS 89
REFERENCES 91
4 APPLICATION OF MULTILEVEL DESIGN ON THE BASE OF UML FOR DIGITAL SYSTEM
DEVELOPING 93
4.1 INTRODUCTION 93
4.2 FEATURES OF DIGITAL SYSTEMS FOR REAL-TIME IMAGE GENERATION 94 4.2.1
ESTIMATION OF THE COMPLEXITY OF THE STANDARD RENDERING PIPELINE 94
SCENE MANAGER 94
MODELING TRANSFORMATION 95
TRIVIAL ACCEPT/REJECT CLASSIFICATION 95
LIGHTING 96
VIEWING TRANSFORMATION 96
CLIPPING 96
DIVISION BY W AND MAPPING TO 3D VIEWPORT 97
RASTERIZATION 97
ESTIMATION OF THE COMPLEXITY OF GEOMETRY CALCULATIONS 98 4.2.2 THE
ARCHITECTURAL DECISIONS AND ALGORITHM APPROACHES FOR THE REAL-TIME
RENDERING SYSTEMS 98
PIPELINED OBJECT-ORDER ARCHITECTURES 99
IMAGE 3
CONTENTS VII
IMAGE-ORDER ARCHITECTURES 99
COMPARING OF ARCHITECTURES 100
4.3 DESIGNING OF SPECIALIZED PROCESSORS 100
4.3.1 SCENE PROCESSOR 100
4.3.2 CLIPPING PROCESSOR 108
4.4 APPLICATION OF RUNTIME RECONFIGURATION 109
4.5 APPLICATION OF UML FOR HDL-CODE CREATION 110
4.5.1 EXAMPLE FOR 2D CLIPPING REALIZATION 112
4.5.2 FRAGMENT OF HDL FOR SCENE PROCESSOR SIMULATION 114 4.6 SUMMARY AND
FUTURE DIRECTIONS 116
REFERENCES 116
PART II: DIGITAL DESIGN WITH PROGRAMMABLE LOGIC
5 LOGIC SYNTHESIS METHOD OF DIGITAL CIRCUITS DESIGNED FOR IMPLEMENTATION
WITH EMBEDDED MEMORY BLOCKS OF FPGAS 121 5.1 INTRODUCTION 121
5.2 DECOMPOSITION OF BOOLEAN FUNCTIONS 122
5.2.1 FUNCTIONAL DECOMPOSITION 122
5.2.2 DECOMPOSITION INTO EMB BLOCKS 125
5.2.3 PARALLEL DECOMPOSITION 126
5.2.4 BALANCED DECOMPOSITION ; 128
5.3 SEQUENTIAL CIRCUITS SYNTHESIS 130
5.3.1 BASIC INFORMATION 131
5.3.2 IMPLEMENTATION OF FINITE STATE MACHINES IN FPGA'S 132 5.3.3 STATES
ENCODING 133
5.3.4 CONSTRUCTION OF PARTITION P G 136
5.3.5 APPLICATION OF THE METHOD 138
5.4 EXPERIMENTAL RESULTS 139
5.5 CONCLUSIONS 142
REFERENCES 142
6 EFFICIENT TECHNOLOGY MAPPING METHOD FOR PAL-BASED DEVICES 145 6.1
INTRODUCTION 145
6.2 THEORETICAL BACKGROUNDS 147
6.3 TECHNOLOGY MAPPING ALGORITHM 150
EXAMPLE 152
6.4 EXPERIMENTAL RESULTS 154
6.5 CONCLUSIONS 157
REFERENCES 157
APPENDIX 159
IMAGE 4
VIII CONTENTS
7 RELIABLE FPGA-BASED SYSTEMS OUT OF UNRELIABLE AUTOMATA: MULTI-VERSION
DESIGN USING GENETIC ALGORITHMS 165
7.1 INTRODUCTION 165
7.2 EXTERNAL AND INTERNAL DESIGN DIVERSITY 167
7.3 PARTIALLY DEFINITE AND PARTIALLY CORRECT AUTOMATA 170
7.4 RELIABILITY OF DIGITAL SYSTEMS OUT OF UNRELIABLE AUTOMATA 173 7.5
DESIGNING DIGITAL SYSTEMS OUT OF UNRELIABLE AUTOMATA 176 7.5.1 GENERAL
GA-BASED APPROACH 176
7.5.2 PHASE 1: OBTAINING A SYSTEM MODEL 178
7.5.3 PHASE 2: INCREASING THE RELIABILITY OF DIGITAL SYSTEMS OUT OF
UNRELIABLE AUTOMATA 180
7.5.4 PHASE 3: DEVELOPMENT OF SWITCHING SUBSYSTEM 182 7.5.5
IMPLEMENTATION 183
7.6 EXPERIMENTAL APPLICATION 184
7.7 CONCLUSIONS 190
REFERENCES 191
8 SYNTHESIS OF COMPOSITIONAL MICROPROGRAM CONTROL UNIT WITH DEDICATED
AREA OF INPUTS 193
8.1 INTRODUCTION 193
8.2 BACKGROUND OF CMCU 194
8.3 SYNTHESIS OF CMCU WITH DEDICATED AREA OF INPUTS 197
8.4 OPTIMIZATION OF COMPOSITIONAL MICROPROGRAM CONTROL UNIT WITH THE
DEDICATED INPUT AREA 208
8.5 CONCLUSIONS 213
REFERENCES 213
9 PENLOGIC - SYSTEM FOR CONCURRENT LOGIC CONTROLLERS DESIGN 215 9.1
INTRODUCTION 215
9.2 PENLOGIC SYSTEM 216
9.2.1 PETRI NET MODELING OF CONCURRENT CONTROLLERS 216
AN EXAMPLE 217
9.2.2 ANALYSIS OF PETRI NET 218
9.2.3 HDL MODELING, SIMULATION AND SYNTHESIS 220
VHDL MODELING 220
VERILOG MODELING 221
9.2.4 PETRI NETS DECOMPOSITION 221
DECOMPOSITION INTO SM-COMPONENTS 223
VERILOG MODELING AND SYNTHESIS 224
9.2.5 DIRECT MAPPING INTO NETLIST 226
9.3 CONCLUSIONS 227
REFERENCES 227
IMAGE 5
CONTENTS IX
PART III: TESTING, MODELING AND SIGNAL PROCESSING
10 METHODS OF SIGNALS PROCESSING IN RADIO ACCESS NETWORKS 231 10.1
GENERAL INFORMATION 231
10.2 SPECIFIC FEATURES OF RADIO ACCESS AT PHYSICAL LEVEL 233 10.2.1
GENERAL DESCRIPTION OF PHYSICAL PROCESSES AT RADIO ACCESS 233
10.2.2 SPACE-TIME ACCESS METHOD 235
10.2.3 POLARIZATION IN ACCESS TASKS 239
10.2.4 ADAPTATION IN THE TASKS OF ACCESS 241
10.2.5 SUPPRESSION (REJECTION) OF INTERFERENCE. ADAPTIVE ANTENNA ARRAYS
AND ADAPTIVE INTERFERENCE CANCELLERS 241 10.2.6 CONTROL OF MULTIPATH
EFFECT IN ACCESS RADIO LINES 246 10.2.7 SPACE-TIME CODING 250
10.3 RECOMMENDATIONS ON PRACTICAL USE OF SIGNAL PROCESSING ALGORITHMS
252
10.3.1 FORMALIZATION OF KALMAN-BUCY ALGORITHM 252 10.3.2 RECOMMENDATIONS
ON PLANNING OF ESTIMATION ALGORITHMS. 253 10.3.3 PROGRAM OF ESTIMATION
CALCULATION WITH THE HELP OF FKB.256 10.3.4 RECOMMENDATIONS FOR
DESIGNING ADAPTIVE NOISE
COMPENSATORS 257
10.3.5 RECOMMENDATIONS FOR PLANNING ADAPTIVE ANTENNA ARRAYS. 258 10.4
CONCLUSIONS 260
REFERENCES 261
11 RECURSIVE CODE SCALES FOR MOVING CONVERTERS 263
11.1 PSEUDO-RANDOM CODE SCALES 263
11.1.1 PSEUDO-RANDOM CODE SCALES FOR CONVERTERS OF ANGULAR MOVINGS 263
11.1.2 PSEUDO-RANDOM CODE SCALES FOR CONVERTERS OF LINEAR MOVING 267
11.2 COMPOSITE CODE SCALES 269
11.2.1 COMPOSITE CODE SCALES FOR CONVERTERS OF ANGULAR MOVING 269
11.2.2 COMPOSITE CODE SCALES FOR CONVERTERS OF LINEAR MOVING. 272
11.3 PLACING OF READING ELEMENTS ON A RECURSIVE CODE SCALE 274 11.3.1
ALGORITHM OF PLACING OF READING ELEMENTS ON A RECURSIVE CODE SCALE 275
11.3.2 READING ELEMENTS LOCATION ON THE PSEUDO-RANDOM CODE SCALE WITH A
CONSTANT STEP 277
11.3.3 READING ELEMENTS LOCATIONS ON THE COMPOSITE CODE SCALE WITH A
CONSTANT STEP 280
11.4 CORRECTING POSSIBILITIES OF RECURSIVE CODE SCALES 283 11.5
CONCLUSIONS 286
REFERENCES 288
IMAGE 6
X CONTENTS
12 INFRASTRUCTURE INTELLECTUAL PROPERTY FOR SOC SIMULATION AND DIAGNOSIS
SERVICE 289
12.1 INFRASTRUCTURE IP 289
12.2 THE THEORETICAL FOUNDATIONS OF DEDUCTIVE FAULT ANALYSIS 293 12.3
DEDUCTIVE COMPONENTS SYNTHESIS FOR SOC FUNCTIONS 295 12.4 STRUCTURE
MODELS OF SIMULATOR PRIMITIVES 301
12.5 ALGEBRA-LOGICAL FAULT DIAGNOSIS METHOD 307
12.6 SIMULATION FOR DIAGNOSIS REFINEMENT 310
12.7 STRUCTURE-LOGICAL FAULT DIAGNOSIS METHOD 313
12.8 VECTOR-LOGICAL DIAGNOSIS METHOD BY THE FAULT DETECTION TABLE 316
12.9 ALGEBRA-LOGICAL MEMORY REPAIR METHOD 320
12.10 CONCLUSIONS 326
REFERENCES 328
13 EVOLUTIONARY TEST GENERATION METHODS FOR DIGITAL DEVICES 331 13.1
GENETIC ALGORITHMS AND THEIR MODIFICATIONS 331
13.1.1 PARENTS SELECTION 332
13.1.2 CROSSOVER OPERATORS 333
13.1.3 MUTATION 334
13.2 GENETIC TEST GENERATION ALGORITHM FOR DIGITAL CIRCUITS 335 13.2.1
TEST GENERATION GENETIC ALGORITHMS FOR COMBINATIONAL CIRCUITS 336
13.2.2 TEST GENERATION GENETIC ALGORITHMS FOR SEQUENTIAL CIRCUITS 339
13.2.3 PROBLEM-ORIENTED FITNESS FUNCTIONS FOR TEST GENERATION 342 13.2.4
GA TEST GENERATION IMPLEMENTATION 345
13.3 DISTRIBUTED TEST GENERATION METHODS 346
13.3.1 GA PARALLELIZATION 346
13.3.2 PARALLEL TEST GENERATION METHOD BASED ON THE "MASTER-SLAVE" MODEL
348
13.3.3 DISTRIBUTED FAULT SIMULATION 349
13.3.4 DISTRIBUTED TEST GENERATION BASED ON THE "MODEL OF ISLANDS" 351
13.3.5 IMPLEMENTATION AND EXPERIMENTAL INVESTIGATIONS OF DISTRIBUTED
GENETIC ALGORITHMS OF TEST GENERATION AND SIMULATION 352
13.6 HIERARCHICAL GA OF TEST GENERATION FOR HIGHLY SEQUENTIAL CIRCUITS
353
13.7 GENETIC PROGRAMMING IN TEST GENERATION OF MICROPROCESSOR SYSTEMS
357
13.8 CONCLUSIONS 361
REFERENCES 361
INDEX 363 |
| any_adam_object | 1 |
| author2 | Adamski, Marian |
| author2_role | edt |
| author2_variant | m a ma |
| author_facet | Adamski, Marian |
| building | Verbundindex |
| bvnumber | BV037345912 |
| classification_rvk | ZN 5600 |
| ctrlnum | (OCoLC)707101445 (DE-599)DNB1007904240 |
| dewey-full | 621.395 621.392 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 621.392 |
| dewey-search | 621.395 621.392 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00000nam a2200000 cb4500</leader><controlfield tag="001">BV037345912</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20110603</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">110418s2011 d||| |||| 00||| eng d</controlfield><datafield tag="015" ind1=" " ind2=" "><subfield code="a">10N44</subfield><subfield code="2">dnb</subfield></datafield><datafield tag="016" ind1="7" ind2=" "><subfield code="a">1007904240</subfield><subfield code="2">DE-101</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">3642175449</subfield><subfield code="9">3-642-17544-9</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9783642175442</subfield><subfield code="9">978-3-642-17544-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)707101445</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)DNB1007904240</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield><subfield code="a">DE-83</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.395</subfield><subfield code="2">22/ger</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.392</subfield><subfield code="2">22/ger</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 5600</subfield><subfield code="0">(DE-625)157468:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">621.3</subfield><subfield code="2">sdnb</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Design of digital systems and devices</subfield><subfield code="c">Marian Adamski ... (eds.)</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Berlin [u.a.]</subfield><subfield code="b">Springer</subfield><subfield code="c">2011</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XVII, 365 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Lecture notes in electrical engineering</subfield><subfield code="v">79</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Testen</subfield><subfield code="0">(DE-588)4367264-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">UML</subfield><subfield code="0">(DE-588)4469781-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Fehlersimulation</subfield><subfield code="0">(DE-588)4234819-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitaltechnik</subfield><subfield code="0">(DE-588)4012303-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Fehlererkennung</subfield><subfield code="0">(DE-588)4133764-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitales System</subfield><subfield code="0">(DE-588)4012300-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logiksynthese</subfield><subfield code="0">(DE-588)4348178-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Programmierbare logische Anordnung</subfield><subfield code="0">(DE-588)4076369-9</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitalschaltung</subfield><subfield code="0">(DE-588)4012295-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Fehlertoleranz</subfield><subfield code="0">(DE-588)4123192-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Systementwurf</subfield><subfield code="0">(DE-588)4261480-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)4143413-4</subfield><subfield code="a">Aufsatzsammlung</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Digitales System</subfield><subfield code="0">(DE-588)4012300-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Systementwurf</subfield><subfield code="0">(DE-588)4261480-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="3"><subfield code="a">UML</subfield><subfield code="0">(DE-588)4469781-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="4"><subfield code="a">Programmierbare logische Anordnung</subfield><subfield code="0">(DE-588)4076369-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Digitalschaltung</subfield><subfield code="0">(DE-588)4012295-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Logiksynthese</subfield><subfield code="0">(DE-588)4348178-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="2"><subfield code="a">Programmierbare logische Anordnung</subfield><subfield code="0">(DE-588)4076369-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Digitaltechnik</subfield><subfield code="0">(DE-588)4012303-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2="1"><subfield code="a">Testen</subfield><subfield code="0">(DE-588)4367264-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2="2"><subfield code="a">Fehlersimulation</subfield><subfield code="0">(DE-588)4234819-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2="3"><subfield code="a">Fehlererkennung</subfield><subfield code="0">(DE-588)4133764-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2="4"><subfield code="a">Fehlertoleranz</subfield><subfield code="0">(DE-588)4123192-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Adamski, Marian</subfield><subfield code="4">edt</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Online-Ausgabe</subfield><subfield code="z">978-3-642-17545-9</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Lecture notes in electrical engineering</subfield><subfield code="v">79</subfield><subfield code="w">(DE-604)BV022422356</subfield><subfield code="9">79</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="q">text/html</subfield><subfield code="u">http://deposit.dnb.de/cgi-bin/dokserv?id=3554082&prov=M&dok_var=1&dok_ext=htm</subfield><subfield code="3">Inhaltstext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">DNB Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=022499505&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-022499505</subfield></datafield></record></collection> |
| genre | (DE-588)4143413-4 Aufsatzsammlung gnd-content |
| genre_facet | Aufsatzsammlung |
| id | DE-604.BV037345912 |
| illustrated | Illustrated |
| indexdate | 2024-07-20T11:05:49Z |
| institution | BVB |
| isbn | 3642175449 9783642175442 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-022499505 |
| oclc_num | 707101445 |
| open_access_boolean | |
| owner | DE-634 DE-83 |
| owner_facet | DE-634 DE-83 |
| physical | XVII, 365 S. graph. Darst. |
| publishDate | 2011 |
| publishDateSearch | 2011 |
| publishDateSort | 2011 |
| publisher | Springer |
| record_format | marc |
| series | Lecture notes in electrical engineering |
| series2 | Lecture notes in electrical engineering |
| spelling | Design of digital systems and devices Marian Adamski ... (eds.) Berlin [u.a.] Springer 2011 XVII, 365 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Lecture notes in electrical engineering 79 Testen (DE-588)4367264-4 gnd rswk-swf UML (DE-588)4469781-8 gnd rswk-swf Fehlersimulation (DE-588)4234819-5 gnd rswk-swf Digitaltechnik (DE-588)4012303-0 gnd rswk-swf Fehlererkennung (DE-588)4133764-5 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf Digitales System (DE-588)4012300-5 gnd rswk-swf Logiksynthese (DE-588)4348178-4 gnd rswk-swf Programmierbare logische Anordnung (DE-588)4076369-9 gnd rswk-swf Digitalschaltung (DE-588)4012295-5 gnd rswk-swf Fehlertoleranz (DE-588)4123192-2 gnd rswk-swf Systementwurf (DE-588)4261480-6 gnd rswk-swf (DE-588)4143413-4 Aufsatzsammlung gnd-content Digitales System (DE-588)4012300-5 s Systementwurf (DE-588)4261480-6 s CAD (DE-588)4069794-0 s UML (DE-588)4469781-8 s Programmierbare logische Anordnung (DE-588)4076369-9 s DE-604 Digitalschaltung (DE-588)4012295-5 s Logiksynthese (DE-588)4348178-4 s Digitaltechnik (DE-588)4012303-0 s Testen (DE-588)4367264-4 s Fehlersimulation (DE-588)4234819-5 s Fehlererkennung (DE-588)4133764-5 s Fehlertoleranz (DE-588)4123192-2 s Adamski, Marian edt Erscheint auch als Online-Ausgabe 978-3-642-17545-9 Lecture notes in electrical engineering 79 (DE-604)BV022422356 79 text/html http://deposit.dnb.de/cgi-bin/dokserv?id=3554082&prov=M&dok_var=1&dok_ext=htm Inhaltstext DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=022499505&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Design of digital systems and devices Lecture notes in electrical engineering Testen (DE-588)4367264-4 gnd UML (DE-588)4469781-8 gnd Fehlersimulation (DE-588)4234819-5 gnd Digitaltechnik (DE-588)4012303-0 gnd Fehlererkennung (DE-588)4133764-5 gnd CAD (DE-588)4069794-0 gnd Digitales System (DE-588)4012300-5 gnd Logiksynthese (DE-588)4348178-4 gnd Programmierbare logische Anordnung (DE-588)4076369-9 gnd Digitalschaltung (DE-588)4012295-5 gnd Fehlertoleranz (DE-588)4123192-2 gnd Systementwurf (DE-588)4261480-6 gnd |
| subject_GND | (DE-588)4367264-4 (DE-588)4469781-8 (DE-588)4234819-5 (DE-588)4012303-0 (DE-588)4133764-5 (DE-588)4069794-0 (DE-588)4012300-5 (DE-588)4348178-4 (DE-588)4076369-9 (DE-588)4012295-5 (DE-588)4123192-2 (DE-588)4261480-6 (DE-588)4143413-4 |
| title | Design of digital systems and devices |
| title_auth | Design of digital systems and devices |
| title_exact_search | Design of digital systems and devices |
| title_full | Design of digital systems and devices Marian Adamski ... (eds.) |
| title_fullStr | Design of digital systems and devices Marian Adamski ... (eds.) |
| title_full_unstemmed | Design of digital systems and devices Marian Adamski ... (eds.) |
| title_short | Design of digital systems and devices |
| title_sort | design of digital systems and devices |
| topic | Testen (DE-588)4367264-4 gnd UML (DE-588)4469781-8 gnd Fehlersimulation (DE-588)4234819-5 gnd Digitaltechnik (DE-588)4012303-0 gnd Fehlererkennung (DE-588)4133764-5 gnd CAD (DE-588)4069794-0 gnd Digitales System (DE-588)4012300-5 gnd Logiksynthese (DE-588)4348178-4 gnd Programmierbare logische Anordnung (DE-588)4076369-9 gnd Digitalschaltung (DE-588)4012295-5 gnd Fehlertoleranz (DE-588)4123192-2 gnd Systementwurf (DE-588)4261480-6 gnd |
| topic_facet | Testen UML Fehlersimulation Digitaltechnik Fehlererkennung CAD Digitales System Logiksynthese Programmierbare logische Anordnung Digitalschaltung Fehlertoleranz Systementwurf Aufsatzsammlung |
| url | http://deposit.dnb.de/cgi-bin/dokserv?id=3554082&prov=M&dok_var=1&dok_ext=htm http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=022499505&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV022422356 |
| work_keys_str_mv | AT adamskimarian designofdigitalsystemsanddevices |