Verfügbarkeit: On-Chip Instrumentation

On-Chip Instrumentation: Design and Debug for Systems on Chip

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Bibliographische Detailangaben
Format:	Buch
Sprache:	English
Veröffentlicht:	Boston, MA Springer Science+Business Media, LLC 2011
Schlagworte:	Ingenieurwissenschaften Engineering Computer aided design Systems engineering
Online-Zugang:	Inhaltsverzeichnis
Beschreibung:	X, 244 S.
ISBN:	9781441975621

Internformat

MARC


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Datensatz im Suchindex

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adam_text	IMAGE 1 VII CONTENTS 1 INTRODUCTION ............................................................................................... 1 1.1 THE NEED FOR ON-CHIP DEBUG ............................................................ 1 1.2 INSTRUMENT- (*IN-SILICON) AND EDA- (PRESILICON) BASED VERIFI CATION 3 1.3 SOC DEBUG REQUIREMENTS .................................................................. 7 1.4 INSTRUMENTATION-BASED DEBUG INFRASTRUCTURE ..................................... 11 2 ON-CHIP INSTRUMENTATION COMPONENTS .................................................. 17 2.1 TRACE AND EVENT TRIGGERING ................................................................ 17 2.2 EXTERNAL INTERFACES FOR ON-CHIP INSTRUMENTATION .............................. 18 2.3 PERFORMANCE ANALYSIS USING ON-CHIP INSTRUMENTATION .................... 19 2.4 ON-CHIP LOGIC AND BUS ANALYSIS ...................................................... 20 2.5 ON-CHIP INSTRUMENTATION EXAMPLES .................................................. 22 2.5.1 TRACE MONITORING AND INTERFACES ........................................... 22 2.5.2 BUS LOGIC MONITORING ........................................................... 23 2.5.3 REAL-TIME DATA EXCHANGE ..................................................... 25 2.6 MULTIPROCESSOR DEBUG ....................................................................... 26 3 JTAG USE IN DEBUG ................................................................................... 31 3.1 JTAG PINS .......................................................................................... 32 3.2 TEST ACCESS PORT ................................................................................. 35 3.3 JTAG REGISTERS .................................................................................. 38 3.4 JTAG INSTRUCTIONS .............................................................................. 39 3.5 BOUNDARY-SCAN DESCRIPTION LANGUAGE .............................................. 40 3.6 THE ROAD TO JTAG: HISTORICAL DEBUG APPROACHES ............................ 44 3.6.1 BACKGROUND DEBUG MODE ...................................................... 47 4 PROCESSOR SYSTEM DEBUG ........................................................................... 49 4.1 A PROCESSOR DEBUG INSTRUMENT IMPLEMENTATION ................................ 52 4.2 PROCESSOR TRACE COMPRESSION ............................................................ 55 4.3 HUNTING CODE ERRORS WITH SELF-TRACE ................................................ 59 CLICK TO BUY NOW! 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CO M IMAGE 2 VIII CONTENTS 5 AN ON-CHIP DEBUG SYSTEM ...................................................................... 61 5.1 OCDS FEATURES .................................................................................. 62 5.1.1 DEBUG EVENTS ......................................................................... 64 5.1.2 DEBUG EVENT ACTIONS ............................................................. 64 5.1.3 DEBUG REGISTERS ..................................................................... 65 5.2 OPERATION MODES ................................................................................ 65 5.2.1 ENTERING COMMUNICATION MODE ............................................ 66 5.2.2 COMMUNICATION MODE INSTRUCTIONS ....................................... 66 5.2.3 MONITOR-TO-DEBUGGER HOST DATA TRANSFER (RECEIVE) ............. 67 5.2.4 DEBUGGER HOST-TO-MONITOR DATA TRANSFER (SEND) ................. 67 5.2.5 HIGH-LEVEL SYNCHRONIZATION .................................................. 67 5.3 OCDS REGISTERS ................................................................................. 68 5.3.1 DEBUG TASK ID REGISTER......................................................... 68 5.3.2 INSTRUCTION POINTER REGISTER ................................................... 68 5.3.3 HARDWARE TRIGGER COMPARISON REGISTERS .............................. 69 5.3.4 CONSIDERATIONS ON ACCESSING OCDS REGISTERS ..................... 69 5.4 OCDS JTAG ACCESS .......................................................................... 70 5.4.1 STEPS TO INITIALIZE THE JTAG MODULE ..................................... 72 5.5 OCDS MODULE ACCESS ....................................................................... 72 5.5.1 ERROR PROTECTION ..................................................................... 72 5.6 OCDS JTAG I/O INSTRUCTIONS ............................................................ 74 5.7 OCDS JTAG REGISTERS ....................................................................... 76 5.8 HARDWARE TRIGGERS ............................................................................. 77 5.8.1 STRUCTURE OF A NONINTERRUPTIBLE MONITOR ROUTINE .................. 79 5.8.2 STRUCTURE OF AN INTERRUPTIBLE MONITOR ROUTINE....................... 79 5.8.3 DEBUG EVENT CONTROL REGISTERS ............................................. 80 5.9 ADDITIONAL FEATURES ............................................................................ 81 5.9.1 SYSTEM SECURITY ..................................................................... 82 5.9.2 RESET FROM THE JTAG SIDE ..................................................... 83 5.9.3 RESET FROM THE CHIP/PROCESSOR SIDE ...................................... 83 6 BUS SYSTEM DEBUG ..................................................................................... 85 6.1 ON-CHIP BUSES ................................................................................... 85 6.2 SOCKET-BASED SOC DESIGN ................................................................. 87 6.2.1 SOC INTERCONNECT COMPLEXITIES ............................................. 87 6.3 BUS-LEVEL INTEGRATION ......................................................................... 90 6.3.1 BUS MASTER MONITORING.......................................................... 91 6.3.2 PERIPHERAL BUS MONITORING .................................................... 91 6.3.3 SLAVE MONITORING ................................................................... 91 6.4 INTERNAL AND EXTERNAL ALTERNATIVES FOR BUS TRACE............................... 92 6.5 PROGRAMMABLE BUS PERFORMANCE MONITORING .................................... 93 6.6 BUS PERFORMANCE MONITORING ............................................................. 94 6.7 ON-CHIP AND OFF-CHIP ANALYSIS ........................................................ 98 6.8 REQUEST RESPONSE TRACE BUS ANALYSIS .............................................. 101 6.8.1 RRT OPERATIONS ..................................................................... 103 6.8.2 RRT IMPLEMENTATION ............................................................. 104 CLICK TO BUY NOW! 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CO M IMAGE 3 IX CONTENTS 7 MULTIPROCESSOR DEBUGGING ....................................................................... 109 7.1 CROSS-TRIGGERING AND GLOBAL BREAKPOINT CONTROL ............................. 110 7.2 HYPERDEBUG DISTRIBUTED CROSS-TRIGGERING ....................................... 110 7.2.1 HYPERDEBUG CONTROLLER ......................................................... 112 7.2.2 TYPICAL HYPERDEBUG IMPLEMENTATION ................................... 113 7.3 MULTICORE SYNCHRONIZATION TRIGGERING AND GLOBAL ACTIONS .............. 115 8 IEEE 1149.7: CJTAG/AJTAG .................................................................... 117 8.1 TEST AND DEBUG VIEWS OF 1149.7 ....................................................... 118 8.2 KEY T0-T5 CLASS FUNCTIONS .............................................................. 120 8.3 MIPI USE OF 1149.7 ........................................................................... 129 8.3.1 MIPI SYSTEM TRACE MODULE .................................................. 130 8.4 NEXUS USE OF 1149.7 ......................................................................... 132 8.4.1 IEEE 1149.7/NEXUS INTEGRATION ............................................. 134 9 IEEE P1687 - IJTAG ................................................................................ 137 9.1 OVERLAP ZONES AND GATEWAY ELEMENTS .............................................. 139 9.2 CLASSES OF P1687 INSTRUMENTS ............................................................ 141 9.3 IEEE 1500 INSTRUMENTS ...................................................................... 143 10 OCP IP DEBUG INTERFACES ......................................................................... 145 10.1 OCP MULTICORE DEBUG ..................................................................... 146 10.2 OCP DEBUG FEATURES ........................................................................ 148 10.3 THREE VIEWS OF DEBUGGING .............................................................. 150 10.3.1 PURE SOFTWARE DEBUGGING................................................... 150 10.3.2 PURE HARDWARE DEBUGGING ................................................. 151 10.3.3 SYSTEM-ON-CHIP DEBUGGING ............................................... 151 10.4 DEBUG COMPONENTS AND IP INTERFACES .............................................. 151 10.5 DEBUG SOCKET DEFI NITIONS ................................................................ 152 10.5.1 CORE DEBUG SOCKET INTERFACES ............................................ 154 10.5.2 CROSS-TRIGGERING SOCKET INTERFACES .................................... 157 10.5.3 OCP SYNCHRONIZED RUN CONTROL ........................................ 163 10.5.4 OCP TRAFFI C-MONITORING AND TRACE INTERFACES ................... 163 10.5.5 PERFORMANCE MONITORING .................................................... 165 10.5.6 SYSTEM TIMESTAMPING ........................................................ 166 10.5.7 POWER MANAGEMENT MONITORING ......................................... 166 10.5.8 SECURITY DEBUG INTERFACE .................................................... 167 11 NEXUS IEEE 5001 ....................................................................................... 169 11.1 NEXUS IMPLEMENTATION CLASSES ........................................................ 171 11.2 NEXUS MESSAGE ARCHITECTURE ........................................................... 172 11.2.1 NEXUS TCODES .................................................................. 174 11.2.2 NEXUS REGISTERS .................................................................. 178 11.3 NEXUS INTERFACES ............................................................................ 180 11.3.1 NEXUS JTAG ACCESS ........................................................... 180 11.3.2 NEXUS AUX INTERFACES .................................................... 181 CLICK TO BUY NOW! P D FXC HANGE VIEWER W W W .DOCU-TRACK. CO MCLICK TO BUY NOW! P D FXC HANGE VIEWER W W W .DOCU-TRACK. CO M IMAGE 4 X CONTENTS 11.4 MULTICORE NEXUS DEBUG APPROACHES ............................................... 185 11.4.1 INPUT TOOL-TO-TARGET MESSAGES ........................................... 187 11.4.2 OUTPUT TARGET-TO-TOOL MESSAGES ........................................ 188 11.5 NEXUS PRODUCT IMPLEMENTATIONS ...................................................... 189 11.6 SUMMARY .......................................................................................... 193 12 MIPS EJTAG ............................................................................................. 195 12.1 EJTAG INSTRUCTIONS AND REGISTERS ................................................... 197 12.2 PC SAMPLING .................................................................................... 199 12.3 MIPS PDTRACE .............................................................................. 199 12.3.1 TRACE OUTPUT FORMATS ......................................................... 200 12.3.2 TRACE CONTROL BLOCK REGISTERS ............................................ 204 12.4 TCB TRIGGER LOGIC OVERVIEW .......................................................... 206 12.5 PDTRACE EXTERNAL INTERFACE ............................................................... 207 12.6 TCTRACE IF ........................................................................................ 209 12.7 PDTRACE OPERATIONS ..................................................................... 210 13 ARM ETM ................................................................................................. 213 13.1 ETM SIGNALS .................................................................................... 213 13.1.1 EXTERNAL SIGNALS .................................................................. 214 13.2 ETM9 REGISTERS ............................................................................... 216 13.3 TRACE INTERFACE ................................................................................. 218 14 INFI NEON MULTICORE DEBUG SOLUTION ............................................................ 219 14.1 MCDS TRACE PROTOCOL DEFI NITION .................................................... 221 14.1.1 DATA TRACE ........................................................................... 223 14.2 DEBUG TRANSACTOR: RUN CONTROL BUS MASTER .................................. 224 14.3 MCDS RUN CONTROL: ON-CHIP DEBUG SUPPORT ................................ 225 14.3.1 BCU LEVEL 1 (BUS-OBSERVER UNIT ON THE SYSTEM BUS) ...... 227 14.3.2 CONCURRENT DEBUGGING IN LEVEL 3 MCDS (TWO-CHANNEL TRACING) .......................................................... 228 14.3.3 DEBUG INTERFACE (CERBERUS) (DEBUG BUS-TRANSACTOR MODULE) ........................................... 228 14.4 RW MODE AND COMMUNICATION MODE ............................................. 228 14.5 MULTICORE BREAK SWITCH ................................................................... 229 15 EJTAG AND TRACE IN TOSHIBA TX CORES ................................................. 231 15.1 PROCESSOR ACCESS OVERVIEW ............................................................. 232 15.2 TOSHIBA EJTAG INSTRUCTIONS AND REGISTERS ...................................... 233 15.3 DEBUG EXCEPTIONS ............................................................................ 235 15.4 PROCESSOR DEBUG INSTRUCTIONS AND CP0 REGISTERS ............................ 235 15.5 BREAK FUNCTIONS ............................................................................... 237 15.6 OUTPUT BY PC TRACE .......................................................................... 238 INDEX ................................................................................................................. 241 CLICK TO BUY NOW! P D FXC HANGE VIEWER W W W .DOCU-TRACK. CO MCLICK TO BUY NOW! P D FXC HANGE VIEWER W W W .DOCU-TRACK. CO M
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spelling	On-Chip Instrumentation Design and Debug for Systems on Chip by Neal Stollon Boston, MA Springer Science+Business Media, LLC 2011 X, 244 S. txt rdacontent n rdamedia nc rdacarrier Ingenieurwissenschaften Engineering Computer aided design Systems engineering Stollon, Neal Sonstige oth SWB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=022486932&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	On-Chip Instrumentation Design and Debug for Systems on Chip Ingenieurwissenschaften Engineering Computer aided design Systems engineering
title	On-Chip Instrumentation Design and Debug for Systems on Chip
title_auth	On-Chip Instrumentation Design and Debug for Systems on Chip
title_exact_search	On-Chip Instrumentation Design and Debug for Systems on Chip
title_full	On-Chip Instrumentation Design and Debug for Systems on Chip by Neal Stollon
title_fullStr	On-Chip Instrumentation Design and Debug for Systems on Chip by Neal Stollon
title_full_unstemmed	On-Chip Instrumentation Design and Debug for Systems on Chip by Neal Stollon
title_short	On-Chip Instrumentation
title_sort	on chip instrumentation design and debug for systems on chip
title_sub	Design and Debug for Systems on Chip
topic	Ingenieurwissenschaften Engineering Computer aided design Systems engineering
topic_facet	Ingenieurwissenschaften Engineering Computer aided design Systems engineering
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=022486932&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
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