Reconfigurable computing: architectures, tools and applications: 7th international symposium, ARC 2011, Belfast, UK, March 23 - 25, 2011 ; proceedings
Gespeichert in:
| Format: | Tagungsbericht Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Berlin [u.a.]
Springer
2011
|
| Schriftenreihe: | Lecture notes in computer science
6578 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Literaturangaben |
| Beschreibung: | XIV, 398 S. Ill., graph. Darst. 24 cm |
| ISBN: | 9783642194740 |
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Datensatz im Suchindex
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IMAGE 1
TABLE OF CONTENTS
PLENARY TALKS
RECONFIGURABLE COMPUTING FOR HIGH PERFORMANCE NETWORKING APPLICATIONS 1
GORDON BREBNER
BIOLOGICALLY-INSPIRED MASSIVELY-PARALLEL ARCHITECTURES: A RECONFIGURABLE
NEURAL MODELLING PLATFORM 2
STEVE FURBER
RECONFIGURABLE ACCELERATORS I
A RECONFIGURABLE AUDIO BEAMFORMING MULTI-CORE PROCESSOR 3 DIMITRIS
THEODOROPOULOS, GEORGI KUZMANOV, AND GEORGI GAYDADJIEV
A REGULAR EXPRESSION MATCHING CIRCUIT BASED ON A DECOMPOSED AUTOMATON 16
HIROKI NAKAHARA, TSUTOMU SASAO, AND MUNEHIRO MATSUURA
DESIGN AND IMPLEMENTATION OF A MULTI-CORE CRYPTO-PROCESSOR FOR SOFTWARE
DEFINED RADIOS 29
MICHAEL GRAND, LILIAN BOSSUET, BERTRAND LE GAL, GUY GOGNIAT, AND
DOMINIQUE DALLET
DESIGN TOOLS
APPLICATION SPECIFIC MEMORY ACCESS, REUSE AND REORDERING FOR SDRAM 41
SAMUEL BAYLISS AND GEORGE A. CONSTANTINIDES
AUTOMATIC GENERATION OF FPGA-SPECIFIC PIPELINED ACCELERATORS 53
CHRISTOPHE ALIAS, BOGDAN PASCA, AND ALEXANDRA PLESCO
HLS TOOLS FOR F P G A: FASTER DEVELOPMENT WITH BETTER PERFORMANCE . . .
67 ALEXANDRE CORNU, STEVEN DERRIEN, AND DOMINIQUE LAVENIER
POSTERS 1
A (FAULT-TOLERANT) 2 SCHEDULER FOR REAL-TIME HW TASKS 79
XABIER ITURBE, KHALED BENKRID, TUGHRUL ARSLAN, MIKEL AZKARATE, AND
IMANOL MARTINEZ
BIBLIOGRAFISCHE INFORMATIONEN HTTP://D-NB.INFO/1009893092
DIGITALISIERT DURCH
IMAGE 2
XII TABLE OF CONTENTS
A COMPACT GAUSSIAN RANDOM NUMBER GENERATOR FOR SMALL WORD LENGTHS 88
SUBHASIS DAS AND SACHIN PATKAR
ACCURATE FLOATING POINT ARITHMETIC THROUGH HARDWARE ERROR-FREE
TRANSFORMATIONS 94
MANOUK V. MANOUKIAN AND GEORGE A. CONSTANTINIDES
ACTIVE STORAGE NETWORKS FOR ACCELERATING K-MEANS D A TA CLUSTERING . .
. 102 JANARDHAN SINGARAJU AND JOHN A. CHANDY
AN FPGA IMPLEMENTATION FOR TEXTURE ANALYSIS CONSIDERING THE REAL-TIME
REQUIREMENTS OF VISION-BASED SYSTEMS 110
MARIO-ALBERTO IBARRA-MANZANO AND DORA-LUZ ALMANZA-OJEDA
CREAMS: AN EMBEDDED MULTIPROCESSOR PLATFORM 118
MATEUS B. RUTZIG, ANTONIO CARLOS S. BECK, AND LUIGI CARRO
DATAFLOW GRAPH PARTITIONING FOR OPTIMAL SPATIO-TEMPORAL COMPUTATION ON A
COARSE GRAIN RECONFIGURABLE ARCHITECTURE 125 RATNA KRISHNAMOORTHY,
KESHAVAN VARADARAJAN, MASAHIRO FUJITA, MYTHRI ALLE, S.K. NANDY, AND
RANJANI NARAYAN
RECONFIGURABLE PROCESSORS
A PIPELINE INTERLEAVED HETEROGENEOUS SIMD SOFT PROCESSOR ARRAY
ARCHITECTURE FOR MIMO-OFDM DETECTION 133
XUEZHENG CHU, JOHN MCALLISTER, AND ROGER WOODS
DESIGN, IMPLEMENTATION, AND VERIFICATION OF AN ADAPTABLE PROCESSOR IN
LAVA HDL 145
STEFAN SCHULZE AND SERGEI SAWITZKI
TOWARDS AN ADAPTABLE MULTIPLE-ISA RECONFIGURABLE PROCESSOR 157 JAIR
FAJARDO JUNIOR, MATEUS B. RUTZIG, ANTONIO CARLOS S. BECK, AND LUIGI
CARRO
APPLICATIONS
FPGA-BASED CHERENKOV RING RECOGNITION IN NUCLEAR AND PARTICLE PHYSICS
EXPERIMENTS 169
MING LIU, ZHONGHAI LU, WOLFGANG KUEHN, AND AXEL JANTSCH
FPGA-BASED SMITH-WATERMAN ALGORITHM: ANALYSIS AND NOVEL DESIGN 181
YOSHIKI YAMAGUCHI, HUNG KUEN TSOI, AND WAYNE LUK
INDEX TO CONSTANT WEIGHT CODEWORD CONVERTER 193
JON T. BUTLER AND TSUTOMU SASAO
IMAGE 3
TABLE OF CONTENTS XIII
ON-CHIP EGO-MOTION ESTIMATION BASED ON OPTICAL FLOW 206 MAURIDO VANEGAS,
LEONARDO RUBIO, MATTEO TOMASI, JAVIER DIAZ, AND EDUARDO ROS
DEVICE ARCHITECTURE
COMPARISON BETWEEN HETEROGENEOUS MESH-BASED AND TREE-BASED APPLICATION
SPECIFIC FPGA 218
UMER FAROOQ, HUSAIN PARVEZ, ZIED MARRAKCHI, AND HABIB MEHREZ
DYNAMIC V D D SWITCHING TECHNIQUE AND MAPPING OPTIMIZATION IN
DYNAMICALLY RECONFIGURABLE PROCESSOR FOR EFFICIENT ENERGY REDUCTION.
230 TATSUYA YAMAMOTO, KAZUEI HIRONAKA, YUKI HAYAKAWA, MASAYUKI KIMURA,
HIDEHARU AMANO, AND KIMIYOSHI USAMI
MEMS INTERLEAVING READ OPERATION OF A HOLOGRAPHIC MEMORY FOR OPTICALLY
RECONFIGURABLE GATE ARRAYS 242
HIRONOBU MORITA AND MINORU WATANABE
POSTERS 2
FARM: FAST RECONFIGURATION MANAGER FOR REDUCING RECONFIGURATION TIME
OVERHEAD ON FPGA 253
FRANGOIS DUHEM, FABRICE MULLER, AND PHILIPPE LORENZINI
FEASIBILITY ANALYSIS OF RECONFIGURABLE COMPUTING IN LOW-POWER WIRELESS
SENSOR APPLICATIONS 261
ANDREAS ENGEL, BJOERN LIEBIG, AND ANDREAS KOCH
HIERARCHICAL OPTICAL FLOW ESTIMATION ARCHITECTURE USING COLOR CUES . .
269 FRANCISCO BARRANCO, MATTEO TOMASI, JAVIER DIAZ, AND EDUARDO ROS
MAGNETIC LOOK-UP TABLE (MLUT) FEATURING RADIATION HARDNESS, HIGH
PERFORMANCE AND LOW POWER 275
YAHYA LAKYS, WEISHENG ZHAO, JACQUES-OLIVIER KLEIN, AND CLAUDE CHAPPERT
RECONFIGURABLE STREAM-PROCESSING ARCHITECTURE FOR SPARSE LINEAR SOLVERS
281
KEVIN CUNNINGHAM AND PRAWAT NAGVAJARA
THE KRAWCZYK ALGORITHM: RIGOROUS BOUNDS FOR LINEAR EQUATION SOLUTION ON
AN FPGA 287
CHRISTOPHE LE LANN, DAVID BOLAND, AND GEORGE CONSTANTINIDES
A DYNAMIC RECONFIGURABLE CPLD ARCHITECTURE FOR STRUCTURED ASIC
TECHNOLOGY 296
TRAIAN TULBURE
IMAGE 4
XIV TABLE OF CONTENTS
RECONFIGURABLE ACCELERATORS II
FPGA ACCELERATED PARALLEL SPARSE MATRIX FACTORIZATION FOR CIRCUIT
SIMULATIONS 302
WEI WU, YI SHAN, XIAOMING CHEN, YU WANG, AND HUAZHONG YANG
FPGA OPTIMIZATIONS FOR A PIPELINED FLOATING-POINT EXPONENTIAL UNIT 316
NIKOLAOS ALACHIOTIS AND ALEXANDROS STAMATAKIS
NETSTAGE/DPR: A SELF-ADAPTABLE FPGA PLATFORM FOR APPLICATION-LEVEL
NETWORK SECURITY 328
SASCHA MUEHLBACH AND ANDREAS KOCH
METHODOLOGY AND SIMULATION
A CORRELATION POWER ANALYSIS ATTACK AGAINST TAETE PAIRING ON FPGA 340
WEIBO PAN AND WILLIAM P. MARNANE
FROM PLASMA TO BEEFARM: DESIGN EXPERIENCE OF AN FPGA-BASED MULTICORE
PROTOTYPE 350
NEHIR SONMEZ, ORIOL AREAS, GOKHAN SAYILAR, OSMAN S. UNSAL, ADRIAN
CRISTAL, IBRAHIM HUR, SATNAM SINGH, AND MATEO VALERO
SYSTEM ARCHITECTURE
ARCHITECTURAL SUPPORT FOR MULTITHREADING ON RECONFIGURABLE HARDWARE 363
PAVEL G. ZAYKOV AND GEORGI KUZMANOV
HIGH PERFORMANCE PROGRAMMABLE FPGA OVERLAY FOR DIGITAL SIGNAL PROCESSING
375
SEAMAS MCGETTRICK, KUNJAN PATEL, AND CHRIS BLEAKLEY
SECURE VIRTUALIZATION WITHIN A MULTI-PROCESSOR SOFT-CORE SYSTEM-ON-CHIP
ARCHITECTURE 385
ALEXANDER BIEDERMANN, MARC STOETTINGER, LIJING CHEN, AND SORIN A. HUSS
AUTHOR INDEX 397 |
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| spelling | Reconfigurable computing: architectures, tools and applications 7th international symposium, ARC 2011, Belfast, UK, March 23 - 25, 2011 ; proceedings Andreas Koch ... (eds.) Berlin [u.a.] Springer 2011 XIV, 398 S. Ill., graph. Darst. 24 cm txt rdacontent n rdamedia nc rdacarrier Lecture notes in computer science 6578 Literaturangaben Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Rekonfiguration (DE-588)4306238-6 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2011 Belfast gnd-content Rekonfiguration (DE-588)4306238-6 s Computerarchitektur (DE-588)4048717-9 s Field programmable gate array (DE-588)4347749-5 s DE-604 Koch, Andreas Sonstige oth ARC 7 2011 Belfast Sonstige (DE-588)16105023-2 oth Lecture notes in computer science 6578 (DE-604)BV000000607 6578 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=021205284&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Reconfigurable computing: architectures, tools and applications 7th international symposium, ARC 2011, Belfast, UK, March 23 - 25, 2011 ; proceedings Lecture notes in computer science Field programmable gate array (DE-588)4347749-5 gnd Computerarchitektur (DE-588)4048717-9 gnd Rekonfiguration (DE-588)4306238-6 gnd |
| subject_GND | (DE-588)4347749-5 (DE-588)4048717-9 (DE-588)4306238-6 (DE-588)1071861417 |
| title | Reconfigurable computing: architectures, tools and applications 7th international symposium, ARC 2011, Belfast, UK, March 23 - 25, 2011 ; proceedings |
| title_auth | Reconfigurable computing: architectures, tools and applications 7th international symposium, ARC 2011, Belfast, UK, March 23 - 25, 2011 ; proceedings |
| title_exact_search | Reconfigurable computing: architectures, tools and applications 7th international symposium, ARC 2011, Belfast, UK, March 23 - 25, 2011 ; proceedings |
| title_full | Reconfigurable computing: architectures, tools and applications 7th international symposium, ARC 2011, Belfast, UK, March 23 - 25, 2011 ; proceedings Andreas Koch ... (eds.) |
| title_fullStr | Reconfigurable computing: architectures, tools and applications 7th international symposium, ARC 2011, Belfast, UK, March 23 - 25, 2011 ; proceedings Andreas Koch ... (eds.) |
| title_full_unstemmed | Reconfigurable computing: architectures, tools and applications 7th international symposium, ARC 2011, Belfast, UK, March 23 - 25, 2011 ; proceedings Andreas Koch ... (eds.) |
| title_short | Reconfigurable computing: architectures, tools and applications |
| title_sort | reconfigurable computing architectures tools and applications 7th international symposium arc 2011 belfast uk march 23 25 2011 proceedings |
| title_sub | 7th international symposium, ARC 2011, Belfast, UK, March 23 - 25, 2011 ; proceedings |
| topic | Field programmable gate array (DE-588)4347749-5 gnd Computerarchitektur (DE-588)4048717-9 gnd Rekonfiguration (DE-588)4306238-6 gnd |
| topic_facet | Field programmable gate array Computerarchitektur Rekonfiguration Konferenzschrift 2011 Belfast |
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