Digital design of signal processing systems: a practical approach
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| 1. Verfasser: | |
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| Format: | Buch |
| Sprache: | English |
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Chichester
Wiley
2011
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| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XX, 586 S. Ill., graph. Darst. |
| ISBN: | 9780470741832 9780470974681 |
Internformat
MARC
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| 100 | 1 | |a Khan, Shoaib |d 1936-2005 |e Verfasser |0 (DE-588)142540781 |4 aut | |
| 245 | 1 | 0 | |a Digital design of signal processing systems |b a practical approach |c Shoab Ahmed Khan |
| 264 | 1 | |a Chichester |b Wiley |c 2011 | |
| 300 | |a XX, 586 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Signal processing |x Digital techniques | |
| 650 | 0 | 7 | |a Signalverarbeitung |0 (DE-588)4054947-1 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Signalverarbeitung |0 (DE-588)4054947-1 |D s |
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Datensatz im Suchindex
| DE-BY-862_location | 2000 |
|---|---|
| DE-BY-FWS_call_number | 2000/ZN 6040 K45 |
| DE-BY-FWS_katkey | 415437 |
| DE-BY-FWS_media_number | 083000504361 |
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| adam_text | Titel: Digital design of signal processing systems
Autor: Khan, Shoab
Jahr: 2011
Contents
Preface xv
Acknowledgments xix
Overview 1
1.1 Introduction 1
1.2 Fueling the Innovation: Moore s Law 3
1.3 Digital Systems 3
1.3.1 Principles 3
1.3.2 Multi-core Systems 6
1.3.3 NoC-based MPSoC 1
1.4 Examples of Digital Systems 8
1.4.1 Digital Receiver for a Voice Communication System 8
1.4.2 The Backplane of a Router 10
1.5 Components of the Digital Design Process 10
1.5.1 Design 10
1.5.2 Implementation 11
1.5.3 Verification 11
1.6 Competing Objectives in Digital Design 11
1.7 Synchronous Digital Hardware Systems 11
1.8 Design Strategies 12
1.8.1 Example of Design Partitioning 14
1.8.2 NoC-based SoC for Carrier-class VoIP Media Gateway 16
7.8.3 Design Flow Migration 18
References 19
Using a Hardware Description Language 21
2.1 Overview 21
2.2 About Verilog 22
2.2.7 History 22
2.2.2 What is Verilog? 22
2.3 System Design Row
2.4 Logic Synthesis
2.5 Using the Verilog HDL
2.5.7 Modules
2.5.2 Design Partitioning
2.5.3 Hierarchical Design
2.5.4 Logic Values
2.5.5 Data Types
2.5.6 Variable Declaration
2.5.7 Constants
2.6 Four Levels of Abstraction
2.6.7 Switch Level
2.6.2 Gate Level or Structural Modeling
2.6.3 Dataflow Level
2.6.4 Behavioral Level
2.6.5 Verilog Tasks
2.6.6 Verilog Functions
2.6.7 Signed Arithmetic
2.7 Verification in Hardware Design
2.7.7 Introduction to Verification
2.7.2 Approaches to Testing a Digital Design
2.7.3 Levels of Testing in the Development Cycle
2.7.4 Methods for Generating Test Cases
2.7.5 Transaction-level Modeling
2.8 Exampl e of a Verification Setup
2.9 SystemVerilog
2.9.7 Data Types
2.9.2 Module Instantiation and Port Listing
2.9.3 Constructs of the C/C+ + Type
2.9.4 for and do-while Loops
2.9.5 The always Procedural Block
2.9.6 The final Procedural Block
2.9.7 The unique and priority Case Statements
2.9.8 Nested Modules
2.9.9 Functions and Tasks
2.9.10 The Interface
2.9.11 Classes
2.9.12 Direct Programming Interface (DPI)
2.9.13 Assertion
2.9.14 Packages
2.9.15 Randomization
2.9.16 Coverage
Exercises
References
Contents
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Contents
System Design Flow and Fixed-point Arithmetic 81
3.1 Overview 81
3.2 System Design Flow 83
3.2.1 Principles 83
3.2.2 Example: Requirements and Specifications of a UHF Software-
defined Radio 85
3.2.3 Coding Guidelines for High-level Behavioral Description 86
3.2.4 Fixed-point versus Floating-point Hardware 88
3.3 Representation of Numbers 89
3.3.1 Types of Representation 89
3.3.2 Two s Complement Representation 89
3.3.3 Computing Two s Complement of a Signed Number 90
3.3.4 Scaling 91
3.4 Floating-point Format 92
3.4.1 Normalized and Denormalized Values 93
3.4.2 Floating-point Arithmetic Addition 95
3.4.3 Floating-point Multiplication 96
3.5 Qn.m Format for Fixed-point Arithmetic 96
3.5.7 Introducing Qn.m 96
3.5.2 Floating-point to Fixed-point Conversion of Numbers 97
3.5.3 Addition in Q Format 98
3.5.4 Multiplication in Q Format 98
3.5.5 Bit Growth in Fixed-point Arithmetic 101
3.5.6 Overflow and Saturation 102
3.5.7 Two s Complement Intermediate Overflow Property 103
3.5.8 Corner Cases 105
3.5.9 Code Conversion and Checking the Corner Case 106
3.5.10 Rounding the Product in Fixed-point Multiplication 107
3.5.11 MATLAB® Support for Fixed-point Arithmetic 110
3.5.12 SystemC Support for Fixed-point Arithmetic 111
3.6 Floating-point to Fixed-point Conversion 112
3.7 Block Floating-point Format 113
3.8 Forms of Digital Filter 115
3.8.1 Infinite Impulse Response Filter 115
3.8.2 Quantization of IIR Filter Coefficients 117
3.8.3 Coefficient Quantization Analysis of a Second-order Section 123
3.8.4 Folded FIR Filters 126
3.8.5 Coefficient Quantization of an FIR Filter 127
Exercises 128
References 132
Mapping on Fully Dedicated Architecture 133
4.1 Introduction 133
4.2 Discrete Real-time Systems 134
4.3 Synchronous Digital Hardware Systems 136
4.4 Kahn Process Networks 137
viii Contents
4.4.1 Introduction to KPN 137
4.4.2 KPN for Modeling Streaming Applications 139
4.4.3 Limitations of KPN 144
4.4.4 Modified KPN and MPSoC 144
4.4.5 Case Study: GMSK Communication Transmitter 145
4.5 Methods of Representing DSP Systems 148
4.5.7 Introduction 148
4.5.2 Block Diagram 149
4.5.3 Signal Flow Graph 151
4.5.4 Dataflow Graph or Data Dependency Graph 151
4.5.5 Self-timed Firing 156
4.5.6 Single-rate and Multi-rate SDFGs 156
4.5.7 Homogeneous SDFG 158
4.5.8 Cyclo-static DFG 158
4.5.9 Multi-dimensional Arrayed Dataflow Graphs 160
4.5.70 Control Flow Graphs 160
4.5.11 Finite State Machine 161
4.5.12 Transformations on a Dataflow Graph 162
4.5.13 Dataflow Interchange Format (DIF) Language 162
4.6 Performance Measures 162
4.6.7 Iteration Period 162
4.6.2 Sampling Period and Throughput 163
4.6.3 Latency 163
4.6.4 Power Dissipation 164
4.7 Fully Dedicated Architecture 164
4.7.7 The Design Space 164
4.7.2 Pipelining 165
4.7.3 Selecting Basic Building Blocks 167
4.7.4 Extending the Concept of One-to-One Mapping 168
4.8 DFG to HW Synthesis 168
4.8.1 Mapping a Multi-rate DFG in Hardware 169
4.8.2 Centralized Controller for DFG Realization 171
Exercises 173
References 181
5 Design Options for Basic Building Blocks 183
5.1 Introduction 183
5.2 Embedded Processors and Arithmetic Units in FPGAs 183
5.3 Instantiation of Embedded Blocks 186
5.3.7 Example of Optimized Mapping 190
5.3.2 Design Optimization for the Target Technology 192
5.4 Basic Building Blocks: Introduction 194
5.5 Adders 194
5.5.7 Overview 194
5.5.2 Half Adders and Full Adders 195
5.5.3 Ripple Carry Adder 196
Contents
5.5.4 Fast Adders 198
5.5.5 Carry Look-ahead Adder 198
5.5.6 Hybrid Ripple Carry and Carry Look-ahead Adder 203
5.5.7 Binary Carry Look-ahead Adder 203
5.5.8 Carry Skip Adder 209
5.5.9 Conditional Sum Adder 209
5.5.10 Carry Select Adder 215
5.5.77 Using Hybrid Adders 217
5.6 Barrel Shifter 217
5.7 Carry Save Adders and Compressors 221
5.7.7 Carry Save Adders 221
5.7.2 Compression Trees 221
5.7.3 Dot Notation 221
5.8 Parallel Multipliers 222
5.8.7 Introduction 222
5.8.2 Partial Product Generation 223
5.8.3 Partial Product Reduction 224
5.8.4 A Decomposed Multiplier 230
5.8.5 Optimized Compressors 231
5.8.6 Single-and Multiple-column Counters 232
5.9 Two s Complement Signed Multiplier 234
5.9.7 Basics 234
5.9.2 Sign Extension Elimination 235
5.9.3 String Property 237
5.9.4 Modified Booth Recoding Multiplier 238
5.9.5 Modified Booth Recoded Multiplier in RTL Verilog 240
5.10 Compression Trees for Multi-operand Addition 243
5.11 Algorithm Transformations for CSA 243
Exercises 247
References 251
Multiplier-less Multiplication by Constants 253
6.1 Introduction 253
6.2 Canonic Signed Digit Representation 254
6.3 Minimum Signed Digit Representation 255
6.4 Multiplication by a Constant in a Signal Processing Algorithm 255
6.5 Optimized DFG Transformation 256
6.6 Fully Dedicated Architecture for Direct-form FIR Filter 261
6.6.7 Introduction 261
6.6.2 Example: Five-coefficient Filter 262
6.6.3 Transposed Direct-form FIR Filter 269
6.6.4 Example: TDFArchitecture 272
6.6.5 Hybrid FIR Filter Structure 276
6.7 Complexity Reduction 277
6.7.1 Sub-graph Sharing 277
Contents
6.7.2 Common Sub-expression Elimination 279
6.7.3 Common Sub-expressions with Multiple Operands 283
6.8 Distributed Arithmetic 283
6.8.1 Basics 283
6.8.2 Example: FIR Filter Design 287
6.8.3 M-Parallel Sub-filter-based Design 291
6.8.4 DA Implementation without Look-up Tables 292
6.9 FFT Architecture using FIR Filter Structure 292
Exercises 297
References 299
Pipelining, Retiming, Look-ahead Transformation and
Polyphase Decomposition 301
7.1 Introduction 301
7.2 Pipelining and Retiming 302
7.2.7 Basics 302
7.2.2 Cut-set Retiming 303
7.2.3 Retiming using the Delay Transfer Theorem 304
7.2.4 Pipelining and Retiming in a Feedforward System 304
7.2.5 Re-pipelining: Pipelining using Feedforward Cut-set 304
7.2.6 Cut-set Retiming of a Direct-form FIR Filter 306
7.2.7 Pipelining using the Delay Transfer Theorem 309
7.2.8 Pipelining Optimized DFG 311
7.2.9 Pipelining Carry Propagate Adder 312
7.2.10 Retiming Support in Synthesis Tools 312
7.2.11 Mathematical Formulation of Retiming 312
7.2.72 Minimizing the Number of Registers and Critical Path Delay 314
7.2.13 Retiming with Shannon Decomposition 315
7.2.14 Peripheral Retiming 316
7.3 Digital Design of Feedback Systems 316
7.3.7 Definitions 316
7.3.2 Cut-set Retiming for a Feedback System 319
7.3.3 Shannon Decomposition to Reduce the 1PB 320
7.4 C-slow Retiming 320
7.4.7 Basics 320
7.4.2 C-Slow for Block Processing 323
7.4.3 C-Slow for FPGAs and Time-multiplexed
Reconfigurable Design 323
7.4.4 C-Slow for an Instruction Set Processor 324
7.5 Look-ahead Transformation for IIR filters 324
7.6 Look-ahead Transformation for Generalized IIR Filters 326
7.7 Polyphase Structure for Decimation and Interpolation Applications 327
7.8 IIR Filter for Decimation and Interpolation 329
Exercises 336
References 340
Contents
Unfolding and Folding of Architectures 343
8.1 Introduction 343
8.2 Unfolding 344
8.3 Sampling Rate Considerations 344
8.3.7 Nyquist Sampling Theorem and Design Options 344
8.3.2 Software-defined Radio Architecture and Band-pass Sampling 345
8.3.3 AID Converter Bandwidth and Band-pass Sampling 347
8.4 Unfolding Techniques 348
8.4.7 Loop Unrolling 348
8.4.2 Unfolding Transformation 349
8.4.3 Loop Unrolling for Mapping SW to HW 350
8.4.4 Unfolding to Maximize Use of a Compression Tree 352
8.4.5 Unfolding for Effective Use of FPGA Resources 353
8.4.6 Unfolding and Retiming in Feedback Designs 356
8.5 Folding Techniques 362
8.5.7 Definitions and the Folding Transformation 363
8.5.2 Folding Regular Structured DFGs 363
8.5.3 Folded Architectures for FFT Computation 366
8.5.4 Memory-based Folded FFT Processor 367
8.5.5 Systolic Folded Architecture 370
8.6 Mathematical Transformation for Folding 372
8.7 Algorithmic Transformation 376
Exercises 377
References 378
Designs based on Finite State Machines 381
9.1 Introduction 381
9.2 Examples of Time-shared Architecture Design 382
9.2.7 Bit-serial and Digit-serial Architectures 382
9.2.2 Sequential Architecture 383
9.3 Sequencing and Control 388
9.3.7 Finite State Machines 388
9.3.2 State Encoding: One-hot versus Binary Assignment 390
9.3.3 Mealy and Moore State Machine Designs 391
9.3.4 Mathematical Formulations 392
9.3.5 Coding Guidelines for Finite State Machines 392
9.3.6 SystemVerilog Support for FSM Coding 397
9.4 Algorithmic State Machine Representation 398
9.4.7 Basics 398
9.4.2 Example: Design of a Four-entry: FIFO 399
9.4.3 Example: Design of an Instruction Dispatcher 401
9.5 FSM Optimization for Low Power and Area 408
9.6 Designing for Testability 409
9.6.7 Methodology 409
9.6.2 Coverage Metrics for Design Validation 410
9.7 Methods for Reducing Power Dissipation 411
Contents
9.7.7 Switching Power 411
9.7.2 Clock Gating Technique 412
9.7.3 FSM Decomposition 413
Exercises 415
References 419
10 Micro-programmed State Machines 421
10.1 Introduction 421
10.2 Micro-programmed Controller 422
70.2.7 Basics All
10.2.2 Moore Micro-programmed State Machines 425
70.2.3 Example: UFO and FIFO 426
10.3 Counter-based State Machines 427
70.3.7 Basics 427
10.3.2 Loadable Counter-based State Machine 429
10.3.3 Counter-based FSM with Conditional Branching 430
10.3.4 Register-based Controllers 431
10.3.5 Register-based Machine with Parity Field 432
10.3.6 Example to Illustrate Complete Functionality 431
10.4 Subroutine Support 434
10.5 Nested Subroutine Support 435
10.6 Nested Loop Support 436
10.7 Examples 439
10.7.1 Design for Motion Estimation 439
10.7.2 Design of a Wavelet Processor 443
Exercises 446
References 451
11 Micro-programmed Adaptive Filtering Applications 453
11.1 Introduction 453
11.2 Adaptive Filter Configurations 453
11.2.1 System Identification 453
11.2.2 Inverse System Modeling 454
11.2.3 Acoustic Noise Cancellation 454
11.2.4 Linear Prediction 455
11.3 Adaptive Algorithms 455
77.3.7 Basics 455
77.3.2 Least Mean Square (LMS) Algorithm 456
77.3.3 Normalized LMS Algorithm 457
77.3.4 Block LMS 457
11.4 Channel Equalizer using NLMS 457
//.4.7 Theory 457
77.4.2 Example: NLMS Algorithm to Update Coefficients 458
11.5 Echo Canceller 463
11.5.1 Acoustic Echo Canceller 463
11.5.2 Line Echo Cancellation (LEC) 464
Contents
11.6 Adaptive Algorithms with Micro-programmed State Machines 464
77.6.7 Basics 464
11.6.2 Example: LEC Micro-coded Accelerator 465
11.6.3 Address Registers Arithmetic 47 4
11.6.4 Pipelining Options 478
11.6.5 Optional Support for Coefficient Update 479
77.6.6 Multi MAC Block Design Option 480
11.6.7 Compression Tree and Single CPA-based Design 480
Exercises 481
References 482
12 CORDIC-based DDFS Architectures 483
12.1 Introduction 483
12.2 Direct Digital Frequency Synthesizer 484
12.3 Design of a Basic DDFS 485
12.4 The CORDIC Algorithm 486
72.4.7 Introduction 486
12.4.2 CORDIC Algorithm for Hardware Implementation 489
12.4.3 Hardware Mapping 492
12.4.4 Time-shared Architecture 498
12.4.5 C-slowed Time-shared Architecture 501
72.4.6 Modified CORDIC Algorithm 502
12.4.7 Recoding of Binary Representation as ±7 502
12.5 Hardware Mapping of Modified CORDIC Algorithm 506
12.5.1 Introduction 506
12.5.2 Hardware Optimization 510
72.5.3 Novel Optimal Hardware Design 514
Exercises 519
References 520
13 Digital Design of Communication Systems 521
13.1 Introduction 521
13.2 Top-level Design Options 522
73.2.7 Bus-based Design 522
73.2.2 Point-to-Point Design 523
73.2.3 Nework-based Design 523
73.2.4 Hybrid Connectivity 524
73.2.5 Point-to-Point KPN-based Top-level Design 524
13.2.6 KPN with Shared Bus and DMA Controller 524
13.2.7 Network-on-Chip Top-level Design 527
73.2.8 Design of a Router for NoC 532
13.2.9 Run-time Reconfiguration 534
73.2.70 NoC for Software-defined Radio 535
13.3 Typical Digital Communication System 536
73.3.7 Source Encoding 536
13.3.2 Data Compression 536
Contents
73.3.3
73.3.4
73.3.5
13.3.6
13.3.7
13.3.8
Exercises
References
Encryption
Channel Coding
Framing
Modulation
Digital Up-conversion and Mixing
Front End of the Receiver
541
559
561
562
572
573
574
577
Index
579
|
| any_adam_object | 1 |
| author | Khan, Shoaib 1936-2005 |
| author_GND | (DE-588)142540781 |
| author_facet | Khan, Shoaib 1936-2005 |
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| author_sort | Khan, Shoaib 1936-2005 |
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| bvnumber | BV037274865 |
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| callnumber-subject | TK - Electrical and Nuclear Engineering |
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| classification_tum | ELT 517f |
| ctrlnum | (OCoLC)711859199 (DE-599)BVBBV037274865 |
| dewey-full | 621.382/2 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.382/2 |
| dewey-search | 621.382/2 |
| dewey-sort | 3621.382 12 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV037274865 |
| illustrated | Illustrated |
| indexdate | 2024-08-01T11:17:08Z |
| institution | BVB |
| isbn | 9780470741832 9780470974681 |
| language | English |
| lccn | 2010026285 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-021187765 |
| oclc_num | 711859199 |
| open_access_boolean | |
| owner | DE-29T DE-Aug4 DE-1050 DE-634 DE-862 DE-BY-FWS DE-91 DE-BY-TUM DE-83 |
| owner_facet | DE-29T DE-Aug4 DE-1050 DE-634 DE-862 DE-BY-FWS DE-91 DE-BY-TUM DE-83 |
| physical | XX, 586 S. Ill., graph. Darst. |
| publishDate | 2011 |
| publishDateSearch | 2011 |
| publishDateSort | 2011 |
| publisher | Wiley |
| record_format | marc |
| spellingShingle | Khan, Shoaib 1936-2005 Digital design of signal processing systems a practical approach Signal processing Digital techniques Signalverarbeitung (DE-588)4054947-1 gnd |
| subject_GND | (DE-588)4054947-1 |
| title | Digital design of signal processing systems a practical approach |
| title_auth | Digital design of signal processing systems a practical approach |
| title_exact_search | Digital design of signal processing systems a practical approach |
| title_full | Digital design of signal processing systems a practical approach Shoab Ahmed Khan |
| title_fullStr | Digital design of signal processing systems a practical approach Shoab Ahmed Khan |
| title_full_unstemmed | Digital design of signal processing systems a practical approach Shoab Ahmed Khan |
| title_short | Digital design of signal processing systems |
| title_sort | digital design of signal processing systems a practical approach |
| title_sub | a practical approach |
| topic | Signal processing Digital techniques Signalverarbeitung (DE-588)4054947-1 gnd |
| topic_facet | Signal processing Digital techniques Signalverarbeitung |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=021187765&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT khanshoaib digitaldesignofsignalprocessingsystemsapracticalapproach |
Inhaltsverzeichnis
Schweinfurt Zentralbibliothek Lesesaal
| Signatur: |
2000 ZN 6040 K45 |
|---|---|
| Exemplar 1 | ausleihbar Verfügbar Bestellen |