Introduction to digital electronics:
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Raleigh, NC
Scitech Publ.
2010
|
| Ausgabe: | Preliminary ed. |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | getr. Zählung graph. Darst. |
| ISBN: | 9781891121074 |
Internformat
MARC
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| 245 | 1 | 0 | |a Introduction to digital electronics |c by Charles Hawkins and Jaume Segura |
| 246 | 1 | 3 | |a Introduction to modern digital electronics |
| 250 | |a Preliminary ed. | ||
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Datensatz im Suchindex
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| adam_text | IMAGE 1
- TABLE OF CONTENTS -
CHAPTER 1. INTRODUCTION 1.1 INTRODUCTION 1.2 COMBINATIONAL LOGIC GATES
AND BOOLEAN ALGEBRA 1.3 BOOLEAN AND LOGIC GATE REDUCTION 1.4 SEQUENTIAL
CIRCUITS
1.5 VOLTAGE AND CURRENT LAWS
KIRCHHOFF S VOLTAGE LAW AND ANALYSIS BY INSPECTION
KIRCHHOFF S CURRENT LAW AND ANALYSIS BY INSPECTION
MIXING VOLTAGE AND CURRENT DIVIDER ANALYSIS BY INSPECTION
1.6 POWER LOSS IN RESISTORS 1.7 CAPACITANCE
CAPACITOR ENERGY AND POWER
CAPACITOR VOLTAGE DIVIDERS
CAPACITIVE POWER LOSS
1.8 INDUCTANCE 1.9 DIODE CIRCUITS
DIODE RESISTOR CIRCUITS
DIODE RESISTANCE
1.10 SUMMARY 1.11 EXERCISES
CHAPTER 2. SEMICONDUCTOR PHYSICS
2.1 INTRODUCTION METALS, INSULATORS, AND SEMICONDUCTORS
CARRIERS IN SEMICONDUCTORS: ELECTRONS AND HOLES
DETERMINING CARRIER POPULATION
2.2 INTRINSIC AND EXTRINSIC SEMICONDUCTORS RC-TYPE SEMICONDUCTORS
IMAGE 2
/?-TYPE SEMICONDUCTORS
2.3 CARRIER TRANSPORT IN SEMICONDUCTORS DRIFT CURRENT
DIFFUSION CURRENT
2.4 THE PN JUNCTION
2.5 BIASING THE/W JUNCTION: I-V CHARACTERISTICS THE PN JUNCTION UNDER
FORWARD BIAS
THE PN JUNCTION UNDER REVERSE BIAS
2.6 DIODE JUNCTION CAPACITANCE
2.7 SUMMARY
2.8 EXERCISES
CHAPTER 3 MOSFET TRANSISTORS
3.1 PRINCIPLES OF OPERATION THE MOSFET AS A DIGITAL SWITCH
PHYSICAL STRUCTURE OF MOSFETS
UNDERSTANDING MOS TRANSISTOR OPERATION: A DESCRIPTIVE APPROACH
MOSFET INPUT CHARACTERISTICS
NMOS TRANSISTOR OUTPUT CHARACTERISTICS
PMOS TRANSISTOR OUTPUT CHARACTERISTICS
3.2 THRESHOLD VOLTAGE IN MOS TRANSISTORS
3.5 SUMMARY
3.7 EXERCISES
CHAPTER 4 . INTERCONNECTIONS
4.1. INTRODUCTION
4.2. METAL INTERCONNECTS
4.3. RESISTIVE EFFECTS
RESISTANCE
THERMAL EFFECTS
VIA RESISTANCE
4.4. CAPACITANCE PARALLEL PLATE MODEL CAPACITIVE POWER LOSS
IMAGE 3
4.5. INDUCTANCE
INDUCTIVE VOLTAGE CHARGE AND DISCHARGE TIMING INDUCTIVE POWER LOSS
4.6. INTERCONNECT RC MODELS C MODEL FOR SHORT LINES RC MODEL FOR LONGER
LINES (ELMORE MODEL)
4.7. SUMMARY 4.8. EXERCISES
CHAPTER 5 THE CMOS INVERTER
5.1 INTRODUCTION
5.2 THE CMOS INVERTER
5.3 INVERTER STATIC OPERATION -VOLTAGE AND CURRENT TRANSFER CURVES
5.4 SYMMETRICAL TRANSFER CURVES
5.5 GRAPHICAL ANALYSIS OF TRANSFER CURVES
5.6 DYNAMIC OPERATION
5.7 INVERTER TRANSITION SPEED MODEL
5.8 INVERTER POWER ANALYSIS
5.9 SIZING AND INVERTER BUFFERS
5.10 POWER SUPPLY SCALING AND LOW POWER
5.11 TAPERED BUFFERS TO DRIVE LARGE LOADS
5.12 SUMMARY
5.13 EXERCISES
CHAPTER 6 NAND, NOR, AND TRANSMISSION GATES
6.1 INTRODUCTION
6.2 NAND GATES
6.3 NAND SIZING
6.4 NOR GATES
6.5 NOR SIZING
6.6 PASS GATES AND CMOS TRANSMISSION GATES
6.7 SUMMARY
6.8 EXERCISES
IMAGE 4
CHAPTER 7 CMOS DESIGN STYLES
7.1 INTRODUCTION
7.2 CMOS STATIC LOGIC
7.3 DYNAMIC CMOS LOGIC
7.4 DOMINO CMOS LOGIC
7.5 TRANSMISSION GATE LOGIC DESIGN
7.6 POWER AND ACTIVITY COEFFICIENTS
7.7 SUMMARY
7.8 EXERCISES
CHAPTER 8. SEQUENTIAL LOGIC GATE DESIGN AND TIMING
8.1 INTRODUCTION
8.2 THE CROSS-COUPLED INVERTER LATCH
8.3 THE GATED LATCH
8.4 EDGE-TRIGGERED STORAGE ELEMENT
SETUP AND HOLD TIMES CLOCK TO Q TIME
8.5 TIMING RULES FOR EDGE-TRIGGERED FLIP-FLOP
PERIOD CONSTRAINT HOLD TIME CONSTRAINT
8.7 CLOCK GENERATION CIRCUITS INTERCONNECT LINES PHASE LOCK LOOP (PLL)
SKEW AND JITTER
PERIOD CONSTRAINT HOLD TIME CONSTRAINT
8.8 OVERALL SYSTEM TIMING IN CHIP DESIGN
8.9 TIMING AND ENVIRONMENTAL NOISE
8.10 SUMMARY
8.11 EXERCISES
IMAGE 5
CHAPTER 9. MEMORY CIRCUITS
9.1 INTRODUCTION 9.2 MEMORY CIRCUIT ORGANIZATION 9.3 MEMORY CORE 9.4
MEMORY DECODERS
ROW DECODERS COLUMN DECODERS
9.5 MEMORY READ OPERATION TRANSISTOR SIZING RATIO DESIGN
9.6 MEMORY WRITE OPERATION CELL WRITE OPERATION COLUMN WRITE CIRCUITS
9.7 MEMORY READ OPERATION AND SENSE AMPLIFIER 9.8 DYNAMIC MEMORIES
(DRAMS) 9.9 SUMMARY 9.10 EXERCISES
CHAPTER 10. PROGRAMMABLE CHAPTER 10. PROGRAMMABLE LOGIC - FPGAS
10.1 FUNDAMENTALS OF PROGRAMMABLE LOGIC IMPLEMENTING BOOLEAN FUNCTIONS
BY PROGRAMMING INTERCONNECTS - THE PROGRAMMABLE SWITCH PROGRAMMABLE
LOGIC GATES
10.2 AND/OR MATRIX GATES - THE PLA EXTENDING THE PLA CAPABILITIES - THE
EXTENDED PLA
10.3 ADVANCED PROGRAMMABLE LOGIC CIRCUITS - THE FPGA INCORPORATING
SEQUENTIAL BLOCKS - THE COMPLEX PROGRAMMABLE LOGIC DEVICE (CPLD)
10.3.2 TIMING MODEL FOR CPLDS
10.4 FPGAS THE CONCEPT OF FPGAS COMMERCIAL ARCHITECTURES
10.5 UNDERSTANDING THE PROGRAMMABLE TECHNOLOGY FUSE/ANTIFUSE TECHNOLOGY
DOUBLE GATE TRANSISTOR SRAM-BASED FPGAS
IX
IMAGE 6
10.6 SUMMARY
10.7 EXERCISES
CHAPTER 11. INTEGRATED CIRCUIT LAYOUT (REQUEST COLOR FIGURES FROM WILEY)
11.1. INTRODUCTION
11.2. PHYSICAL DESIGN, CMOS DESIGN RULES
11.3. DESIGN RULES AND MINIMUM SPACING
11.4. LAYOUT APPROACH: BOOLEAN EQUATIONS, TRANSISTOR SCHEMATIC, AND
STICK DIAGRAMS
11.5. LAYING OUT A CIRCUIT WITH POWERPOINT
11.6. REVISITING THE DESIGN RULES OF THE/7-MOS TRANSISTOR LAYOUT
11.7. MULTI-INPUT LOGIC GATE LAYOUTS MERGING LOGIC GATE STANDARD CELL
LAYOUTS
11.8. MERGING LOGIC GATE STANDARD CELL LAYOUTS
11.9. LAYOUT COMPUTER AIDED DESIGN (CAD) TOOLS
11.10. MORE ON LAYOUT
11.11. SUMMARY
11.12. EXERCISES
CHAPTER 12. THE MANUFACTURING FABRICATION PROCESS
12.1 INTRODUCTION
12.2 IC FABRICATION OVERVIEW
12.3 WAFER CONSTRUCTION
12.4 FRONT AND BACK END OF LINE FABRICATION
12.5 FRONT END OF LINE (FOL) FAB TECHNIQUES PHOTOLITHOGRAPHY ETCHING
DEPOSITION CLEANING AND SAFETY OPERATIONS
12.6 BACK END OF LINE (BOL) FAB TECHNIQUES SPUTTERING DUAL DAMASCENE
INTERLEVEL DIELECTRIC AND FINAL PASSIVATION PACKAGING
12.7 FABRICATING A CMOS INVERTER ETCHING FRONT END OF LINE OPERATION
IMAGE 7
BACK END OF LINE OPERATION
PACKAGING
12.8 PHYSICAL AND CHEMICAL DEPOSITIONS EVAPORATION AND SPUTTERING
CHEMICAL VAPOR DEPOSITION (CVD)
12.9 METAL INTERCONNECT DAMASCENE PROCESS -FLAT LINES AND VIAS CONTACTS
12.10 A CMOS FABRICATION SEQUENCE
12.11 SLICING THE DIE
12.12 DIE PACKAGING
12.13 SUMMARY
12.14 EXERCISES
|
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | Preliminary ed. |
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| illustrated | Illustrated |
| indexdate | 2024-07-09T22:45:24Z |
| institution | BVB |
| isbn | 9781891121074 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-020590494 |
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| publishDate | 2010 |
| publishDateSearch | 2010 |
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| spelling | Hawkins, Charles Verfasser aut Introduction to digital electronics by Charles Hawkins and Jaume Segura Introduction to modern digital electronics Preliminary ed. Raleigh, NC Scitech Publ. 2010 getr. Zählung graph. Darst. txt rdacontent n rdamedia nc rdacarrier Digitalelektronik (DE-588)4260328-6 gnd rswk-swf Digitalelektronik (DE-588)4260328-6 s DE-604 Segura, Jaume Verfasser aut SWB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=020590494&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Hawkins, Charles Segura, Jaume Introduction to digital electronics Digitalelektronik (DE-588)4260328-6 gnd |
| subject_GND | (DE-588)4260328-6 |
| title | Introduction to digital electronics |
| title_alt | Introduction to modern digital electronics |
| title_auth | Introduction to digital electronics |
| title_exact_search | Introduction to digital electronics |
| title_full | Introduction to digital electronics by Charles Hawkins and Jaume Segura |
| title_fullStr | Introduction to digital electronics by Charles Hawkins and Jaume Segura |
| title_full_unstemmed | Introduction to digital electronics by Charles Hawkins and Jaume Segura |
| title_short | Introduction to digital electronics |
| title_sort | introduction to digital electronics |
| topic | Digitalelektronik (DE-588)4260328-6 gnd |
| topic_facet | Digitalelektronik |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=020590494&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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