VLSI in the nanometer era: proceedings of the 2003 ACM Great Lakes Symposium on VLSI, Radisson Barcelo Hotel, Washington, DC, USA, April 28 - 29. 2003
Gespeichert in:
| Körperschaft: | |
|---|---|
| Format: | Tagungsbericht Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY
ACM Press
2003
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Auf der Hauttitels. auch: GLSVLSI '03. - Literaturangaben |
| Beschreibung: | XII, 308 S. Ill., graph. Darst. |
| ISBN: | 1581136773 |
Internformat
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| 111 | 2 | |a Great Lakes Symposium on VLSI |n 13 |d 2003 |c Washington, DC |j Verfasser |0 (DE-588)10077778-8 |4 aut | |
| 245 | 1 | 0 | |a VLSI in the nanometer era |b proceedings of the 2003 ACM Great Lakes Symposium on VLSI, Radisson Barcelo Hotel, Washington, DC, USA, April 28 - 29. 2003 |c sponsored by SIGDA with technical support from IEEE ... |
| 264 | 1 | |a New York, NY |b ACM Press |c 2003 | |
| 300 | |a XII, 308 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
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| 650 | 0 | 7 | |a Nanotechnologie |0 (DE-588)4327470-5 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 2003 |z Washington DC |2 gnd-content | |
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| 710 | 2 | |a Association for Computing Machinery |b Special Interest Group on Design Automation |e Sonstige |0 (DE-588)10620-3 |4 oth | |
| 710 | 2 | |a Institute of Electrical and Electronics Engineers |e Sonstige |0 (DE-588)1692-5 |4 oth | |
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Datensatz im Suchindex
| _version_ | 1804143292447719424 |
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| adam_text | IMAGE 1
... FOREWORD
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111
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GLSVLSI 2004 CALL FOR PAPERS IV
SYMPOSIUM ORGANIZATION
.................................................................................................................
X
ADDITIONAL REVIEWERS
...........................................................................................................................
XII
WELCOME ADDRESS 8:30 - 8:45 AM
SESSION I : CAD 8:45 - 9:45 AM CHAIR: JAGAN NARASIMHAN
SL.1 CONSTRUCTING EXACT OCTAGONAL STEINER MINIMAL TREES (BEST PAPER
WINNER) ......... 1 C. S. COULSTON (PENN STATE ERIE, USA)
~ 1 . 2 S BOUNDING THE EFFORTS ON CONGESTION OPTIMIZATION FOR PHYSICAL
SYNTHESIS .................. 7 D. PANDINI (STMICROELECLRONICS, USA), L.
T. PILEGGI, A. J. STROJWAS (CARNEGIE MELLON UNIVERSIT): USA)
~ 1 . 3 S A COMPREHENSIVE HIGH-LEVEL SYNTHESIS SYSTEM FOR CONTROL-FLOW
INTENSIVE BEHAVIORS
.....................................................................................................................................
11
W. WANG, T. K. TAN, J. LUO, Y. FEI, L. SHANG, K. S. VALLERIO, L. ZHONG,
N. K. JHA (PRINCETON UNIVERSITY, USA), A. RAGHUNATHAN (NEC, USA)
SESSION 2: VLSL CIRCUITS 10:OO AM - 12:OO NOON CHAIR: TRAVIS BLALOCK
S2.1 ITERATIVE DECODING IN ANALOG CMOS
..................................................................................
15
S. HEMATI, A. 1-1. BANIHASHEMI (CARLETON UNIVERSITY, CANADA)
................. S2.2 DESIGN ISSUES IN LOW-VOLTAGE HIGH-SPEED
CURRENT-MODE LOGIC BUFFERS ...21 P. HEYDARI (UNIVERSITY OF CALIFORNIA.
USA)
S2.3 OPTIMUM WIRE SIZING OF RLC INTERCONNECT WITH REPEATERS
............................................ 27
M. A. EL-MOURSY, E. G. FRIEDMAN (UNIVERSITY OF ROCHESTER, USA)
~2.4S REDUCED DYNAMIC SWING DOMINO LOGIC .............. ..
....................................................... 33
R. MADER, I. KOURTEV (UNIVEWITY OF PIFTSBZRRGH, USA)
..... ~ 2 . 5 S A 5-20 GHZ, LOW POWER FPGA IMPLEMENTED BY SIGE HBT
BICMOS TECHNOLOGY 37 C. YOU, J.-R. GUO, R. P. KRAF?, K. ZHOU, M. CHU, J.
F. MCDONALD (RENSSEHER POLYTECLINIC INSTIT~RTE, USA)
............ ~ 2 . 6 S INTERCONNECTED RINGS AND OSCILLATORS AS GIGAHERTZ
CLOCK DISTRIBUTION NETS 41 M. S. MAZA, M. L. ARANDA (INAOE, MEXICO)
LUNCH 12:OO NOON - 1:15 PM
SESSION 3: NANOTECHNOLOGY 1 : I 5 - 2 3 5 PM CHAIR: AZEEZ BHAVNAGARWALA
................................... S3.1 INFORMATION STORAGE CAPACITY OF
CROSSBAR SWITCHING NETWORKS 45 P. P. SOTIRIADIS (JOHN HOPKINS
UNIVERSITY, USA)
............... S3.2 EXPLOITING MULTIPLE FUNCTIONALITY FOR NANO-SCALE
RECONFIGURABLE SYSTEMS 50 P. BECKETT (RMT UNIVERSITY, AUSTRALIA)
IMAGE 2
~ 3 . 3 S A 0.07 PM CMOS FLASH ANALOG-TO-DIGITAL CONVERTER FOR HIGH
SPEED AND LOW VOLTAGE APPLICATIONS
................................................................................................
56
J. YOO, K. CHOI, J. GHAZNAVI (PENNSJ~LVANIA SLATE UNIVERSITY, USA)
...................... ~ 3 . 4 S MODELING QCA FOR AREA MINIMIZATION IN
LOGIC SYNTHESIS .. .................... 60
N. GERGEL, S. CRAFT, J, LAC11 (UNIVERSITY OF VIRGINIA, USA)
POSTER SESSION I 2:35 - 4:00 PM CHAIR : ANKUR SRIVASTAVA
POWER-AWARE PIPELINED MULTIPLIER DESIGN BASED ON 2-DIMENTIONAL PIPELINE
GATING
..........................................................................................................................
64
J. DI, J. S. YUAN (UNIVERSITY OF CENTRD FLORIDA, USA)
.......... LOW POWER VLSL SEQUENTIAL CIRCUIT ARCHITECTURE USING CRITICAL
RACE CONTROL 68 M. LOWY, N. BUTLER, R. TINKLER (BAE SYSTEMS, USA)
A HYBRID ADIABATIC CONTENT ADDRESSABLE MEMORY FOR ULTRA LOW-POWER
APPLICATIONS ................... ..
.................................................................................
72
A. NATARAJAN, D. JASINSKI, W. BURLESON, R. TESSIER (UNIVERSITY OF
MASSACH~CSETTS, AMHERST, USA)
TEM-CELL AND SURFACE SCAN TO IDENTIFY THE ELECTROMAGNETIC EMISSION OF
INTEGRATED CIRCUITS ........... ..
............................................................................................
76
T. OSTERMANN (UNIVERSITY OF LINZ, AUSTRIA), B. DEUTSCHMANN
(AUSTR.IAMICROSYSTCMS AG, AZRSTRIA)
MUTATE: AN EFFICIENT DESIGN FOR TESTABILITY TECHNIQUE FOR MULTIPLEXOR
BASED CIRCUITS ....................... ..
................................................................ 80
R. DRECHSLER, J. SHI, CI. FEY (UNIVERSITY OF BREMEN, GERNLANY)
COOLING OF INTEGRATED CIRCUITS USING DROPLET-BASED MICROFLUIDICS
............................... 84 V. K. PAMULA, K. CHAKRABARTY (DUKE
UNIVERSITY, USA)
LANGUAGE EMPTINESS CHECKING USING MDGS
................................................................... 88
F. WANG, S. TAHAR (CONCORDIN UNIVERSITY, CUNADA)
A SYSTEM-LEVEL METHODOLOGY FOR FAST MULTI-OBJECTIVE DESIGN SPACE
EXPLORATION
...................................................................................................................
92
G. PALEMO, C. SILVANO, S. VALSECCHI, V. ZACCARIA (POLITECNICO DI MILANO,
ITALY)
A PRACTICAL CAD TECHNIQUE FOR REDUCING POWERLGROUND NOISE IN DSM
CIRCUITS ...... 96 A. MUKHERJEE, K. R. DUSETY, R. SANKARANARAYAN (THE
UNIVERSITY OFNORTH CAROLINA AT CHARLOTTE, USA)
RF CMOS CIRCUIT OPTIMIZING PROCEDURE AND SYNTHESIS TOOL
....................................... 100 C. RAJAGOPAL, K. SRIDHAR, A.
NUNEZ (SYRACUSE UNIVERSITY, USA)
.................................. .................... WIRELENGTH
REDUCTION BY USING DIAGONAL WIRE ... 104
C. CHIANG, Q. SU (SYNOPSYS, BZC., USA), C . 4 . CHIANG (SOOCHOW
UNIVERSITY, TAIWAN)
A FAST SIMULATION APPROACH FOR INDUCTIVE EFFECTS OF VLSL INTERCONNECTS
................ 108 X. QI, G. LEONHARDT, D. FLEES, X.-D. YANG, S. KIM,
S. MUELLER, H. MAU (SUN MICROSYSTEMS, INC. USA), L. T . PILEGGI
(CARNEGIE MELLON UNIVERSITY, USA)
BUFFER SIZING FOR MINIMUM ENERGY-DELAY PRODUCT BY USING
.............................................................................................
AN APPROXIMATING POLYNOMIAL 112
C. W. KANG, S . ABBASPOUR, M. PEDRAM (UNIVERSITY OFSOUTHERN CALFORNIA,
USA)
.................... FORCE: A FAST AND EASY-TO-IMPLEMENT
VARIABLE-ORDERING HEURISTIC 116 F, A. ALOUL, I. L. MARKOV, K. A.
SAKALLAH (UNIVERSITY OF MICHIGAN, USA)
ROUTING METHODOLOGY FOR MINIMIZING INTERCONNECT ENERGY DISSIPATION
................... 120 A. SAKAI, T. YAMADA, Y. MATSUSHITA (SANYO
ELECTRIC CO., LTD., JAPAN), H . YASUURA (KYZRSYU UNIVERSITY)
CIRCUIT DESIGN OF A WIDE TUNING RANGE CMOS VCO
.................................................. WITH AUTOMATIC
AMPLITUDE CONTROL ............................ .. 124
J. CHEN, B. SHI (TSINGHIRA UNIVERSIT)), CHINA)
IMAGE 3
P1.17 A DECOUPLING TECHNIQUE FOR CMOS STRONG-COUPLED STRUCTURES
.............................. 128 L. Y ANG, J. S. YUAN (UNIVER.SI/Y OJ
CENTRD FLORIC/~R, USA)
P1.18 A CUSTOM FPGAFOR THE SIMULATION OF GENE REGULATORY NETWORKS
............................ 132 I . TAGKOPOULOS, C. ZUKOWSKI, G.
CAVCLIER, D. ANASTASSIOU (COLUAZHICR UTLIVERSI~R., LISA)
SESSION 4: VLSL DESIGN 4:00 - 6:00 PM CHAIR: VIJAY NARAYANAN
S4.1 A NOVEL ARCHITECTURE FOR POWER MASKABLE ARITHMETIC UNITS
......................................... 136
L. BENINI (UNIVERSITIR DI BOLOGNRR). A. MACII, E. MACII (POLIRCCNICO DI
TORINO, ITALY), E . OMERBEGOVIC (BULLDAST S.R.L., ITOLJQ, M. PONCINO
(UNIIWSITC DI LTCWRITR, ITALY), F . PRO (BTRLLDASTS.R.1.. IRA&)
S4.2 3D DIRECT VERTICAL INTERCONNECT MICROPROCESSORS TEST VEHICLE
................................... 14 1
J. MAYCGA, 0. ERDOGAN, P. M. BELENIJIAN, K. ZHOU, J. F. MCDONALD, RUSSCL
P. KRAFT (RENS.SELAER POLYTEL-HIC BISLIHRTC., USA)
S4.3 ZERO OVERHEAD WATERMAKING TECHNIQUE FOR FPGA DESIGNS
........................................ 147
A. K. JAIN, 1,. YUAN, P. R. PARI, G. Q U (UNIVEMITY OJ H.ITRRYLTRR~~/,
USA)
~ 4 . 4 S MATRIX DATAPATH ARCHITECTURE FOR AN ITERATIVE 4X4 MLMO NOISE
WHITENING ALGOITHM
..............................................................................................................
153
G. KNAGGE (UNIVERSITY O F N E ~ ~ C U S T K , AI~STR(RLIOR), D .
GARRETT, S . VENKATCSAN, C. NICOL (LUCENT TECHRZOLOGIES. A~RSTRZRLIA)
~ 4 . 5 S SYSTEM LEVEL DESIGN OF REAL TIME FACE RECOGNITION ARCHITECTURE
BASED ON COMPOSITE PCA
.................................................................................................................
157
R. GOTTUMUKKAL, V. K. ASARI (OLD DOMINION UNIVERSITY)
~ 4 . 6 S DESIGN AND MODELING OF A 16-BIT 1 SMSPS SUCCESSIVE
APPROXIMATION ADC WITH NON-BINARY CAPACITOR ARRAY
.........................................................................................
161
J. CAN (CIRRZRS LOGIC, INC., USA), S . YAN, J. ABRAHAM (UNIVERSITY OF
TEXOS UT AZRSTIN, USA)
BANQUET 6:00 PRN
TUESDAY, APRIL 2GTH
SESSION 5: VLSL CIRCUITS 8:30 - 9:45 AM CHAIR: RUCHIR PURI
.............................. ............. S5.1 SHIELDING EFFECT OF
ON-CHIP INTERCONNECT INDUCTANCE .. 165
M. A. EL-MOURSY, E. G. FRIEDMAN (UNIVER.SITY OFROCHESTER; USA)
S5.2 A PIPELINED CLOCK-DELAY DOMINO CARRY-LOOKAHEAD ADDER
...................................... 171
B. A. SHINKRE, J. E. STINE (ILLINOI~ INSTITUTE OFTECHNOLO@, USA)
................ S5.3 A GLOBALLY ASYNCHRONOUS LOCALLY DYNAMIC SYSTEM FOR
ASLCS AND SOCS 176 A. CHATTOPADHYAY, Z. ZILIC (MCCILL UNIVERSITY USA)
~ 5 . 4 S 40 MHZ 0.25 P M CMOS EMBEDDED I T BIT-LINE DECOUPLED DRAM FIFO
...............................................................................................
FOR MIXED-SIGNAL APPLICATIONS 182
M. I. FULLCR, J. P. MABRY, J. A. ILOSSACK, T. N. BLALOCK (UNIVERSITY
OFVIRGINIA, USA)
SESSION 6: CAD 10:OO AM - 12:OO NOON CHAIR: RHETT DAVIS
............................ S6.1 DESIGN TOPOLOGY AWARE PHYSICAL METRICS
FOR PLACEMENT ANALYSIS 186 S. RAN~JI, N. R. DHANWADA (IBM
MICI.OELECTRONICS, USA)
S6.2 A NOVEL ULTRA-FAST HEURISTIC FOR VLSL CAD STEINER TREES
........................... .... ............... 192
B. KRISHNA (INTEL CORPORC& ON, USA). C . Y. R. CHEN (SYRDACUSE
UTIVERSITY, USA), N. K. SEHGAL ( H T E L CORPORATION, USA)
VII
IMAGE 4
S6.3 COMBINING WIRE SWAPPING AND SPACING FOR LOW-POWER DEEP-SUBMICRON
BUSES
..........................................................................................................
198
E. MACII (POLITECNICO DI TORINO, ITALY), M. PONCINO (UNIVERSITA DI
VEROLZA, ITALY), S . SALEMO (POLITECNICO DI TORINO, ITALY)
~ 6 . 4 ~ CLUSTERING BASED ACYCLIC MULTI-WAY PARTITIONING
...................................................... 203
E. S. H. WONG, E. F. Y. YOUNG (THE CHINE.SE UNIVERSITY OF H. K.), W . K.
MAK (UNIVE,SI!Y OF S. FLORIDA, USA)
~ 6 . 5 S SYNTHESIS OF CONTINUOUS-TIME FILTERS AND ANALOG T O DIGITAL
CONVERTERS ...................... BY INTEGRATED CONSTRAINT
TRANSFORMATION, FLOORPLANNING AND ROUTING 207 H. TANG, H. ZHANG, A.
DOBOLI (SUNY-STONY BROOK, USA) ...................... ~ 6 . 6 S
CONGESTION REDUCTION IN TRADITIONAL AND NEW ROUTING ARCHITECTURES 21 1
A. R. AGNIHOTRI, P. H. MADDEN (STATE UNIVERSITY OJNEW YORK NT
BINGHAMTON, USA)
LUNCH E 12:OO NOON - 1:15 PM
SESSION 7: LOW POWER 1 :I 5 - 2:15 PM CHAIR: GANG QU
S7.1 SIMULTANEOUS PEAK AND AVERAGE POWER MINIMIZATION
........................................................... DURING
DATAPATH SCHEDULING FOR DSP PROCESSORS 2 15
S. P. MOHANTY, N. RANGANATHAN, S. K. CHAPPIDI (UNIVERSITY OFSOZRTH
FLORIDA, USA)
~7.2S UNIFICATION OF BASIC RETIMING AND SUPPLY VOLTAGE SCALING TO
MINIMIZE DYNAMIC POWER CONSUMPTION FOR SYNCHRONOUS DIGITAL DESIGNS
................................ 221 N. CHABINI (PRINCETON UNIVEVSITY,
USA), E. M . ABOULHAMID (UNIVERSITD DE MONTRDAL, CANADA), I . CHABINI
(MASSACHUSETTS INSTITUTE OF TECHNOLOGY, USA),
Y . SAVARIA ( ~ C O L E POLYTECHNIPRE DE MONTLDNL, CANADA)
~7.3S BRANCH PREDICTION TECHNIQUES FOR LOW-POWER VLLW PROCESSORS
............................... 225 G. PALERMO (POLITECNICO DI MILANO,
ITALY, STMICROELECTRONIC~.~, ITALY), M . SAMI, C. SILVANO, V. ZACCARIA
(POLITECNICO DI MILANO, ITALY), R. ZAFALON (STMICL-OELECTRONICS, ITALY)
POSTER SESSION 2 2:15 - 3:30 PM CHAIR: MIRCEA STAN
P2.1 ORTHOGONAL CODE GENERATOR FOR 3G WIRELESS TRANSCEIVERS
.......................................... 229
8. D. ANDREEV, E. L. TITLEBAUM, E. G. FRIEDMAN (UNIVERSITY AFROCHESTER,
USA)
P2.2 54X54-BIT RADIX-4 MULTIPLIER BASED ON MODIFIED BOOTH ALGORITHM
............................... 233 K. CHO, J. PARK, J. HONG, G. CHOI
(SAMSUNG ELECTRONICS CO., KOWA)
P2.3 POWER-TIME FLEXIBLE ARCHITECTURE FOR G F ( ~ ~ ) ELLIPTIC CURVE
CRYPTOSYSTEM
..................................................................................................
COMPUTATION ....................... .. 237
A. A,-A. GUH~B, M. K. IBMHIM (KING FNHD UNIVERSITY OF PETROLEUM AND
MINERALS, SAUDI ARABIA)
P2.4 A NOVEL 32-BIT SCALABLE MULTIPLIER ARCHITECTURE
................................................................ 241
Y. KOLLA (SZRN MICROSJNEMS, INC. USA), Y.-B. KILN (NORTHEUSTERN
UNIVERSITY. USA), J. CARTER (UNIVERSITY OF UTAH, USA)
P2.5 HIGH THROUGHOUT OVERLAPPED MESSAGE PASSING FOR LOW DENSITY
...............................................................................
........................... PARITY CHECK CODES .. 245
Y. CLEN, K. K. PARHI (UNIVERSITY OF MINNESOTA, USA)
P2.6 EXPONENTIAL SPLIT ACCUMULATOR FOR HIGH-SPEED REDUCED AREA
................................................... LOW-POWER DIRECT
DIGITAL FREQUENCY SYNTHESIZERS 249
E. MERLO, K-H. BAEK, M. J. CHOE (ROCKWELL SCIENTIJC COMPANY, USA)
.......................................... P2.7 USING DYNAMIC DOMINO
CIRCUITS IN SELF-TIMED SYSTEMS 253
J.-L. YANG, E. BRUNVAND (UNIVERSITY OF UTAH, USA)
P2.8 DYNAMIC SINGLE-RAIL SELF-TIMED LOGIC STRUCTURES FOR POWER EFFICIENT
SYNCHRONOUS PIPELINED DESIGNS
................................................................... 257
F. GRASSERT, D. TIINMEIMANN (UNIVERSITY OF ROSTOCK, GENNANY)
...
V L L L
IMAGE 5
P2.G COMPARISON OF NOISE TOLERANT PRECHARGE (NTP) TO CONVENTIONAL
................................................................................
FEEDBACK KEEPERS FOR DYNAMIC LOGIC 261
D. HARRIS, G. BREED, M. ERLER, D. DIAZ (HARVEY M~,DD CONEGE, USA)
.......................................................... P2.10
VARIABLE GAIN AMPLIFIER WITH OFFSET CANCELLATION 265
A. EMIRA, E. SINCHEZ-SINENCIO (TEXAS A&M UNIVERSITY, USA)
~ 2 . 1 1 REPEATER AND CURRENT-SENSING HYBRID CIRCUITS FOR ON-CHIP
INTERCONNECTS .............. 269 A. MAHESHWARI, W. BUSLCSON (UNIVEISITY
OF MASSACHZ/SETTS, AMHERST, USA)
~ 2 . 1 2 A SLEW RATE ENHANCEMENT TECHNIQUE FOR OPERATIONAL AMPLIFIERS
BASED O N A TUNABLE ACTIVE G,-BASED
CAPACITANCE MULTIPLICATION CIRCUIT ................ 273
R. SURYANARAYAN, A. GUPTA, T. N. BLALOCK (UNIVERSITY OF VIRGINIA, USA)
P2.13 A DUAL BAND CMOS VCO WITH A BALANCED DUTY CYCLE BUFFER
................................... 277
Y. C. HAN (SAMSZMG ELECTRONICS CO., KOREA), K. KIM, J . KIM, K. S. YOON,
J. CHEN, B. SHI (INHU UNIVERSITY, KOREA)
P2.14 NEW APPROACH T O CMOS CURRENT REFERENCE WITH VERY LOW TEMPERATURE
COEFFICIENT
........................................................................................................
28 1
J . CHEN, B. SHI (TSINGHZMU UNIVETDSI4~, CHINA)
~ 2 . 1 5 NOISE TOLERANT LOW VOLTAGE XOR-XNOR FOR FAST ARITHMETIC
............. .. ................... 285 M. ELGAMEL, S. GOEL, M. BAYOUMI
(UNIVERSIV OF LOZRISIANA AT LAFIIYETTE, USA)
SESSION 8: TESTING * 3:30 - 4:45 PM CHAIR: JOHN LACH
S8.1 ON AUTOMATIC GENERATION OF RTL VALIDATION TEST BENCHES USING
CIRCUIT TESTING TECHNIQUES
.....................................................................................
289
1. GHOSH (FULILSZM LOBORATORIES OF ANLERICA, USA), S. RAVI (NEC
LABORATORIES OF AMERICA, USA)
............. ~ 8 . 2 S A HIGHLY REGULAR MULTI-PHASE RESEEDING TECHNIQUE
FOR SCAN-BASED BET 295 E. KALLIGEROS, X. KAVOUSIANOS (UNIVERSITY OF
PATRAS, GREECE), D. NIKOLOS (COMPUTER TC~CHNOLOGY IRRSTILUTE, GREECE)
~ 8 . 3 S COEFFICIENT-BASED PARAMETRIC FAULTS DETECTION IN ANALOG
CIRCUITS ........................... 299 Z. GUO (NEW JCRSCY INSTIFZITE
QF TECHNOLOGY, USA)
~ 8 . 4 S MIXING ATPG AND PROPERTY CHECKING FOR TESTING HWLSW INTERFACES
...................... 303 A. FIN, F. FUMMI, G. PRAVADELLI (UNIVERSITY
OF VERONA, RALY)
CLOSING REMARKS * 4:45 - 5:00 PM
AUTHOR INDEX
.......................................................................................................................................
307
|
| any_adam_object | 1 |
| author_corporate | Great Lakes Symposium on VLSI Washington, DC |
| author_corporate_role | aut |
| author_facet | Great Lakes Symposium on VLSI Washington, DC |
| author_sort | Great Lakes Symposium on VLSI Washington, DC |
| building | Verbundindex |
| bvnumber | BV036668968 |
| classification_tum | TEC 030f ELT 355f |
| ctrlnum | (OCoLC)249432563 (DE-599)GBV368877868 |
| discipline | Technik Elektrotechnik |
| format | Conference Proceeding Book |
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| genre | (DE-588)1071861417 Konferenzschrift 2003 Washington DC gnd-content |
| genre_facet | Konferenzschrift 2003 Washington DC |
| id | DE-604.BV036668968 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T22:45:21Z |
| institution | BVB |
| institution_GND | (DE-588)10077778-8 (DE-588)10620-3 (DE-588)1692-5 |
| isbn | 1581136773 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-020588094 |
| oclc_num | 249432563 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | XII, 308 S. Ill., graph. Darst. |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | ACM Press |
| record_format | marc |
| spelling | Great Lakes Symposium on VLSI 13 2003 Washington, DC Verfasser (DE-588)10077778-8 aut VLSI in the nanometer era proceedings of the 2003 ACM Great Lakes Symposium on VLSI, Radisson Barcelo Hotel, Washington, DC, USA, April 28 - 29. 2003 sponsored by SIGDA with technical support from IEEE ... New York, NY ACM Press 2003 XII, 308 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Auf der Hauttitels. auch: GLSVLSI '03. - Literaturangaben VLSI (DE-588)4117388-0 gnd rswk-swf Nanotechnologie (DE-588)4327470-5 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2003 Washington DC gnd-content VLSI (DE-588)4117388-0 s Nanotechnologie (DE-588)4327470-5 s DE-604 Association for Computing Machinery Special Interest Group on Design Automation Sonstige (DE-588)10620-3 oth Institute of Electrical and Electronics Engineers Sonstige (DE-588)1692-5 oth OEBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=020588094&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | VLSI in the nanometer era proceedings of the 2003 ACM Great Lakes Symposium on VLSI, Radisson Barcelo Hotel, Washington, DC, USA, April 28 - 29. 2003 VLSI (DE-588)4117388-0 gnd Nanotechnologie (DE-588)4327470-5 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4327470-5 (DE-588)1071861417 |
| title | VLSI in the nanometer era proceedings of the 2003 ACM Great Lakes Symposium on VLSI, Radisson Barcelo Hotel, Washington, DC, USA, April 28 - 29. 2003 |
| title_auth | VLSI in the nanometer era proceedings of the 2003 ACM Great Lakes Symposium on VLSI, Radisson Barcelo Hotel, Washington, DC, USA, April 28 - 29. 2003 |
| title_exact_search | VLSI in the nanometer era proceedings of the 2003 ACM Great Lakes Symposium on VLSI, Radisson Barcelo Hotel, Washington, DC, USA, April 28 - 29. 2003 |
| title_full | VLSI in the nanometer era proceedings of the 2003 ACM Great Lakes Symposium on VLSI, Radisson Barcelo Hotel, Washington, DC, USA, April 28 - 29. 2003 sponsored by SIGDA with technical support from IEEE ... |
| title_fullStr | VLSI in the nanometer era proceedings of the 2003 ACM Great Lakes Symposium on VLSI, Radisson Barcelo Hotel, Washington, DC, USA, April 28 - 29. 2003 sponsored by SIGDA with technical support from IEEE ... |
| title_full_unstemmed | VLSI in the nanometer era proceedings of the 2003 ACM Great Lakes Symposium on VLSI, Radisson Barcelo Hotel, Washington, DC, USA, April 28 - 29. 2003 sponsored by SIGDA with technical support from IEEE ... |
| title_short | VLSI in the nanometer era |
| title_sort | vlsi in the nanometer era proceedings of the 2003 acm great lakes symposium on vlsi radisson barcelo hotel washington dc usa april 28 29 2003 |
| title_sub | proceedings of the 2003 ACM Great Lakes Symposium on VLSI, Radisson Barcelo Hotel, Washington, DC, USA, April 28 - 29. 2003 |
| topic | VLSI (DE-588)4117388-0 gnd Nanotechnologie (DE-588)4327470-5 gnd |
| topic_facet | VLSI Nanotechnologie Konferenzschrift 2003 Washington DC |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=020588094&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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