Digital system design with SystemVerilog:
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Upper Saddle River, NJ [u.a.]
Addison-Wesley
2010
|
| Series: | Prentice Hall modern semiconductor design series
|
| Subjects: | |
| Item Description: | Includes bibliographical references and index |
| Physical Description: | XXIX, 367 S. Ill. 24 cm |
| ISBN: | 9780137045792 0137045794 |
Staff View
MARC
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| 264 | 1 | |a Upper Saddle River, NJ [u.a.] |b Addison-Wesley |c 2010 | |
| 300 | |a XXIX, 367 S. |b Ill. |c 24 cm | ||
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| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 650 | 4 | |a Electronic digital computers |x Design and construction | |
| 650 | 4 | |a Computer simulation | |
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| author | Zwoliński, Mark |
| author_facet | Zwoliński, Mark |
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| author_sort | Zwoliński, Mark |
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| dewey-search | 621.390285/53 |
| dewey-sort | 3621.390285 253 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV036617001 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T22:44:16Z |
| institution | BVB |
| isbn | 9780137045792 0137045794 |
| language | English |
| lccn | 2009034771 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-020537116 |
| oclc_num | 705736224 |
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| owner | DE-92 |
| owner_facet | DE-92 |
| physical | XXIX, 367 S. Ill. 24 cm |
| publishDate | 2010 |
| publishDateSearch | 2010 |
| publishDateSort | 2010 |
| publisher | Addison-Wesley |
| record_format | marc |
| series2 | Prentice Hall modern semiconductor design series |
| spelling | Zwoliński, Mark Verfasser aut Digital system design with SystemVerilog Mark Zwolinski Upper Saddle River, NJ [u.a.] Addison-Wesley 2010 XXIX, 367 S. Ill. 24 cm txt rdacontent n rdamedia nc rdacarrier Prentice Hall modern semiconductor design series Includes bibliographical references and index Verilog (Computer hardware description language) Electronic digital computers Design and construction Computer simulation VERILOG (DE-588)4268385-3 gnd rswk-swf VERILOG (DE-588)4268385-3 s DE-604 |
| spellingShingle | Zwoliński, Mark Digital system design with SystemVerilog Verilog (Computer hardware description language) Electronic digital computers Design and construction Computer simulation VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4268385-3 |
| title | Digital system design with SystemVerilog |
| title_auth | Digital system design with SystemVerilog |
| title_exact_search | Digital system design with SystemVerilog |
| title_full | Digital system design with SystemVerilog Mark Zwolinski |
| title_fullStr | Digital system design with SystemVerilog Mark Zwolinski |
| title_full_unstemmed | Digital system design with SystemVerilog Mark Zwolinski |
| title_short | Digital system design with SystemVerilog |
| title_sort | digital system design with systemverilog |
| topic | Verilog (Computer hardware description language) Electronic digital computers Design and construction Computer simulation VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Verilog (Computer hardware description language) Electronic digital computers Design and construction Computer simulation VERILOG |
| work_keys_str_mv | AT zwolinskimark digitalsystemdesignwithsystemverilog |