Digital system design with SystemVerilog:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Upper Saddle River, NJ [u.a.]
Addison-Wesley
2010
|
| Schriftenreihe: | Prentice Hall modern semiconductor design series
|
| Schlagworte: | |
| Beschreibung: | Includes bibliographical references and index |
| Beschreibung: | XXIX, 367 S. Ill. 24 cm |
| ISBN: | 9780137045792 0137045794 |
Internformat
MARC
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| 008 | 100816s2010 xxua||| |||| 00||| eng d | ||
| 010 | |a 2009034771 | ||
| 020 | |a 9780137045792 |9 978-0-13-704579-2 | ||
| 020 | |a 0137045794 |c hardback : alk. paper |9 0-13-704579-4 | ||
| 035 | |a (OCoLC)705736224 | ||
| 035 | |a (DE-599)BVBBV036617001 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 044 | |a xxu |c US | ||
| 049 | |a DE-92 | ||
| 050 | 0 | |a TK7885.7 | |
| 082 | 0 | |a 621.390285/53 | |
| 084 | |a ZN 4030 |0 (DE-625)157339: |2 rvk | ||
| 100 | 1 | |a Zwoliński, Mark |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Digital system design with SystemVerilog |c Mark Zwolinski |
| 264 | 1 | |a Upper Saddle River, NJ [u.a.] |b Addison-Wesley |c 2010 | |
| 300 | |a XXIX, 367 S. |b Ill. |c 24 cm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Prentice Hall modern semiconductor design series | |
| 500 | |a Includes bibliographical references and index | ||
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 650 | 4 | |a Electronic digital computers |x Design and construction | |
| 650 | 4 | |a Computer simulation | |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 0 | |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-020537116 | ||
Datensatz im Suchindex
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|---|---|
| any_adam_object | |
| author | Zwoliński, Mark |
| author_facet | Zwoliński, Mark |
| author_role | aut |
| author_sort | Zwoliński, Mark |
| author_variant | m z mz |
| building | Verbundindex |
| bvnumber | BV036617001 |
| callnumber-first | T - Technology |
| callnumber-label | TK7885 |
| callnumber-raw | TK7885.7 |
| callnumber-search | TK7885.7 |
| callnumber-sort | TK 47885.7 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4030 |
| ctrlnum | (OCoLC)705736224 (DE-599)BVBBV036617001 |
| dewey-full | 621.390285/53 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.390285/53 |
| dewey-search | 621.390285/53 |
| dewey-sort | 3621.390285 253 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV036617001 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T22:44:16Z |
| institution | BVB |
| isbn | 9780137045792 0137045794 |
| language | English |
| lccn | 2009034771 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-020537116 |
| oclc_num | 705736224 |
| open_access_boolean | |
| owner | DE-92 |
| owner_facet | DE-92 |
| physical | XXIX, 367 S. Ill. 24 cm |
| publishDate | 2010 |
| publishDateSearch | 2010 |
| publishDateSort | 2010 |
| publisher | Addison-Wesley |
| record_format | marc |
| series2 | Prentice Hall modern semiconductor design series |
| spelling | Zwoliński, Mark Verfasser aut Digital system design with SystemVerilog Mark Zwolinski Upper Saddle River, NJ [u.a.] Addison-Wesley 2010 XXIX, 367 S. Ill. 24 cm txt rdacontent n rdamedia nc rdacarrier Prentice Hall modern semiconductor design series Includes bibliographical references and index Verilog (Computer hardware description language) Electronic digital computers Design and construction Computer simulation VERILOG (DE-588)4268385-3 gnd rswk-swf VERILOG (DE-588)4268385-3 s DE-604 |
| spellingShingle | Zwoliński, Mark Digital system design with SystemVerilog Verilog (Computer hardware description language) Electronic digital computers Design and construction Computer simulation VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4268385-3 |
| title | Digital system design with SystemVerilog |
| title_auth | Digital system design with SystemVerilog |
| title_exact_search | Digital system design with SystemVerilog |
| title_full | Digital system design with SystemVerilog Mark Zwolinski |
| title_fullStr | Digital system design with SystemVerilog Mark Zwolinski |
| title_full_unstemmed | Digital system design with SystemVerilog Mark Zwolinski |
| title_short | Digital system design with SystemVerilog |
| title_sort | digital system design with systemverilog |
| topic | Verilog (Computer hardware description language) Electronic digital computers Design and construction Computer simulation VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Verilog (Computer hardware description language) Electronic digital computers Design and construction Computer simulation VERILOG |
| work_keys_str_mv | AT zwolinskimark digitalsystemdesignwithsystemverilog |