Digital design, with RTL design, VHDL, and Verilog:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Hoboken, NJ
Wiley
2011
|
| Ausgabe: | 2. ed. |
| Schlagworte: | |
| Beschreibung: | Includes bibliographical references and index |
| Beschreibung: | XVI, 575 S. Ill., graph. Darst. |
| ISBN: | 9780470531082 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV036451508 | ||
| 003 | DE-604 | ||
| 005 | 20101019 | ||
| 007 | t | ||
| 008 | 100512s2011 ad|| |||| 00||| eng d | ||
| 020 | |a 9780470531082 |9 978-0-470-53108-2 | ||
| 035 | |a (OCoLC)699545960 | ||
| 035 | |a (DE-599)BVBBV036451508 | ||
| 040 | |a DE-604 |b ger |e rakwb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-29T |a DE-634 |a DE-573 |a DE-83 | ||
| 084 | |a ST 150 |0 (DE-625)143594: |2 rvk | ||
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| 084 | |a ZN 5620 |0 (DE-625)157469: |2 rvk | ||
| 100 | 1 | |a Vahid, Frank |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Digital design, with RTL design, VHDL, and Verilog |c Frank Vahid |
| 250 | |a 2. ed. | ||
| 264 | 1 | |a Hoboken, NJ |b Wiley |c 2011 | |
| 300 | |a XVI, 575 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Includes bibliographical references and index | ||
| 650 | 4 | |a Electronic digital computers / Design and construction | |
| 650 | 4 | |a Computer architecture | |
| 650 | 4 | |a RTL (Computer program language) | |
| 650 | 4 | |a VHDL (Computer hardware description language) | |
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Computer |0 (DE-588)4070083-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Computerarchitektur |0 (DE-588)4048717-9 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Computer |0 (DE-588)4070083-5 |D s |
| 689 | 0 | 1 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Computerarchitektur |0 (DE-588)4048717-9 |D s |
| 689 | 1 | 1 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 1 | 2 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 1 | |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-020323628 | ||
Datensatz im Suchindex
| _version_ | 1804142938532347904 |
|---|---|
| any_adam_object | |
| author | Vahid, Frank |
| author_facet | Vahid, Frank |
| author_role | aut |
| author_sort | Vahid, Frank |
| author_variant | f v fv |
| building | Verbundindex |
| bvnumber | BV036451508 |
| classification_rvk | ST 150 ST 250 ZN 4904 ZN 5620 |
| ctrlnum | (OCoLC)699545960 (DE-599)BVBBV036451508 |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 2. ed. |
| format | Book |
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| id | DE-604.BV036451508 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T22:39:43Z |
| institution | BVB |
| isbn | 9780470531082 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-020323628 |
| oclc_num | 699545960 |
| open_access_boolean | |
| owner | DE-29T DE-634 DE-573 DE-83 |
| owner_facet | DE-29T DE-634 DE-573 DE-83 |
| physical | XVI, 575 S. Ill., graph. Darst. |
| publishDate | 2011 |
| publishDateSearch | 2011 |
| publishDateSort | 2011 |
| publisher | Wiley |
| record_format | marc |
| spelling | Vahid, Frank Verfasser aut Digital design, with RTL design, VHDL, and Verilog Frank Vahid 2. ed. Hoboken, NJ Wiley 2011 XVI, 575 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Includes bibliographical references and index Electronic digital computers / Design and construction Computer architecture RTL (Computer program language) VHDL (Computer hardware description language) Verilog (Computer hardware description language) Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Computer (DE-588)4070083-5 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 gnd rswk-swf VERILOG (DE-588)4268385-3 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Computer (DE-588)4070083-5 s Schaltungsentwurf (DE-588)4179389-4 s DE-604 Computerarchitektur (DE-588)4048717-9 s VHDL (DE-588)4254792-1 s VERILOG (DE-588)4268385-3 s |
| spellingShingle | Vahid, Frank Digital design, with RTL design, VHDL, and Verilog Electronic digital computers / Design and construction Computer architecture RTL (Computer program language) VHDL (Computer hardware description language) Verilog (Computer hardware description language) Schaltungsentwurf (DE-588)4179389-4 gnd Computer (DE-588)4070083-5 gnd Computerarchitektur (DE-588)4048717-9 gnd VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4070083-5 (DE-588)4048717-9 (DE-588)4268385-3 (DE-588)4254792-1 |
| title | Digital design, with RTL design, VHDL, and Verilog |
| title_auth | Digital design, with RTL design, VHDL, and Verilog |
| title_exact_search | Digital design, with RTL design, VHDL, and Verilog |
| title_full | Digital design, with RTL design, VHDL, and Verilog Frank Vahid |
| title_fullStr | Digital design, with RTL design, VHDL, and Verilog Frank Vahid |
| title_full_unstemmed | Digital design, with RTL design, VHDL, and Verilog Frank Vahid |
| title_short | Digital design, with RTL design, VHDL, and Verilog |
| title_sort | digital design with rtl design vhdl and verilog |
| topic | Electronic digital computers / Design and construction Computer architecture RTL (Computer program language) VHDL (Computer hardware description language) Verilog (Computer hardware description language) Schaltungsentwurf (DE-588)4179389-4 gnd Computer (DE-588)4070083-5 gnd Computerarchitektur (DE-588)4048717-9 gnd VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd |
| topic_facet | Electronic digital computers / Design and construction Computer architecture RTL (Computer program language) VHDL (Computer hardware description language) Verilog (Computer hardware description language) Schaltungsentwurf Computer Computerarchitektur VERILOG VHDL |
| work_keys_str_mv | AT vahidfrank digitaldesignwithrtldesignvhdlandverilog |