Microelectronic circuit design:
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| Format: | Buch |
| Sprache: | English |
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New York, NY
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2011
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| Ausgabe: | 4. ed., internat. student ed. |
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| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXVI, 1334 S. Ill., graph. Darst. |
| ISBN: | 9780071221993 0071221999 |
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| 100 | 1 | |a Jaeger, Richard C. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Microelectronic circuit design |c Richard C. Jaeger ; Travis N. Blalock |
| 250 | |a 4. ed., internat. student ed. | ||
| 264 | 1 | |a New York, NY |b McGraw-Hill |c 2011 | |
| 300 | |a XXVI, 1334 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
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Datensatz im Suchindex
| _version_ | 1804142912414416896 |
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| adam_text | Titel: Microelectronic circuit design
Autor: Jaeger, Richard C
Jahr: 2011
CONTENTS
Preface xx CHAPTER 2
SOLID-STATE ELECTRONICS 42
P A R T 0 N E 2.1 Solid-State Electronic Materials 44
SOLID STATE ELECTRONIC 2-2 Covalent Bond Model 45
AND DEVICES 1 2 3 Dr ^ Currents and Mobility in
Semiconductors 48
CHAPTER 1
2.3.1 Drift Currents 48
2.3.2 Mobility 49
INTRODUCTION TO ELECTRONICS 3 2.3.3 Velocity Saturation 49
2.4 Resistivity of Intrinsic Silicon 50
2.5 Impurities in Semiconductors 51
2.5.1 Donor Impurities in Silicon 52
2.5.2 Acceptor Impurities in Silicon 52
2.6 Electron and Hole Concentrations in Doped
Semiconductors 52
2.6.1 n-Type Material (ND NA) 53
2.6.2 p-Type Material (NA ND) 54
2.7 Mobility and Resistivity in Doped
Semiconductors 55
2.8 Diffusion Currents 59
2.9 Total Current 60
2.10 Energy Band Model 61
2.10.1 Electron-Hole Pair Generation in an
Intrinsic Semiconductor 61
2.10.2 Energy Band Model for a Doped
Semiconductor 62
2.10.3 Compensated Semiconductors 62
.-,.. ._¦ ,n ,.¦ i a it 2.11 Overview of Integrated Circuit
1.7.1 Ideal Operational Amplifiers 23 ,. . s
1.1 A Brief History of Electronics:
From Vacuum Tubes to Giga-Scale
Integration 5
1.2 Classification of Electronic Signals 8
1.2.1 Digital Signals 9
1.2.2 Analog Signals 9
1.2.3 A/D and D/A Converters-Bridging
the Analog and Digital
Domains 10
1.3 Notational Conventions 12
1.4 Problem-Solving Approach 13
1.5 Important Concepts from Circuit Theory 15
1.5.1 Voltage and Current Division 15
1.5.2 Thevenin and Norton Circuit
Representations 16
1.6 Frequency Spectrum of Electronic
Signals 21
1.7 Amplifiers 22
1.7.2 Amplifier Frequency Response 25
1.8 Element Variations in Circuit Design 26
1.8.1 Mathematical Modeling of
Tolerances 26
1.8.2 Worst-Case Analysis 27
1.8.3 Monte Carlo Analysis 29
1.8.4 Temperature Coefficients 32
1.9 Numeric Precision 34
Summary 34
Key Terms 35 SOLID-STATE DIODES AND DIODE CIRCUITS 74
Summary 67
Key Terms 68
Reference 69
Additional Reading 69
Important Equations 69
Problems 70
CHAPTER 3
References 36 ,..,. ..
Additional Reading 36 31 The P Junct,on D,ode 75
Problems 37 3 1 1 P Junction Electrostatics 75
3.1.2 Internal Diode Currents 79
VII
VIII Contents
3.2 The /-y Characteristics of the Diode 80 3.14 Full-Wave Rectifier Circuits 123
3.3 The Diode Equation: A Mathematical Model 3.14.1 Full-Wave Rectifier with Negative
for the Diode 82 Output Voltage 124
3.4 Diode Characteristics Under Reverse, Zero, 3.15 Full-Wave Bridge Rectification 125
and Forward Bias 85 3.16 Rectifier Comparison and Design
3.4.1 Reverse Bias 85 Tradeoffs 125
3.4.2 Zero Bias 85 3.17 Dynamic Switching Behavior of the
3.4.3 Forward Bias 86 Diode 129
3.5 Diode Temperature Coefficient 89 3.18 Photo Diodes, Solar Cells, and
3.6 Diodes Under Reverse Bias 89 Light-Emitting Diodes 130
3.6.1 Saturation Current in Real 3.18.1 Photo Diodes and
Diodes 90 Photodetectors 130
3.6.2 Reverse Breakdown 91 3.18.2 Power Generation from Solar
3.6.3 Diode Model for the Breakdown Cells 131
Region 92 3.18.3 Light-Emitting Diodes (LEDs) 132
3.7 pn Junction Capacitance 92 Summary 133
3.7.1 Reverse Bias 92 Key Terms 134
3.7.2 Forward Bias 93 Reference 135
3.8 Schottky Barrier Diode 93 Additional Reading 135
3.9 Diode SPICE Model and Layout 94 Problems 135
3.10 Diode Circuit Analysis 96
3.10.1 Load-Line Analysis 96 CHAPTER 4
3.10.2 Analysis Using the Mathematical cicincmrrTDniJcicTftDc * ac
Model for the Diode 98 FIELD-EFFECT TRANSISTORS 145
3.10.3 The Ideal Diode Model 102 4.1 Characteristics oftheMOS Capacitor 146
3.10.4 Constant Voltage Drop Model 104 4.1,1 Accumulation Region 147
3.10.5 Model Comparison and 4.1.2 Depletion Region 148
Discussion 105 4.1.3 Inversion Region 148
3.11 Multiple-Diode Circuits 106 4.2 The NMOS Transistor 148
3.12 Analysis of Diodes Operating in the 4.2.1 Qualitative i-v Behavior of the
Breakdown Region 109 NMOS Transistor 149
3.12.1 Load-Line Analysis 109 4.2.2 Triode Region Characteristics of the
3.12.2 Analysis with the Piecewise Linear NMOS Transistor 150
Model 109 4.2.3 On Resistance 153
3.12.3 Voltage Regulation 110 4.2.4 Saturation of the i-v
3.12.4 Analysis Including Zener Characteristics 154
Resistance 111 4.2.5 Mathematical Model in the
3.12.5 Line and Load Regulation 112 Saturation (Pinch-Off) Region 155
3.13 Half-Wave Rectifier Circuits 113 4.2.6 Transconductance 157
3.13.1 Half-Wave Rectifier with Resistor 4.2.7 Channel-Length Modulation 157
Load 113 4.2.8 Transfer Characteristics and
3.13.2 Rectifier Filter Capacitor 114 Depletion-Mode MOSFETS 158
3.13.3 Half-Wave Rectifier with RC 4.2.9 Body Effect or Substrate
Load 115 Sensitivity 159
3.13.4 Ripple Voltage and Conduction 4.3 PMOS Transistors 161
Interval 116 4.4 MOSFET Circuit Symbols 163
3.13.5 Diode Current 118 4.5 Capacitances in MOS Transistors 165
3.13.6 Surge Current 120 4.5.1 NMOS Transistor Capacitances in
3.13.7 Peak-lnverse-Voltage (PIV) the Triode Region 165
Rating 120 4.5.2 Capacitances in the Saturation
3.13.8 Diode Power Dissipation 120 Region 166
3.13.9 Half-Wave Rectifier with Negative 4.5.3 Capacitances in Cutoff 166
Output Voltage 121 4.6 MOSFET Modeling in SPICE 167
Contents IX
4.7 MOS Transistor Scaling 169 5.3 The pnp Transistor 225
4.7.1 Drain Current 169 5.4 Equivalent Circuit Representations for the
4.7.2 Gate Capacitance 169 Transport Models 227
4.7.3 Circuit and Power Densities 170 5.5 The i-v Characteristics of the Bipolar
4.7.4 Power-Delay Product 170 Transistor 228
4.7.5 Cutoff Frequency 171 5.5.1 Output Characteristics 228
4.7.6 High Field Limitations 171 5.5.2 Transfer Characteristics 229
4.7.7 Subthreshold Conduction 172 5.6 The Operating Regions of the Bipolar
4.8 MOS Transistor Fabrication and Layout Transistor 230
Design Rules 172 5.7 Transport Model Simplifications 231
4.8.1 Minimum Feature Size and 5.7.1 Simplified Model for the Cutoff
Alignment Tolerance 173 Region 231
4.8.2 MOS Transistor Layout 173 5.7.2 Model Simplifications for the
4.9 Biasing the NMOS Field-Effect Forward-Active Region 233
Transistor 176 5.7.3 Diodes in Bipolar Integrated
4.9.1 Why Do We Need Bias? 176 Circuits 239
4.9.2 Constant Gate-Source Voltage 5.7.4 Simplified Model for the
Bias 178 Reverse-Active Region 240
4.9.3 Load Line Analysis for the 5.7.5 Modeling Operation in the
Q-Point 181 Saturation Region 242
4.9.4 Four-Resistor Biasing 182 5.8 Nonideal Behavior of the Bipolar
4.10 Biasing the PMOS Field-Effect Transistor 245
Transistor 188 5.8.1 Junction Breakdown Voltages 246
4.11 The Junction Field-Effect Transistor 5.8.2 Minority-Carrier Transport in the
(JFET) 190 Base Region 246
4.11.1 The JFET with Bias Applied 191 5.8.3 Base Transit Time 247
4.11.2 JFET Channel with Drain-Source 5.8.4 Diffusion Capacitance 249
Bias 191 5.8.5 Frequency Dependence of the
4.11.3 f?-ChannelJFET/-v Common-Emitter Current
Characteristics 193 Gain 250
4.11.4 The p-Channel JFET 195 5.8.6 The Early Effect and Early
4.11.5 Circuit Symbols and JFET Model Voltage 250
Summary 195 5.8.7 Modeling the Early Effect 251
4.11.6 JFET Capacitances 196 5.8.8 Origin of the Early Effect 251
4.12 JFET Modeling in SPICE 197 5.9 Transconductance 252
4.13 Biasing the JFET and Depletion-Mode 5.10 Bipolar Technology and SPICE Model 253
MOSFET 198 5.10.1 Qualitative Description 253
Summary 200 5.10.2 SPICE Model Equations 254
Key Terms 202 5.10.3 High-Performance Bipolar
References 203 Transistors 255
Problems 204 5.11 Practical Bias Circuits for the BJT 256
5.11.1 Four-Resistor Bias Network 258
CHAPTERS 5.11.2 Design Objectives for the
mnni m iiiiirrinuTDAucicTnnc 7 Four-Resistor Bias Network 260
BIPOLAR JUNCTION TRANSISTORS 217 5113 lterativeAnalysisofthe
5.1 Physical Structure of the Bipolar Four-Resistor Bias Circuit 266
Transistor 218 5.12 Tolerances in Bias Circuits 266
5.2 The Transport Model for the npn 5.12.1 Worst-Case Analysis 267
Transistor 219 5.12.2 Monte Carlo Analysis 269
5.2.1 Forward Characteristics 220 Summary 272
5.2.2 Reverse Characteristics 222 Key Terms 274
5.2.3 The Complete Transport Model References 274
Equations for Arbitrary Bias Problems 275
Conditions 223
Contents
DIGITAL ELECTRONICS 285
CHAPTER 6
PART TWO 6.11.1 Capacitances in Logic Circuits 337
6.11.2 Dynamic Response of the NMOS
Inverter with a Resistive Load 338
6.11.3 Pseudo NMOS Inverter 343
6.11.4 A Final Comparison of NMOS
INTRODUCTION TO DIGITAL ELECTRONICS 287 Inverter Delays 344
..... 6.11.5 Scaling Based Upon Reference
6.1 Idea Logic Gates 289 r. ° ... .
, ..._,.. . .... Circuit Simulation 346
6.2 Logic Level Definitions and No.se 6116 Ring 0scillator Measurement of
Margins 289 Intrinsic Gate Delay 346
6.11.7 Unloaded Inverter Delay 347
6.12 PMOS Logic 349
6.12.1 PMOS Inverters 349
6.12.2 NOR and NAND Gates 352
Summary 352
Key Terms 354
References 355
Additional Reading 355
Problems 355
CHAPTER 7
6.2.1 Logic Voltage Levels 291
6.2.2 Noise Margins 291
6.2.3 Logic Gate Design Goals 292
6.3 Dynamic Response of Logic Gates 293
6.3.1 Rise Time and Fall Time 293
6.3.2 Propagation Delay 294
6.3.3 Power-Delay Product 294
6.4 Review of Boolean Algebra 295
6.5 NMOS Logic Design 297
6.5.1 NMOS Inverter with Resistive
Load 298
6.5.2 Design of the W/L Ratio of Ms 299
6.5.3 Load Resistor Design 300 COMPLEMENTARY MOS (CMOS) LOGIC
6.5.4 Load-Line Visualization 300 DESIGN 367
6.5.5 On-Resistance of the Switching
Device 302 71 CMOS Inverter Technology 368
6.5.6 Noise Margin Analysis 303 7-1-1 CMOS Inverter Layout 370
6.5.7 Calculation of VIL and V0H 303 7-2 Static Characteristics of the CMOS
6.5.8 Calculation of VIH and V0L 304 Inverter 370
6.5.9 Load Resistor Problems 305 7-2-1 CMOS Voltage Transfer
6.6 Transistor Alternatives to the Load Characteristics 371
Resistor 306 7-2-2 Noise Margins for the CMOS
6.6.1 The NMOS Saturated Load Inverter 373
Inverter 307 7-3 Dynamic Behavior of the CMOS Inverter 375
6.6.2 NMOS Inverter with a Linear Load 7-3-1 Propagation Delay Estimate 375
Device 315 7-3-2 Rise and Fall Times 377
6.6.3 NMOS Inverter with a 7-3-3 Performance Scaling 377
Depletion-Mode Load 316 7-3-4 Delay of Cascaded Inverters 379
6.6.4 Static Design of the Pseudo NMOS 7A Power Dissipation and Power Delay Product
Inverter 319 in CM0S 380
6.7 NMOS Inverter Summary and 7-4-1 Static Power Dissipation 380
Comparison 323 7-4-2 Dynamic Power Dissipation 381
6.8 NMOS NAND and NOR Gates 324 7-4-3 Power-Delay Product 382
6.8.1 NOR Gates 325 7-5 CM0S N0R and NAND Gates 384
6A2 NAND Gates 326 7-5-1 CM( S N°R Gate 384
6.8.3 NOR and NAND Gate Layouts in 7-5-2 CMOS NAND Gates 387
NMOS Depletion-Mode 7-6 Design of Complex Gates in CMOS 388
Technology 327 7-7 Minimum Size Gate Design and
6.9 Complex NMOS Logic Design 328 Performance 393
6.10 Power Dissipation 333 7-8 Dynamic Domino CMOS Logic 395
6.10.1 Static Power Dissipation 333 7-9 Cascade Buffers 397
6 10 2 Dynamic Power Dissipation 334 7-9-1 Cascade Buffer Delay Model 397
6.10.3 Power Scaling in MOS Logic 7-9-2 Optimum Number of Stages 398
Gates 335 710 The CMOS Transmission Gate 400
6.11 Dynamic Behavior of MOS Logic Gates 337 7A1 CM0S Latchup 401
Contents XI
Summary 404 9.1.2 Current Switch Analysis for
Key Terms 405 v, I/REf 463
References 406 9.1.3 Current Switch Analysis for
Problems 406 Vi VKf 464
9.2 The Emitter-Coupled Logic (ECL) Gate 464
CHAPTER 8 9-2.1 ECL Gate with v, = VH 465
MOS MEMORY AND STORAGE CIRCUITS 416 l** fcL Gate with v, = ^J 36
9.2.3 Input Current of the ECL Gate 466
8.1 Random Access Memory 417 9.2.4 ECL Summary 466
8.1.1 Random Access Memory (RAM) 9.3 Noise Margin Analysis for the ECL Gate 467
Architecture 417 9.3.1 VIL, V0h, ViH,and Vol 467
8.1.2 A 256-Mb Memory Chip 418 9.3.2 Noise Margins 468
8.2 Static Memory Cells 419 9.4 Current Source Implementation 469
8.2.1 Memory Ceil Isolation and 9.5 The ECL OR-NOR Gate 471
Access-The 6-T Cell 422 9.6 The Emitter Follower 473
8.2.2 The Read Operation 422 9.6.1 Emitter Follower with a Load
8.2.3 Writing Data into the 6-T Cell 426 Resistor 474
8.3 Dynamic Memory Cells 428 9.7 Emitter Dotting or Wired-OR Logic 476
8.3.1 The One-Transistor Cell 430 9.7.1 Parallel Connection of
8.3.2 Data Storage in the i-T Cell 430 Emitter-Follower Outputs 477
8.3.3 Reading Data from the i-T Cell 431 9.7.2 The Wired-OR Logic Function 477
8.3.4 The Four-Transistor Cell 433 9.8 ECL Power-Delay Characteristics 477
8.4 Sense Amplifiers 434 9.8.1 Power Dissipation 477
8.4.1 A Sense Amplifier for the 6-T 9.8.2 Gate Delay 479
Cell 434 9.8.3 Power-Delay Product 480
8.4.2 A Sense Amplifier for the i-T 9.9 Current Mode Logic 481
Cell 436 9.9.1 CML Logic Gates 481
8.4.3 The Boosted Wordline Circuit 438 9.9.2 CML Logic Levels 482
8.4.4 Clocked CMOS Sense 9.9.3 VEC Supply Voltage 482
Amplifiers 438 9.9.4 Higher-Level CML 483
8.5 Address Decoders 440 9.9.5 CML Power Reduction 484
8.5.1 NOR Decoder 440 9.9.6 NMOS CML 485
8.5.2 NAND Decoder 440 9.10 The Saturating Bipolar Inverter 487
8.5.3 Decoders in Domino CMOS 9.10.1 Static Inverter Characteristics 488
Logic 443 9.10.2 Saturation Voltage of the Bipolar
8.5.4 Pass-Transistor Column Transistor 488
Decoder 443 9.10.3 Load-Line Visualization 491
8.6 Read-Only Memory (ROM) 444 9.10.4 Switching Characteristics of the
8.7 Flip-Flops 447 Saturated BJT 491
8.7.1 RSFlip-Flop 449 9.11 A Transistor-Transistor Logic (TTL)
8.7.2 The D-Latch Using Transmission Prototype 494
Gates 450 9.11.1 TTL Inverter for v, = VL 494
8.7.3 A Master-Slave D Flip-Flop 450 9.11.2 TTL Inverter for v, = VH 495
Summary 451 9.11.3 Power in the Prototype TTL
Key Terms 452 Gate 496
References 452 9.11.4 Vm, VIL, and Noise Margins for the
Problems 453 TTL Prototype 496
9.11.5 Prototype Inverter Summary 498
CHAPTER 9 9.11.6 Fanout Limitations of the TTL
BIPOLAR LOGIC CIRCUITS 460
Prototype 498
9.12 The Standard 7400 Series TTL Inverter 500
9.1 The Current Switch (Emitter-Coupled 9-12.1 Analysis for v, = VL 500
Pair) 461 9.12.2 Analysis for v, - VH 501
9.1.1 Mathematical Model for Static
Behavior of the Current Switch 462
XII Contents
9.12.3 Power Consumption 503 10.9 Analysis of Circuits Containing Ideal
9.12.4 TTL Propagation Delay and Operational Amplifiers 552
Power-Delay Product 503 10.9.1 The Inverting Amplifier 553
9.12.5 TTL Voltage Transfer Characteristic 10.9.2 The Transresistance Amplifier-A
and Noise Margins 503 Current-to-Voltage Converter 556
9.12.6 Fanout Limitations of Standard 10.9.3 The Noninverting Amplifier 558
TTL 504 10.9.4 The Unity-Gain Buffer, or Voltage
9.13 Logic Functions in TTL 504 Follower 561
9.13.1 Multi-Emitter Input Transistors 505 10.9.5 The Summing Amplifier 563
9.13.2 TTL NAND Gates 505 10.9.6 The Difference Amplifier 565
9.13.3 Input Clamping Diodes 506 10.10 Frequency-Dependent Feedback 568
9.14 Schottky-Clamped TTL 506 10.10.1 Bode Plots 568
9.15 Comparison of the Power-Delay Products of 10.10.2 The Low-Pass Amplifier 568
ECL and TTL 508 10.10.3 The High-Pass Amplifier 572
9.16 BiCMOS Logic 508 10.10.4 Band-Pass Amplifiers 575
9.16.1 BiCMOS Buffers 509 10.10.5 An Active Low-Pass Filter 578
9.16.2 BiNMOS Inverters 511 10.10.6 An Active High-Pass Filter 581
9.16.3 BiCMOS Logic Gates 513 10.10.7 The Integrator 582
Summary 513 10.10.8 The Differentiator 586
Key Terms 515 Summary 586
References 515 Key Terms 588
Additional Reading 515 References 588
Problems 516 Additional Reading 589
Problems 589
PART THREE
ANALOG ELECTRONICS 527 chapter 11
NONIDEAL OPERATIONAL AMPLIFIERS AND
CHAPTER 10 FEEDBACK AMPLIFIER STABILITY 600
ANALOG SYSTEMS AND IDEAL OPERATIONAL 11.1 classic Feedback Systems 601
AMPLIFIERS 529 11.1.1 Closed-Loop Gain Analysis 602
_ . _ . , . . _. t . 11.1.2 Gain Error 602
10.1 An Example of an Analog Electronic .... . , . ,,. .. -. . . . .. .. ,
_ ,. :. 11.2 Analysis of Circuits Containing Nonideal
System 530 _. .. . . ..
Operational Amplifiers 603
11.2.1 Finite Open-Loop Gain 603
11.2.2 Nonzero Output Resistance 606
11.2.3 Finite Input Resistance 610
11.2.4 Summary of Nonideal Inverting and
T _»...,*. ,t ^ , Noninverting Amplifiers 614
10.3 Two-Port Models for Amphfiers 537 3 series and Shunt Feedback Circuits 615
in a m . k rfefParame?,fS T 11-3-1 FeedbackAmplifierCategories 615
10.4 Mismatched Source and Load .noo w ¦» » a it, c • c-u *
. . r.* 11.3.2 Voltage Amplifiers-Series-Shunt
Resistances 541 c .£ . J _
*n^ i » j ^- ^ « .. .. .... . Feedback 616
10.5 In^uc^toOpen^lAmpUfiers 544 Transimpedance
ntl The D,fferent,alAmphfier 544 Amptifiers-Shunt-Shunt
10.5.2 DifferentalAmplifierVoltage Fee^back
Transfer Characteristic 545 _ . r tA ..» ... . c .
10.5.3 Voltage Gain 545 1134 CurrentAmplifiers-Shunt-Ser.es
10.6 Distortion in Amplifiers 548 Feedback 616
10.7 Differential Amplifier Model 549 1135 Transconductance
Ideal Differential and Operational Amplifiers-Ser.es-Ser.es
Amplifiers 551 Feedback 616
10.8.1 Assumptions for Ideal Operational 114 JJJS Approach to Feedback Amplifier Gain
Amplifier Analysis 551
10.2 Amplification 531
10.2.1 Voltage Gain 532
10.2.2 Current Gain 533
10.2.3 Power Gain 533
10.2.4 The Decibel Scale 534
10.8
Calculation 616
Contents Xlll
11.4.1 Closed-Loop Gain Analysis 617 11.12.5 An Alternate Interpretation of
11.4.2 Resistance Calculation Using CMRR 657
Blackman S Theorem 617 11.12.6 Power Supply Rejection Ratio 657
11.5 Series-Shunt Feedback-Voltage 11.13 Frequency Response and Bandwidth of
Amplifiers 617 Operational Amplifiers 659
11.5.1 Closed-Loop Gain Calculation 618 11.13.1 Frequency Response of the
11.5.2 Input Resistance Calculation 618 Noninverting Amplifier 661
11.5.3 Output Resistance 11.13.2 Inverting Amplifier Frequency
Calculation 619 Response 664
11.5.4 Series-Shunt Feedback Amplifier 11.13.3 Using Feedback to Control
Summary 620 Frequency Response 666
11.6 Shunt-Shunt Feedback-Transresistance 11.13.4 Large-Signal Limitations-Slew
Amplifiers 624 Rate and Full-Power
11.6.1 Closed-Loop Gain Calculation 625 Bandwidth 668
11.6.2 Input Resistance Calculation 625 11.13.5 Macro Model for Operational
11.6.3 Output Resistance Calculation 625 Amplifier Frequency Response 669
11.6.4 Shunt-Shunt Feedback Amplifier 11.13.6 Complete Op Amp Macro Models in
Summary 626 SPICE 670
11.7 Series-Series Feedback-Transconductance 11.13.7 Examples of Commercial
Amplifiers 629 General-Purpose Operational
11.7.1 Closed-Loop Gain Calculation 630 Amplifiers 670
11.7.2 Input Resistance Calculation 630 11.14 Stability of Feedback Amplifiers 671
11.7.3 Output Resistance Calculation 631 11.14.1 The Nyquist Plot 671
11.7.4 Series-Series Feedback Amplifier 11.14.2 First-Order Systems 672
Summary 631 11.14.3 Second-Order Systems and Phase
11.8 Shunt-Series Feedback-Current Margin 673
Amplifiers 633 11.14.4 Step Response and Phase
11.8.1 Closed-Loop Gain Calculation 634 Margin 674
11.8.2 Input Resistance Calculation 635 11.14.5 Third-Order Systems and Gain
11.8.3 Output Resistance Calculation 635 Margin 677
11.8.4 Series-Series Feedback Amplifier 11.14.6 Determining Stability from the
Summary 635 Bode Plot 678
11.9 Finding the Loop Gain Using Successive Summary 682
Voltage and Current Injection 638 Key Terms 684
11.9.1 Simplifications 641 References 684
11.10 Distortion Reduction Through the Use of Problems 685
Feedback 641
11.11 DC Error Sources and Output Range CHAPTER 12
Limitations 642
11.11.1 Input-Offset Voltage 643
11.11.2 Offset-Voltage Adjustment 644 12.1 Cascaded Amplifiers 698
11.11.3 Input-Bias and Offset 12.1.1 Two-Port Representations 698
Currents 645 12.1.2 Amplifier Terminology Review 700
11.11.4 Output Voltage and Current 12.1.3 Frequency Response of Cascaded
Limits 647 Amplifiers 703
11.12 Common-Mode Rejection and Input 12.2 The Instrumentation Amplifier 711
Resistance 650 12.3 Active Filters 714
11.12.1 Finite Common-Mode Rejection 12.3.1 Low-Pass Filter 714
Ratio 650 12.3.2 A High-Pass Filter with Gain 718
11.12.2 Why Is CMRR Important? 651 12.3.3 Band-Pass Filter 720
11.12.3 Voltage-Follower Gain Error Due to 12.3.4 The Tow-Thomas Biquad 722
CMRR 654 12.3.5 Sensitivity 726
11.12.4 Common-Mode Input 12.3.6 Magnitude and Frequency
Resistance 656 Scaling 727
OPERATIONAL AMPLIFIER APPLICATIONS 697
XIV Contents
12.4 Switched-Capacitor Circuits 728 13.5 Small-Signal Models for Bipolar Junction
12.4.1 A Switched-Capacitor Transistors 799
Integrator 728 13.5.1 The Hybrid-Pi Model 801
12.4.2 Noninverting SC Integrator 730 13.5.2 Graphical Interpretation of the
12.4.3 Switched-Capacitor Filters 732 Transconductance 802
12.5 Digital-to-Analog Conversion 733 13.5.3 Small-Signal Current Gain 802
12.5.1 D/A Converter Fundamentals 733 13.5.4 The Intrinsic Voltage Gain of the
12.5.2 D/A Converter Errors 734 BJT 803
12.5.3 Digital-to-Analog Converter 13.5.5 Equivalent Forms of the
Circuits 737 Small-Signal Model 804
12.6 Analog-to-Digital Conversion 740 13.5.6 Simplified Hybrid Pi Model 805
12.6.1 A/D Converter Fundamentals 741 13.5.7 Definition of a Small Signal for the
12.6.2 Analog-to-Digital Converter Bipolar Transistor 805
Errors 742 13.5.8 Small-Signal Model for the pop
12.6.3 Basic A/D Conversion Transistor 807
Techniques 743 13.5.9 ac Analysis Versus Transient
12.7 Oscillators 754 Analysis in SPICE 807
12.7.1 The Barkhausen Criteria for 13.6 The Common-Emitter (C-E) Amplifier 808
Oscillation 754 13.6.1 Terminal Voltage Gain 809
12.7.2 Oscillators Employing 13.6.2 Input Resistance 809
Frequency-Selective RC 13.6.3 Signal Source Voltage Gain 810
Networks 755 13.7 Important Limits and Model
12.8 Nonlinear Circuit Applications 760 Simplifications 810
12.8.1 A Precision Half-Wave Rectifier 760 13.7.1 A Design Guide for the
12.8.2 Nonsaturating Precision-Rectifier Common-Emitter Amplifier 810
Circuit 761 13.7.2 Upper Bound on the
12.9 Circuits Using Positive Feedback 763 Common-Emitter Gain 812
12.9.1 The Comparator and Schmitt 13.7.3 Small-Signal Limit for the
Trigger 763 Common-emitter Amplifier 812
12.9.2 The Astable Multivibrator 765 13.8 Small-Signal Models for Field-Effect
12.9.3 The Monostable Multivibrator or Transistors 815
One Shot 766 13.8.1 Small-Signal Model for
Summary 770 the MOSFET 815
Key Terms 772 13.8.2 Intrinsic Voltage Gain of
Additional Reading 773 the MOSFET 817
Problems 773 13.8.3 Definition of Small-Signal
Operation for the MOSFET 817
CHAPTER 13 13.8.4 Body Effect in the Four-Terminal
SMALL-SIGNAL MODELING AND LINEAR
AMPLIFICATION 786
MOSFET 818
13.8.5 Small-Signal Model for the PMOS
Transistor 819
13.1 The Transistor as an Amplifier 787 13.8.6 Small-Signal Model for the Junction
13.1.1 The BJT Amplifier 788 Field-Effect Transistor 820
13.1.2 The MOSFET Amplifier 789 13.9 Summary and Comparison of the
13.2 Coupling and Bypass Capacitors 790 Small-Signal Models of the BJT and FET 821
13.3 Circuit Analysis Using dc and ac Equivalent 13.10 The Common-Source Amplifier 824
Circuits 792 13.10.1 Common-Source Terminal Voltage
13.3.1 Menu for dc and ac Analysis 792 Gain 825
13.4 Introduction to Small-Signal Modeling 796 13.10.2 Signal Source Voltage Gain for the
13.4.1 Graphical Interpretation of the Common-Source Amplifier 825
Small-Signal Behavior of the 13.10.3 A Design Guide for the
Diode 796 Common-Source Amplifier 826
13.4.2 Small-Signal Modeling of the 13.10.4 Small-Signal Limit for the
Diode 797 Common-Source Amplifier 827
Contents XV
13.10.5 Input Resistances of the 14.3 Follower Circuits-Common-Collector and
Common-Emitter and Common-Drain Amplifiers 886
Common-Source Amplifiers 829 14.3.1 Terminal Voltage Gain 886
13.10.6 Common-Emitter and 14.3.2 Input Resistance 887
Common-Source Output 14.3.3 Signal Source Voltage Gain 888
Resistances 832 14.3.4 Follower Signal Range 888
13.10.7 Comparison of the Three Amplifier 14.3.5 Follower Output Resistance 889
Resistances 838 14.3.6 Current Gain 890
13.11 Common-Emitter and Common-Source 14.3.7 C-C/C-D Amplifier Summary 890
Amplifier Summary 838 14.4 Noninverting Amplifiers-Common-Base
13.11.1 Guidelines for Neglecting the and Common-Gate Circuits 894
Transistor Output 14.4.1 Terminal Voltage Gain and Input
Resistance 839 Resistance 895
13.12 Amplifier Power and Signal Range 839 14.4.2 Signal Source Voltage Gain 896
13.12.1 Power Dissipation 839 14.4.3 Input Signal Range 897
13.12.2 Signal Range 840 14.4.4 Resistance at the Collector and
Summary 843 Drain Terminals 897
Key Terms 844 14.4.5 Current Gain 898
Problems 845 14.4.6 Overall Input and Output
Resistances for the Noninverting
CHAPTER 14 Amplifiers 899
SINGLE-TRANSISTOR AMPLIFIERS 857 R *Alr C-B/C-G Amplifier Summary 902
14.5 Amplifier Prototype Review and
14.1 Amplifier Classification 858 Comparison 903
14.1.1 Signal Injection and 14.5.1 The BJT Amplifiers 903
Extraction-The BJT 858 14.5.2 The FET Amplifiers 905
14.1.2 Signal Injection and 14.6 Common-Source Amplifiers Using MOS
Extraction-The FET 859 Inverters 907
14.1.3 Common-Emitter (C-E) and 14.6.1 Voltage Gain Estimate 908
Common-Source (C-S) 14.6.2 Detailed Analysis 909
Amplifiers 860 14.6.3 Alternative Loads 910
14.1.4 Common-Collector (C-C) and 14.6.4 Input and Output Resistances 911
Common-Drain (C-D) 14.7 Coupling and Bypass Capacitor Design 914
Topologies 861 14.7.1 Common-Emitter and
14.1.5 Common-Base (C-B) and Common-Source Amplifiers 914
Common-Gate (C-G) Amplifiers 863 14.7.2 Common-Collector and
14.1.6 Small-Signal Model Review 864 Common-Drain Amplifiers 919
14.2 Inverting Amplifiers-Common-Emitter and 14.7.3 Common-Base and Common-Gate
Common-Source Circuits 864 Amplifiers 921
14.2.1 The Common-Emitter (C-E) 14.7.4 Setting Lower Cutoff Frequency
Amplifier 864 ft 924
14.2.2 Common-Emitter Example 14.8 Amplifier Design Examples 925
Comparison 877 14.8.1 Monte Carlo Evaluation of the
14.2.3 The Common-Source Amplifier 877 Common-Base Amplifier
14.2.4 Small-Signal Limit for the Design 934
Common-Source Amplifier 880 14.9 Multistage ac-Coupled Amplifiers 939
14.2.5 Common-Emitter and 14.9.1 A Three-Stage ac-Coupled
Common-Source Amplifier Amplifier 939
Characteristics 884 14.9.2 Voltage Gain 941
14.2.6 C-E/C-S Amplifier Summary 885 14.9.3 Input Resistance 943
14.2.7 Equivalent Transistor 14.9.4 Signal Source Voltage Gain 943
Representation of the Generalized 14.9.5 Output Resistance 943
C-E/C-S Transistor 885 14.9.6 Current and Power Gain 944
XVI Contents
14.9.7 Input Signal Range 945
14.9.8 Estimating the Lower Cutoff 15-2-5 BiCMOS Amplifiers 1004
Frequency of the Multistage 15-2-6 All Transistor
Amplifier 948 Implementations 1004
Summary 950 15-3 Output Stages 1006
Key Terms 951 15.3.1 The Source Follower-A Class-A
Additional Reading 952 0utPut StaSe 1006
Problems 952 15-3-2 Efficiency of Class-A
Amplifiers 1007
/-u.r -ri- ic 15.3.3 Class-B Push-PullOutput
CHAPTER15 Stage 1008
DIFFERENTIAL AMPLIFIERS AND OPERATIONAL 15.34 ciass-AB Amplifiers 1010
AMPLIFIER DESIGN 968 15.3.5 Class-AB Output Stages for
Operational Amplifiers 1011
15.3.6 Short-Circuit Protection 1011
15.3.7 Transformer Coupling 1013
15.4 Electronic Current Sources 1016
15.4.1 Single-Transistor Current
Sources 1017
15.4.2 Figure of Merit for Current
Sources 1017
15.4.3 Higher Output Resistance
Sources 1018
15.1 Differential Amplifiers 969
15.1.1 Bipolar and MOS Differential
Amplifiers 969
15.1.2 dc Analysis of the Bipolar
Differential Amplifier 970
15.1.3 Transfer Characteristic for the
Bipolar Differential
Amplifier 972
15.1.4 ac Analysis of the Bipolar
Differential Amplifier 973 .
15.1.5 Differential-Mode Gain and Input 15A4 Current Source Des.gn
and Output Resistances 974 Examples 1018
15.1.6 Common-Mode Gain and Input Summary 1027
Resistance 976 Key Terms 1028
15.1.7 Common-Mode Rejection Ratio AeJ^encef J02?.
(CMRR) 978 Additional Reading 1029
15.1.8 Analysis Using Differential-and Problems 1029
Common-Mode Half-Circuits 979
15.1.9 Biasing with Electronic Current CHAPTER16
Sources 982 ANALOG INTEGRATED CIRCUIT DESIGN
15.1.10 Modeling the Electronic Current TECHNIQUES 1046
Source in SPICE 983
15.1.11 dc Analysis of the MOSFET 16-1 Circuit Element Matching 1047
Differential Amplifier 983 16-2 Current Mirrors 1049
15.1.12 Differential-Mode Input 16-2-1 dc Analysis of the MOS Transistor
Signals 985 Current Mirror 1049
15.1.13 Small-Signal Transfer 16-2.2 Changing the MOS Mirror
Characteristic for the MOS Ratio 1051
Differential Amplifier 986 16-2-3 dc Analysis of the Bipolar
15.1.14 Common-Mode Input Signals 986 Transistor Current Mirror 1052
15.1.15 Two-Port Model for Differential 16-2-4 Altering the BJT Current Mirror
Pairs 987 totio 1054
15.2 Evolution to Basic Operational 1fi-2-5 Multiple Current Sources 1055
Amplifiers 991 16.2.6 Buffered Current Mirror 1056
15.2.1 A Two-Stage Prototype for an 16-2-7 Output Resistance of the Current
Operational Amplifier 992 Mirrors 1057
15.2.2 Improving the Op Amp Voltage 16-2-8 Two-Port Model for the Current
Gain 997 Mirror 1058
15.2.3 Output Resistance Reduction 998 16-2-9 The Widlar Current Source 1060
15.2.4 A CMOS Operational Amplifier 16-2-10 The MOS Version of the Widlar
Prototype 1002 Source 1063
Contents XVII
16.3 High-Output-Resistance Current CHAPTER 17
Mirrors 1063 AMPLIFIER FREQUENCY RESPONSE 1128
16.3.1 The Wilson Current Sources 1064
16.3.2 Output Resistance of the Wilson 17.1 Amplifier Frequency Response 1129
Source 1065 17.1.1 Low-Frequency Response 1130
16.3.3 Cascode Current Sources 1066 17.1.2 Estimating coL in the Absence of a
16.3.4 Output Resistance of the Cascode Dominant Pole 1130
Sources 1067 17.1.3 High-Frequency Response 1133
16.3.5 Regulated Cascode Current 17.1.4 Estimating coH in the Absence of a
Source 1068 Dominant Pole 1133
16.3.6 Current Mirror Summary 1069 17.2 Direct Determination of the Low-Frequency
16.4 Reference Current Generation 1072 Poles and Zeros-The Common-Source
16.5 Supply-Independent Biasing 1073 Amplifier 1134
16.5.1 A Vbe-Based Reference 1073 17.3 Estimation of wL Using the Short-Circuit
16.5.2 The Widlar Source 1073 Time-Constant Method 1139
16.5.3 Power-Supply-lndependent Bias 17.3.1 Estimate of coL for the
Cell 1074 Common-Emitter Amplifier 1140
16.5.4 A Supply-Independent MOS 17.3.2 Estimate of wL for the
Reference Cell 1075 Common-Source Amplifier 1144
16.6 The Bandgap Reference 1077 17.3.3 Estimate of a L for the
16.7 The Current Mirror As an Active Common-Base Amplifier 1145
Load 1081 17.3.4 Estimate of wL for the
16.7.1 CMOS Differential Amplifier with Common-Gate Amplifier 1146
Active Load 1081 17.3.5 Estimate of a L for the
16.7.2 Bipolar Differential Amplifier with Common-Collector Amplifier 1147
Active Load 1088 17.3.6 Estimate of wL for the
16.8 Active Loads in Operational Common-Drain Amplifier 1147
Amplifiers 1092 17.4 Transistor Models at High Frequencies 1148
16.8.1 CMOS Op Amp Voltage 17.4.1 Frequency-Dependent Hybrid-Pi
Gain 1092 Model for the Bipolar
16.8.2 dc Design Considerations 1093 Transistor 1148
16.8.3 Bipolar Operational 17.4.2 Modeling Cn and C in SPICE 1149
Amplifiers 1095 17.4.3 Unity-Gain Frequency fT 1149
16.8.4 Input Stage Breakdown 1096 17.4.4 High-Frequency Model for the
16.9 The HA741 Operational Amplifier 1097 FET 1152
16.9.1 Overall Circuit Operation 1097 17.4.5 Modeling C6S and CGD in
16.9.2 Bias Circuitry 1098 SPICE 1153
16.9.3 dc Analysis of the 741 Input 17.4.6 Channel Length Dependence of
Stage 1099 fT 1153
16.9.4 ac Analysis of the 741 Input 17.4.7 Limitations of the High-Frequency
Stage 1102 Models 1155
16.9.5 Voltage Gain of the Complete 17.5 Base Resistance in the Hybrid-Pi
Amplifier 1103 Model 1155
16.9.6 The 741 Output Stage 1107 17.5.1 Effect of Base Resistance on
16.9.7 Output Resistance 1109 Midband Amplifiers 1156
16.9.8 Short Circuit Protection 1109 17.6 High-Frequency Common-Emitter and
16.9.9 Summary of the HA741 Common-Source Amplifier Analysis 1158
Operational Amplifier 17.6.1 The Miller Effect 1159
Characteristics 1109 17.6.2 Common-Emitter and
16.10 The Gilbert Analog Multiplier 1110 Common-Source Amplifier
Summary 1112 High-Frequency Response 1160
Key Terms 1113 17.6.3 Direct Analysis of the
References 1114 Common-Emitter Transfer
Problems 1114 Characteristic 1162
TRANSISTOR FEEDBACK AMPLIFIERS
AND OSCILLATORS 1228
XVIII Contents
17.6.4 Poles of the Common-Emitter Summary 1213
Amplifier 1163 Key Terms 1215
17.6.5 Dominant Pole for the Reference 1215
Common-Source Amplifier 1166 Problems 1215
17.6.6 Estimation of dh Using the
Open-Circuit Time-Constant CHAPTER 18
Method 1167
17.6.7 Common-Source Amplifier with
Source Degeneration
Resistance 1170 18.1 Basic Feedback System Review 1229
17.6.8 Poles of the Common-Emitter with 18.1.1 Closed-Loop Gain 1229
Emitter Degeneration 18.1.2 Closed-Loop Impedances 1230
Resistance 1172 18.1.3 Feedback Effects 1230
17.7 Common-Base and Common-Gate 18.2 Feedback Amptifier Analysis at
Amplifier High-Frequency Response 1174 Midband 1232
17.8 Common-Collector and Common-Drain i8.3 Feedback Amplifier Circuit Examples 1234
Amplifier High-Frequency Response 1177 18.3.1 Series-Shunt Feedback-Voltage
17.9 Single-stage Amplifier High-Frequency Amplifiers 1234
Response Summary 1179 18.3.2 Differential Input Series-Shunt
17.9.1 Amplifier Gain-Bandwidth Voltage Amplifier 1239
Limitations 1180 -I8.3.3 Shunt-Shunt
17.10 Frequency Response of Multistage Feedback-Transresistance
Amplifiers 1181 Amplifiers 1242
17.10.1 Differential Amplifier 1181 18.3.4 Series-Series
17.10.2 The Common-Collector/ Feedback-Transconductance
Common-Base Cascade 1182 Amplifiers 1248
17.10.3 High-Frequency Response of the -18,3.5 Shunt-Series Feedback-Current
Cascode Amplifier 1184 Amplifiers 1251
17.10.4 Cutoff Frequency for the Current 13.4 Review of Feedback Amplifier Stability 1254
Mirror 1185 18.4.1 Closed-Loop Response of the
17.10.5 Three-Stage Amplifier Uncompensated Amplifier 1254
Example 1187 18.4.2 Phase Margin 1256
17.11 Introduction to Radio Frequency -I8.4.3 Higher-Order Effects 1259
Circuits 1193 13.4.4 Response of the Compensated
17.11.1 Radio Frequency Amplifiers 1194 Amplifier 1260
17.11.2 The Shunt-Peaked Amplifier 1194 18.4.5 Small-Signal Limitations 1262
17.11.3 Single-Tuned Amplifier 1197 13.5 Single-Pole Operational Amplifier
17.11.4 UseofaTappedlnductor-The Compensation 1262
Auto Transformer 1199 185.1 Three-Stage Op Amp Analysis 1263
17.11.5 Multiple Tuned 1852 Transmission Zeros in FET Op
Circuits-Synchronous and Amps 1265
Stagger Tuning 1201 -I8.5.3 Bipolar Amplifier
17.11.6 Common-Source Amplifier with Compensation 1266
Inductive Degeneration 1202 18.54 Slew Rate of the Operational
17.12 Mixers and Balanced Modulators 1205 Amplifier 1266
17.12.1 Introduction to Mixer -I8.5.5 Relationships Between Slew Rate
Operation 1205 and Gain-Bandwidth Product 1268
17.12.2 A Single-Balanced Mixer 1206 i8.6 High-Frequency Oscillators 1277
17.12.3 The Differential Pair as a 18.6.1 The Colpitts Oscillator 1278
Single-Balanced Mixer 1207 18.6.2 The Hartley Oscillator 1279
17.12.4 A Double-Balanced Mixer 1208 1S.6.3 Amplitude Stabilization in LC
17.12.5 The Gilbert Multiplier as a Oscillators 1280
Double-Balanced 1S.6.4 Negative Resistance in
Mixer/Modulator 1210 Oscillators 1280
Contents XIX
18.6.5 Negative GM Oscillator 1281 APPENDIXES
18.6.6 Crystal Oscillators 1283 A standard Discrete Component Values 1300
Summary 1287 B Solid.state Device Models and SP|CE
Key Terms 1289 Simulation Parameters 1303
References 1289 c Two.Port Review 1310
Problems 1289
Index 1313
|
| any_adam_object | 1 |
| author | Jaeger, Richard C. Blalock, Travis N. |
| author_facet | Jaeger, Richard C. Blalock, Travis N. |
| author_role | aut aut |
| author_sort | Jaeger, Richard C. |
| author_variant | r c j rc rcj t n b tn tnb |
| building | Verbundindex |
| bvnumber | BV036433590 |
| classification_rvk | ZN 4900 ZN 4904 |
| ctrlnum | (OCoLC)695029894 (DE-599)BVBBV036433590 |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 4. ed., internat. student ed. |
| format | Book |
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| id | DE-604.BV036433590 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T22:39:18Z |
| institution | BVB |
| isbn | 9780071221993 0071221999 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-020306111 |
| oclc_num | 695029894 |
| open_access_boolean | |
| owner | DE-1043 DE-1102 DE-859 DE-83 |
| owner_facet | DE-1043 DE-1102 DE-859 DE-83 |
| physical | XXVI, 1334 S. Ill., graph. Darst. |
| publishDate | 2011 |
| publishDateSearch | 2011 |
| publishDateSort | 2011 |
| publisher | McGraw-Hill |
| record_format | marc |
| spelling | Jaeger, Richard C. Verfasser aut Microelectronic circuit design Richard C. Jaeger ; Travis N. Blalock 4. ed., internat. student ed. New York, NY McGraw-Hill 2011 XXVI, 1334 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Elektronische Schaltung (DE-588)4113419-9 gnd rswk-swf Mikroelektronik (DE-588)4039207-7 gnd rswk-swf Elektronische Schaltung (DE-588)4113419-9 s DE-604 Logische Schaltung (DE-588)4131023-8 s Entwurf (DE-588)4121208-3 s Mikroelektronik (DE-588)4039207-7 s 1\p DE-604 Blalock, Travis N. Verfasser aut HBZ Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=020306111&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Jaeger, Richard C. Blalock, Travis N. Microelectronic circuit design Logische Schaltung (DE-588)4131023-8 gnd Entwurf (DE-588)4121208-3 gnd Elektronische Schaltung (DE-588)4113419-9 gnd Mikroelektronik (DE-588)4039207-7 gnd |
| subject_GND | (DE-588)4131023-8 (DE-588)4121208-3 (DE-588)4113419-9 (DE-588)4039207-7 |
| title | Microelectronic circuit design |
| title_auth | Microelectronic circuit design |
| title_exact_search | Microelectronic circuit design |
| title_full | Microelectronic circuit design Richard C. Jaeger ; Travis N. Blalock |
| title_fullStr | Microelectronic circuit design Richard C. Jaeger ; Travis N. Blalock |
| title_full_unstemmed | Microelectronic circuit design Richard C. Jaeger ; Travis N. Blalock |
| title_short | Microelectronic circuit design |
| title_sort | microelectronic circuit design |
| topic | Logische Schaltung (DE-588)4131023-8 gnd Entwurf (DE-588)4121208-3 gnd Elektronische Schaltung (DE-588)4113419-9 gnd Mikroelektronik (DE-588)4039207-7 gnd |
| topic_facet | Logische Schaltung Entwurf Elektronische Schaltung Mikroelektronik |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=020306111&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT jaegerrichardc microelectroniccircuitdesign AT blalocktravisn microelectroniccircuitdesign |