Verfügbarkeit: ESL models and their application

ESL models and their application: electronic system level design and verification in practice

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Bailey, Brian (VerfasserIn), Martin, Grant (VerfasserIn)
Format:	Buch
Sprache:	English
Veröffentlicht:	New York [u.a.] Springer 2010
Schlagworte:	Embedded computer systems > Design and construction Embedded computer systems > Industrial applications
Online-Zugang:	Inhaltsverzeichnis
Beschreibung:	XXIV, 446 S. graph. Darst. 260 mm x 193 mm
ISBN:	9781441909640

Internformat

MARC


LEADER	00000nam a2200000 c 4500
001	BV036105446
003	DE-604
005	20230126
007	t
008	100331s2010 d\|\|\| \|\|\|\| 00\|\|\| eng d
015			\|a 09,N23,2062 \|2 dnb
016	7		\|a 994283679 \|2 DE-101
020			\|a 9781441909640 \|c GB. : ca. EUR 85.55 (freier Pr.), ca. sfr 102.50 (freier Pr.) \|9 978-1-441-90964-0
024	3		\|a 9781441909640
028	5	2	\|a 12575251
035			\|a (OCoLC)730259396
035			\|a (DE-599)DNB994283679
040			\|a DE-604 \|b ger \|e rakddb
041	0		\|a eng
049			\|a DE-91
050		0	\|a TK7895.E42
082	0		\|a 621.3815 \|2 22
084			\|a ST 153 \|0 (DE-625)143597: \|2 rvk
084			\|a 004 \|2 sdnb
084			\|a 620 \|2 sdnb
084			\|a DAT 130f \|2 stub
100	1		\|a Bailey, Brian \|e Verfasser \|4 aut
245	1	0	\|a ESL models and their application \|b electronic system level design and verification in practice \|c Brian Bailey ; Grant Martin
264		1	\|a New York [u.a.] \|b Springer \|c 2010
300			\|a XXIV, 446 S. \|b graph. Darst. \|c 260 mm x 193 mm
336			\|b txt \|2 rdacontent
337			\|b n \|2 rdamedia
338			\|b nc \|2 rdacarrier
650		4	\|a Embedded computer systems \|x Design and construction
650		4	\|a Embedded computer systems \|x Industrial applications
700	1		\|a Martin, Grant \|e Verfasser \|4 aut
856	4	2	\|m SWB Datenaustausch \|q application/pdf \|u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018995722&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA \|3 Inhaltsverzeichnis
999			\|a oai:aleph.bib-bvb.de:BVB01-018995722

Datensatz im Suchindex

_version_	1804141177279086592
adam_text	IMAGE 1 CONTENTS 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 A DEFINITION OF A MODEL . . . . . . . . . . . . . . . . . . . . . . 1 1.2 A DAY IN THE LIFE OF A MODEL . . . . . . . . . . . . . . . . . . . 2 1.3 TYPES OF MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 MODELS OF COMPUTATION . . . . . . . . . . . . . . . . . . . . . . 8 1.5 SIMPLIF ICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5.1 ABSTRACTION . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5.2 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.6 MODELS AND LANGUAGES . . . . . . . . . . . . . . . . . . . . . . 12 1.6.1 IMPERATIVE LANGUAGES . . . . . . . . . . . . . . . . . . . 12 1.6.2 DECLARATIVE LANGUAGES . . . . . . . . . . . . . . . . . . . 13 1.6.3 FUNCTIONAL . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6.4 NON-FUNCTIONAL . . . . . . . . . . . . . . . . . . . . . . . 15 1.6.5 META . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.6.6 TESTBENCH . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.7 THE DESIRE FOR A NEW LANGUAGE . . . . . . . . . . . . . . . . . . 18 1.8 BIG SHOES TO FILL . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.8.1 PTOLEMY SIMULATOR . . . . . . . . . . . . . . . . . . . . . 20 1.8.2 SYSTEMC . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.8.3 FUNCTION AND INTERFACE . . . . . . . . . . . . . . . . . . . 22 1.9 TAXONOMY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.9.1 THREE NEW AXES . . . . . . . . . . . . . . . . . . . . . . 23 1.9.2 APPLICATION TO MODELS AND LANGUAGES . . . . . . . . . . 25 1.9.3 TRANSFORMATION OF MODELS . . . . . . . . . . . . . . . . . 27 1.10 DEF INITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2 IP META-MODELS FOR SOC ASSEMBLY AND HW/SW INTERFACES . . . . 33 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2 IP DATABASES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3 SPIRIT/IP-XACT . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.3.1 HISTORY OF SPIRIT . . . . . . . . . . . . . . . . . . . . . 34 2.3.2 RTL ASSEMBLY LEVEL . . . . . . . . . . . . . . . . . . . 37 XV IMAGE 2 XVI CONTENTS 2.3.3 SYSTEM MODELING LEVEL . . . . . . . . . . . . . . . . . . 41 2.4 REGISTER DEFINITION LANGUAGES . . . . . . . . . . . . . . . . . . . 41 2.4.1 MOTIVATION: MODELING THE HW/SW INTERFACE . . . . . . . 42 2.4.2 HW/SW DESIGN FLOW FOR HW/SW INTERFACES . . . . . . . 56 2.4.3 EMERGING HW/SW INTERFACE TOOLS AND DESIGN FLOWS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.5 CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3 FUNCTIONAL MODELS . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.1 DYNAMIC MODELS AND LANGUAGES . . . . . . . . . . . . . . . . . 84 3.1.1 ALGORITHMIC LANGUAGES . . . . . . . . . . . . . . . . . . 84 3.1.2 ARCHITECTURAL MODELING LANGUAGES: SYSTEMC . . . . . . . 91 3.1.3 ARCHITECTURAL MODELS . . . . . . . . . . . . . . . . . . . 134 3.2 FORMAL MODELS . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 3.2.1 PROPERTY LANGUAGES . . . . . . . . . . . . . . . . . . . . 137 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 4 TESTBENCH MODELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.1 TESTBENCH BASICS . . . . . . . . . . . . . . . . . . . . . . . . . . 144 4.1.1 TESTBENCH COMPONENTS . . . . . . . . . . . . . . . . . . 146 4.1.2 VERIFICATION METHODOLOGIES . . . . . . . . . . . . . . . . 149 4.1.3 VERIF ICATION IP . . . . . . . . . . . . . . . . . . . . . . . 152 4.2 VERIF ICATION PLAN . . . . . . . . . . . . . . . . . . . . . . . . . . 152 4.3 COMPARISON MODEL . . . . . . . . . . . . . . . . . . . . . . . . . 157 4.3.1 TESTBENCH LANGUAGES . . . . . . . . . . . . . . . . . . . 158 4.4 PROGRESS MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . 161 4.4.1 AD HOC METRICS . . . . . . . . . . . . . . . . . . . . . . 161 4.4.2 STRUCTURAL METRICS . . . . . . . . . . . . . . . . . . . . . 161 4.4.3 FUNCTIONAL METRICS . . . . . . . . . . . . . . . . . . . . . 162 4.4.4 COVERAGE METRICS IN SYSTEMC . . . . . . . . . . . . . . . 162 4.4.5 COVERAGE METRICS IN SYSTEMVERILOG . . . . . . . . . . . . 165 4.5 INPUT CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . 166 4.6 VERIF ICATION IP . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 4.6.1 VIP COMPONENTS . . . . . . . . . . . . . . . . . . . . . . 169 4.6.2 VIP STANDARDIZATION . . . . . . . . . . . . . . . . . . . . 170 4.7 CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5 VIRTUAL PROTOTYPES AND MIXED ABSTRACTION MODELING . . . . . . . . 173 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 5.1.1 HISTORICAL PERSPECTIVE . . . . . . . . . . . . . . . . . . . 176 5.1.2 USE MODELS . . . . . . . . . . . . . . . . . . . . . . . . 179 5.1.3 TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . 183 5.1.4 INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . 187 5.1.5 PROCESSOR MODELS . . . . . . . . . . . . . . . . . . . . . 188 IMAGE 3 CONTENTS XVII 5.2 SYSTEM PROTOTYPES . . . . . . . . . . . . . . . . . . . . . . . . . 191 5.2.1 DEVELOPMENT ENVIRONMENTS FOR SOFTWARE DEVELOPMENT . . . . . . . . . . . . . . . . . . . . . . . . 191 5.2.2 HYBRID HARDWARE-SOFTWARE-BASED DEVELOPMENT PLATFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . 193 5.2.3 HYBRID SYSTEM PROTOTYPING USE MODELS . . . . . . . . . 194 5.3 CONSTRUCTING A SYSTEM-LEVEL VIRTUAL PROTOTYPE . . . . . . . . . . 195 5.3.1 MODELING LANGUAGES . . . . . . . . . . . . . . . . . . . . 196 5.3.2 MODEL CREATION . . . . . . . . . . . . . . . . . . . . . . 200 5.3.3 MODEL IMPORT . . . . . . . . . . . . . . . . . . . . . . . 201 5.3.4 MODEL LIBRARIES . . . . . . . . . . . . . . . . . . . . . . 201 5.3.5 VIRTUAL DEVICES . . . . . . . . . . . . . . . . . . . . . . . 202 5.3.6 MODELING THE ENVIRONMENT . . . . . . . . . . . . . . . . 204 5.3.7 TYING IT ALL TOGETHER . . . . . . . . . . . . . . . . . . . . 205 5.3.8 DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . 205 5.4 RUNNING THE PROTOTYPE . . . . . . . . . . . . . . . . . . . . . . . 206 5.4.1 DEBUG . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 5.4.2 ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . 208 5.5 VERIF ICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 5.5.1 PLATFORM DEPLOYMENT . . . . . . . . . . . . . . . . . . . 214 5.5.2 VERIFICATION METHODOLOGY MANUAL . . . . . . . . . . . . . 215 5.5.3 BUILDING THE RTL TESTBENCH . . . . . . . . . . . . . . . . 216 5.5.4 REGRESSIONS . . . . . . . . . . . . . . . . . . . . . . . . 217 5.6 EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.6.1 THE APPLICATION . . . . . . . . . . . . . . . . . . . . . . 219 5.6.2 THE BOTTOM LINE . . . . . . . . . . . . . . . . . . . . . . 222 5.7 THE FUTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 6 PROCESSOR-CENTRIC DESIGN: PROCESSORS, MULTI-PROCESSORS, AND SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 6.1 CHOICES AND TRADE-OFFS IN PROCESSOR-CENTRIC DESIGN . . . . . . . 225 6.2 AN ASIP INTEGRATED DEVELOPMENT ENVIRONMENT (IDE) . . . . . . 229 6.3 INTRODUCTION TO FLOW AND EXAMPLE . . . . . . . . . . . . . . . . 232 6.4 STARTING WITH ALGORITHMS . . . . . . . . . . . . . . . . . . . . . 234 6.5 PROCESSOR DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . 234 6.5.1 DESIGNING THE DESIGN SPACE EXPLORATION . . . . . . . . . 234 6.5.2 EXPLORING THE PROCESSOR DESIGN SPACE: PRECONFIGURED CORES . . . . . . . . . . . . . . . . . . . . 236 6.5.3 EXPLORING THE PROCESSOR DESIGN SPACE: AUTOMATICALLY . . 240 6.5.4 EXPLORING THE PROCESSOR DESIGN SPACE: CACHE AND MEMORY . . . . . . . . . . . . . . . . . . . . . . . . 248 6.5.5 EXPLORING THE PROCESSOR DESIGN SPACE: FINE-TUNING . . . 249 6.5.6 SPEED-AREA-POWER TRADE-OFFS . . . . . . . . . . . . . . 252 6.5.7 DETAILED ENERGY SPACE EXPLORATION . . . . . . . . . . . . 255 IMAGE 4 XVIII CONTENTS 6.6 SOFTWARE IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . 256 6.7 PREDICTING SOFTWARE PERFORMANCE VIA SAMPLING . . . . . . . . . . 258 6.8 MULTICORE ISSUES . . . . . . . . . . . . . . . . . . . . . . . . . . 261 6.8.1 A PRACTICAL METHODOLOGY FOR MULTI-PROCESSOR ASIP DEFINITION AND PROGRAMMING . . . . . . . . . . . . 262 6.8.2 DEVELOPING MULTICORE SYSTEM-LEVEL MODELS . . . . . . . 265 6.8.3 PORTING METHODOLOGY FOR NEW VIDEO CODECS TO THE MULTICORE SYSTEM . . . . . . . . . . . . . . . . . . 265 6.8.4 USING THE IDE FOR MULTICORE SIMULATION AND VALIDATION . . . . . . . . . . . . . . . . . . . . . . . 267 6.9 DEBUG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 6.9.1 SINGLE-CORE DEBUG IN THE IDE . . . . . . . . . . . . . . . 268 6.9.2 MULTI-PROCESSOR DEBUG IN THE IDE . . . . . . . . . . . . . 268 6.10 CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 7 CODESIGN EXPERIENCES BASED ON A VIRTUAL PLATFORM . . . . . . . . . 273 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 7.2 VIRTUAL PLATFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . 274 7.2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . 274 7.2.2 EVOLUTION OF PLATFORM COMPLEXITY . . . . . . . . . . . . . 274 7.2.3 METHODOLOGIES . . . . . . . . . . . . . . . . . . . . . . . 275 7.2.4 COMMERCIAL TECHNOLOGIES FOR VIRTUAL PLATFORM DEVELOPMENT . . . . . . . . . . . . . . . . . . . . . . . . 277 7.2.5 MODELS OF COMPUTATION . . . . . . . . . . . . . . . . . . 280 7.3 PLATFORM AND APPLICATION DESCRIPTION . . . . . . . . . . . . . . . 281 7.3.1 SYSTEM SPECIFICATION AND FUNCTIONAL VERIFICATION . . . . . 282 7.3.2 ARCHITECTURAL EXPLORATION . . . . . . . . . . . . . . . . . 284 7.3.3 ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . 292 7.3.4 INTEGRATION . . . . . . . . . . . . . . . . . . . . . . . . . 297 7.4 EXPERIMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 7.4.1 PIPELINED VS. NON-PIPELINED MODELS . . . . . . . . . . . . 300 7.4.2 ARCHITECTURAL EXPLORATION OF THE JPEG DECODER . . . . . . 302 7.5 CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 8 TRANSACTION-LEVEL PLATFORM CREATION . . . . . . . . . . . . . . . . . 309 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 8.2 TRANSACTION-LEVEL MODELING COMES OF AGE . . . . . . . . . . . . 311 8.3 MODEL ABSTRACTIONS . . . . . . . . . . . . . . . . . . . . . . . . 312 8.3.1 TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . 312 8.3.2 MODEL TAXONOMY . . . . . . . . . . . . . . . . . . . . . 313 8.4 ROLES OF THE TLM PLATFORM . . . . . . . . . . . . . . . . . . . . 315 8.5 CONTEXTUAL VERIF ICATION . . . . . . . . . . . . . . . . . . . . . . 317 8.6 CREATING MODELS . . . . . . . . . . . . . . . . . . . . . . . . . . 319 8.6.1 MODEL REFINEMENT . . . . . . . . . . . . . . . . . . . . . 320 IMAGE 5 CONTENTS XIX 8.6.2 MULTI-ABSTRACTION . . . . . . . . . . . . . . . . . . . . . . 323 8.6.3 VERIF ICATION . . . . . . . . . . . . . . . . . . . . . . . . . 325 8.7 TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 8.7.1 TIMING POLICIES . . . . . . . . . . . . . . . . . . . . . . 335 8.7.2 DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 8.7.3 SPLIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 8.7.4 SEQUENTIAL . . . . . . . . . . . . . . . . . . . . . . . . . 337 8.7.5 PIPELINING . . . . . . . . . . . . . . . . . . . . . . . . . 338 8.7.6 PUTTING IT ALL TOGETHER . . . . . . . . . . . . . . . . . . . 339 8.7.7 TIMING CALLBACKS . . . . . . . . . . . . . . . . . . . . . 341 8.8 POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 8.9 CREATING A MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . 342 8.9.1 USING MODEL BUILDER . . . . . . . . . . . . . . . . . . . . 342 8.9.2 SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . 345 8.9.3 INTEGRATING 3RD PARTY MODELS . . . . . . . . . . . . . . . 346 8.9.4 MODEL ABSTRACTION . . . . . . . . . . . . . . . . . . . . . 346 8.9.5 BUILDING A SYSTEM . . . . . . . . . . . . . . . . . . . . . 346 8.9.6 NAVIGATING A SYSTEM . . . . . . . . . . . . . . . . . . . . 347 8.10 EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 8.10.1 BUILDING THE SYSTEM . . . . . . . . . . . . . . . . . . . . 350 8.10.2 RUNNING THE SIMULATION . . . . . . . . . . . . . . . . . . 351 8.10.3 ANALYZING THE SYSTEM . . . . . . . . . . . . . . . . . . . 354 8.10.4 INSERTING AN ISS MODEL . . . . . . . . . . . . . . . . . . 356 8.11 CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 9 C/C++ HARDWARE DESIGN FOR THE REAL WORLD . . . . . . . . . . . . . 361 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 9.1.1 CHAPTER OVERVIEW . . . . . . . . . . . . . . . . . . . . . 362 9.2 WHERE DOES IT FIT IN AN ESL FLOW . . . . . . . . . . . . . . . . . 363 9.2.1 HARDWARE IMPLEMENTATION INPUT . . . . . . . . . . . . . . 365 9.2.2 HIGH-LEVEL SYNTHESIS OUTPUT . . . . . . . . . . . . . . . 367 9.2.3 VERIFICATION MODELS . . . . . . . . . . . . . . . . . . . . 368 9.2.4 OTHER USES FOR THE INPUT MODEL . . . . . . . . . . . . . . 369 9.3 WHY C/C++/SYSTEMC . . . . . . . . . . . . . . . . . . . . . . . 369 9.3.1 LANGUAGE LIMITATIONS FOR SYNTHESIS . . . . . . . . . . . . 372 9.4 HIGH-LEVEL SYNTHESIS FUNDAMENTALS . . . . . . . . . . . . . . . 373 9.4.1 SCHEDULE AND ALLOCATION TRADE-OFFS . . . . . . . . . . . . 373 9.4.2 SYNTHESIS AT THE INTERFACE . . . . . . . . . . . . . . . . . 375 9.4.3 HIERARCHY . . . . . . . . . . . . . . . . . . . . . . . . . . 375 9.4.4 OTHER CONTROL . . . . . . . . . . . . . . . . . . . . . . . 376 9.4.5 TARGET LIBRARY . . . . . . . . . . . . . . . . . . . . . . . 378 9.4.6 DATA-TYPE LIBRARIES FOR SYNTHESIS . . . . . . . . . . . . . 378 9.4.7 SYNTHESIS TOOLS . . . . . . . . . . . . . . . . . . . . . . 382 9.5 SYNTHESIS DOMAINS . . . . . . . . . . . . . . . . . . . . . . . . . 385 IMAGE 6 XX CONTENTS 9.6 A SIMPLE EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . 385 9.6.1 EMBEDDED ARCHITECTURE . . . . . . . . . . . . . . . . . . 386 9.7 TYING IT INTO A VERIF ICATION FLOW . . . . . . . . . . . . . . . . . . 392 9.7.1 VERIF ICATION WITH SIMULATION . . . . . . . . . . . . . . . . 392 9.7.2 VERIFICATION WITH EQUIVALENCE CHECKING . . . . . . . . . . 394 9.7.3 VERIFICATION AGAINST ALGORITHMIC MODEL . . . . . . . . . 394 9.7.4 VERIFYING POWER . . . . . . . . . . . . . . . . . . . . . . 396 9.8 A MORE COMPLEX EXAMPLE . . . . . . . . . . . . . . . . . . . . 397 9.8.1 THE APPLICATION . . . . . . . . . . . . . . . . . . . . . . 398 9.8.2 THE FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . 399 9.8.3 DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 9.8.4 VERIF ICATION . . . . . . . . . . . . . . . . . . . . . . . . . 415 9.8.5 SYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . 417 9.8.6 RESULTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 9.8.7 RESULTS ANALYSIS . . . . . . . . . . . . . . . . . . . . . . 425 9.9 SUCCESSFUL ADOPTION . . . . . . . . . . . . . . . . . . . . . . . . 426 9.10 THE FUTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 9.11 SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 ACRONYMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
any_adam_object	1
author	Bailey, Brian Martin, Grant
author_facet	Bailey, Brian Martin, Grant
author_role	aut aut
author_sort	Bailey, Brian
author_variant	b b bb g m gm
building	Verbundindex
bvnumber	BV036105446
callnumber-first	T - Technology
callnumber-label	TK7895
callnumber-raw	TK7895.E42
callnumber-search	TK7895.E42
callnumber-sort	TK 47895 E42
callnumber-subject	TK - Electrical and Nuclear Engineering
classification_rvk	ST 153
classification_tum	DAT 130f
ctrlnum	(OCoLC)730259396 (DE-599)DNB994283679
dewey-full	621.3815
dewey-hundreds	600 - Technology (Applied sciences)
dewey-ones	621 - Applied physics
dewey-raw	621.3815
dewey-search	621.3815
dewey-sort	3621.3815
dewey-tens	620 - Engineering and allied operations
discipline	Maschinenbau / Maschinenwesen Informatik Elektrotechnik / Elektronik / Nachrichtentechnik
format	Book
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01594nam a2200421 c 4500</leader><controlfield tag="001">BV036105446</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20230126 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">100331s2010 d\|\|\| \|\|\|\| 00\|\|\| eng d</controlfield><datafield tag="015" ind1=" " ind2=" "><subfield code="a">09,N23,2062</subfield><subfield code="2">dnb</subfield></datafield><datafield tag="016" ind1="7" ind2=" "><subfield code="a">994283679</subfield><subfield code="2">DE-101</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781441909640</subfield><subfield code="c">GB. : ca. EUR 85.55 (freier Pr.), ca. sfr 102.50 (freier Pr.)</subfield><subfield code="9">978-1-441-90964-0</subfield></datafield><datafield tag="024" ind1="3" ind2=" "><subfield code="a">9781441909640</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">12575251</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)730259396</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)DNB994283679</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7895.E42</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">22</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 153</subfield><subfield code="0">(DE-625)143597:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">004</subfield><subfield code="2">sdnb</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">620</subfield><subfield code="2">sdnb</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 130f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Bailey, Brian</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">ESL models and their application</subfield><subfield code="b">electronic system level design and verification in practice</subfield><subfield code="c">Brian Bailey ; Grant Martin</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">New York [u.a.]</subfield><subfield code="b">Springer</subfield><subfield code="c">2010</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXIV, 446 S.</subfield><subfield code="b">graph. Darst.</subfield><subfield code="c">260 mm x 193 mm</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Embedded computer systems</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Embedded computer systems</subfield><subfield code="x">Industrial applications</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Martin, Grant</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">SWB Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018995722&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-018995722</subfield></datafield></record></collection>
id	DE-604.BV036105446
illustrated	Illustrated
indexdate	2024-07-09T22:11:43Z
institution	BVB
isbn	9781441909640
language	English
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-018995722
oclc_num	730259396
open_access_boolean
owner	DE-91 DE-BY-TUM
owner_facet	DE-91 DE-BY-TUM
physical	XXIV, 446 S. graph. Darst. 260 mm x 193 mm
publishDate	2010
publishDateSearch	2010
publishDateSort	2010
publisher	Springer
record_format	marc
spelling	Bailey, Brian Verfasser aut ESL models and their application electronic system level design and verification in practice Brian Bailey ; Grant Martin New York [u.a.] Springer 2010 XXIV, 446 S. graph. Darst. 260 mm x 193 mm txt rdacontent n rdamedia nc rdacarrier Embedded computer systems Design and construction Embedded computer systems Industrial applications Martin, Grant Verfasser aut SWB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018995722&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	Bailey, Brian Martin, Grant ESL models and their application electronic system level design and verification in practice Embedded computer systems Design and construction Embedded computer systems Industrial applications
title	ESL models and their application electronic system level design and verification in practice
title_auth	ESL models and their application electronic system level design and verification in practice
title_exact_search	ESL models and their application electronic system level design and verification in practice
title_full	ESL models and their application electronic system level design and verification in practice Brian Bailey ; Grant Martin
title_fullStr	ESL models and their application electronic system level design and verification in practice Brian Bailey ; Grant Martin
title_full_unstemmed	ESL models and their application electronic system level design and verification in practice Brian Bailey ; Grant Martin
title_short	ESL models and their application
title_sort	esl models and their application electronic system level design and verification in practice
title_sub	electronic system level design and verification in practice
topic	Embedded computer systems Design and construction Embedded computer systems Industrial applications
topic_facet	Embedded computer systems Design and construction Embedded computer systems Industrial applications
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018995722&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT baileybrian eslmodelsandtheirapplicationelectronicsystemleveldesignandverificationinpractice AT martingrant eslmodelsandtheirapplicationelectronicsystemleveldesignandverificationinpractice

Verfügbarkeit

Es ist kein Print-Exemplar vorhanden.

Fernleihe Bestellen Achtung: Nicht im THWS-Bestand! Inhaltsverzeichnis

MARC

Datensatz im Suchindex

Es ist kein Print-Exemplar vorhanden.

Ähnliche Einträge