Integrated circuit and system design: power and timing modeling, optimization and simulation ; 19th international workshop, PATMOS 2009, Delft, The Netherlands, September 9 - 11, 2009 ; revised selected papers
Gespeichert in:
| Format: | Tagungsbericht Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Berlin [u.a.]
Springer
2010
|
| Schriftenreihe: | Lecture notes in computer science
5953 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | Literaturangaben |
| Beschreibung: | XIII, 368 S. Ill., graph. Darst. 24 cm |
| ISBN: | 9783642118012 |
Internformat
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV036055050 | ||
| 003 | DE-604 | ||
| 005 | 20100611 | ||
| 007 | t| | ||
| 008 | 100301s2010 xx ad|| |||| 10||| eng d | ||
| 015 | |a 10,N06 |2 dnb | ||
| 016 | 7 | |a 1000035484 |2 DE-101 | |
| 020 | |a 9783642118012 |c kart. : EUR 57.78 (freier Pr.), sfr 84.00 (freier Pr.) |9 978-3-642-11801-2 | ||
| 024 | 3 | |a 9783642118012 | |
| 028 | 5 | 2 | |a 12844012 |
| 035 | |a (OCoLC)502033384 | ||
| 035 | |a (DE-599)DNB1000035484 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-706 |a DE-91G |a DE-11 |a DE-83 | ||
| 050 | 0 | |a TK7874.75 | |
| 082 | 0 | |a 621.395 |2 22/ger | |
| 084 | |a 004 |2 sdnb | ||
| 084 | |a 620 |2 sdnb | ||
| 084 | |a DAT 190f |2 stub | ||
| 245 | 1 | 0 | |a Integrated circuit and system design |b power and timing modeling, optimization and simulation ; 19th international workshop, PATMOS 2009, Delft, The Netherlands, September 9 - 11, 2009 ; revised selected papers |c José Monteiro ... (eds.) |
| 264 | 1 | |a Berlin [u.a.] |b Springer |c 2010 | |
| 300 | |a XIII, 368 S. |b Ill., graph. Darst. |c 24 cm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Lecture notes in computer science |v 5953 | |
| 500 | |a Literaturangaben | ||
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Computer-aided design |v Congresses | |
| 650 | 0 | 7 | |a Entwurfsautomation |0 (DE-588)4312536-0 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |y 2009 |z Delft |2 gnd-content | |
| 689 | 0 | 0 | |a Entwurfsautomation |0 (DE-588)4312536-0 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Monteiro, José |e Sonstige |4 oth | |
| 711 | 2 | |a PATMOS |n 19 |d 2009 |c Delft |j Sonstige |0 (DE-588)16057629-5 |4 oth | |
| 830 | 0 | |a Lecture notes in computer science |v 5953 |w (DE-604)BV000000607 |9 5953 | |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018946651&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-018946651 | |
Datensatz im Suchindex
| _version_ | 1820875201911455744 |
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| adam_text |
MONICA FIGUEIREDO AND RUI L. AGUIAR TABLE OF CONTENTS KEYNOTES ROBUST
LOW POWER EMBEDDED SRAM DESIGN: FROM SYSTEM TO MEMORY CELL 1 TOBY DOOM
AND ROELOF SALTERS VARIABILITY IN ADVANCED NANOMETER TECHNOLOGIES:
CHALLENGES AND SOLUTIONS 2 DAVIDE PANDINI SUBTHRESHOLD CIRCUIT DESIGN
FOR ULTRA-LOW-POWER APPLICATIONS 3 YUSUF LEBLEBICI SPECIAL SESSION
SYSTEMC AMS EXTENSIONS: NEW LANGUAGE - NEW METHODS - NEW APPLICATIONS 4
MARTIN BARNASCONI, MARKUS DAMM, AND KARSTEN EINWICH SESSION 1:
VARIABILITY & STATISTICAL TIMING PROCESS VARIATION AWARE PERFORMANCE
ANALYSIS OF ASYNCHRONOUS CIRCUITS CONSIDERING SPATIAL CORRELATION 5
MOHSEN RAJI, BEHNAM GHAVAMI, HAMID R. ZARANDI, AND HOSSEIN PEDRAM
INTERPRETING SSTA RESULTS WITH CORRELATION 16 ZEQIN WU, PHILIPPE
MAURINE, NADINE AZEMARD, AND GILLE DUCHARME RESIDUE ARITHMETIC FOR
VARIATION-TOLERANT DESIGN OF MULTIPLY-ADD UNITS 26 IOANNIS KOURETAS AND
VASSILIS PALIOURAS EXPONENT MONTE CARLO FOR QUICK STATISTICAL CIRCUIT
SIMULATION 36 PAUL ZUBER, VLADIMIR MATVEJEV, PHILIPPE ROUSSEL, PETR
DOBROVOLNY, AND MIGUEL MIRANDA POSTER SESSION 1: CIRCUIT LEVEL
TECHNIQUES CLOCK REPEATER CHARACTERIZATION FOR JITTER-AWARE CLOCK TREE
SYNTHESIS 46 BIBLIOGRAFISCHE INFORMATIONEN HTTP://D-NB.INFO/1000035484
DIGITALISIERT DURCH X TABLE OF CONTENTS A HARDWARE IMPLEMENTATION OF THE
USER-CENTRIC DISPLAY ENERGY MANAGEMENT 56 VASILY G. MOSHNYAGA, KOJI
HASHIMOTO, TADASHI SUETSUGU, AND SHUHEI HIGASHI ON-CHIP THERMAL MODELING
BASED ON SPICE SIMULATION 66 WEI LIU, ANDREA CALIMERA, ALBERTO
NANNARELLI, ENRICO MACII, AND MASSIMO PONCINO SWITCHING NOISE
OPTIMIZATION IN THE WAKE-UP PHASE OF LEAKAGE-AWARE POWER GATING
STRUCTURES 76 JAVIER CASTRO, PILAR PARRA, AND ANTONIO J. ACOSTA SESSION
2: POWER MANAGEMENT APPLICATION-SPECIFIC TEMPERATURE REDUCTION
SYSTEMATIC METHODOLOGY FOR 2D AND 3D NETWORKS-ON-CHIP 86 IRAKLIS
ANAGNOSTOPOULOS, ALEXANDROS BARTZAS, AND DIMITRIOS SOUDRIS DATA-DRIVEN
CLOCK GATING FOR DIGITAL FILTERS 96 ALBERTO BONANNO, ALBERTO BOCEA,
ALBERTO MACII, ENRICO MACII, AND MASSIMO PONCINO POWER MANAGEMENT AND
ITS IMPACT ON POWER SUPPLY NOISE 106 HOWARD CHEN AND INDIRA NAIR
ASSERTIVE DYNAMIC POWER MANAGEMENT (ASDPM) STRATEGY FOR GLOBALLY
SCHEDULED RT MULTIPROCESSOR SYSTEMS 116 MUHAMMAD KHURRAM BHATTI,
MUHAMMAD FAROOQ, CECILE BELLEUDY, MICHEL AUGUIN, AND ONS MBAREK SESSION
3: LOW POWER CIRCUITS & TECHNOLOGY DESIGN OPTIMIZATION OF LOW-POWER 90NM
CMOS SOC APPLICATION USING 0.5V BULK PMOS DYNAMIC-THRESHOLD WITH DUAL
THRESHOLD (MTCMOS): BP-DTMOS-DT TECHNIQUE 127 CHIH-HSIANG TABLE OF
CONTENTS XI POSTER SESSION 2: SYSTEM LEVEL TECHNIQUES MULTI-GRANULARITY
NOC SIMULATION FRAMEWORK FOR EARLY PHASE EXPLORATION OF SDR HARDWARE
PLATFORMS 165 NIKOLAOS ZOMPAKIS, MARTIN TRAUTMANN, ALEXANDRAS BARTZAS,
STYLIANOS MAMAGKAKIS, DIMITRIOS SOUDRIS, LIESBET VAN DER PERRE, AND
FRANCKY CATTHOOR DYNAMIC DATA TYPE OPTIMIZATION AND MEMORY ASSIGNMENT
METHODOLOGIES 175 ALEXANDROS BARTZAS, CHRISTOS BALOUKAS, DIMITRIOS
SOUDRIS, KONSTANTINOS POTAMIANOS, FRAGKISKOS IEROMNIMON, AND NIKOLAOS S.
VOWS ACCELERATING EMBEDDED SOFTWARE POWER PROFILING USING RUN-TIME POWER
EMULATION 186 CHRISTIAN BACHMANN, ANDREAS GENSER, CHRISTIAN STEGER,
REINHOLD WEISS, AND JOSEF HAID WRITE INVALIDATION ANALYSIS IN CHIP
MULTIPROCESSORS 196 NEWSHA ARDALANI AND AMIRALI BANIASADI PRACTICAL
DESIGN SPACE EXPLORATION OF AN H264 DECODER FOR HANDHELD DEVICES USING A
VIRTUAL PLATFORM 206 MARIUS GLIGOR, NICOLAS FOURNEL, FREDERIC PETROT,
FABIEN COLAS-BIGEY, ANNE-MARIE FOUILLIART, PHILIPPE TENINGE, AND
MARCELLO COPPOLA BSAA: A SWITCHING ACTIVITY ANALYSIS AND VISUALISATION
TOOL FOR SOC POWER OPTIMISATION 216 TOM ENGLISH, KA LOK MAN, AND EMANUEL
POPOVICI SESSION 4: POWER & TIMING OPTIMIZATION TECHNIQUES REDUCING
TIMING OVERHEAD IN SIMULTANEOUSLY CLOCK-GATED AND POWER-GATED DESIGNS BY
PLACEMENT-AWARE CLUSTERING 227 GAURANG XII TABLE OF CONTENTS SESSION 5:
SELF-TIMED CIRCUITS LOW-POWER SOFT ERROR HARDENED LATCH 256 HOSSEIN
KARIMIYAN ALIDASH AND VOJIN G. OKLOBDZIJA DIGITAL TIMING SLACK MONITORS
AND THEIR SPECIFIC INSERTION FLOW FOR ADAPTIVE COMPENSATION OF
VARIABILITIES 266 BETTINA REBAUD, MARC BELLEVILLE, EDITH BEIGNE,
CHRISTIAN BERNARD, MICHEL ROBERT, PHILIPPE MAURINE, AND NADINE AZEMARD
QUASI-DELAY-INSENSITIVE COMPUTING DEVICE: METHODOLOGICAL ASPECTS AND
PRACTICAL IMPLEMENTATION 276 YURI STEPCHENKOV, YURI DIACHENKO, VICTOR
ZAKHAROV, YURI ROGDESTVENSKI, NIKOLAI MOROZOV, AND DMITRI STEPCHENKOV
THE MAGIC RULE OF TILES: VIRTUAL DELAY INSENSITIVITY 286 DELONG SHANG,
FEI XIA, STANISLAVS GOLUBCOVS, AND ALEX YAKOVLEV SESSION 6: LOW POWER
CIRCUIT ANALYSIS & OPTIMIZATION ANALYSIS OF POWER CONSUMPTION USING A
NEW METHODOLOGY FOR THE CAPACITANCE MODELING OF COMPLEX LOGIC GATES 297
SIDINEI GHISSONI, JOAO BATISTA DOS SANTOS MARTINS, RICARDO AUGUSTO DA
LUZ REIS, AND JOSE CARLOS MONTEIRO A NEW METHODOLOGY FOR POWER-AWARE
TRANSISTOR SIZING: FREE POWER RECOVERY (FPR) 307 MILENA VRATONJIC,
MATTHEW ZIEGLER, GEORGE D. GRISTEDE, VICTOR ZYUBAN, THOMAS MITCHELL, EE
CHO, CHANDU VISWESWARIAH, AND VOJIN G. OKLOBDZIJA ROUTING RESISTANCE
INFLUENCE IN LOADING EFFECT ON LEAKAGE ANALYSIS . 317 PAULO F.
BUTZEN, ANDRE I. REIS, AND RENATO P. RIBAS SESSIO TABLE OF CONTENTS XIII
ENERGY DISSIPATION REDUCTION OF A CARDIAC EVENT DETECTOR IN THE SUB-V T
DOMAIN BY ARCHITECTURAL FOLDING 347 JOACHIM NEVES RODRIGUES, ORNER CAN
AKGUN, PUNEET ACHARYA, ADOLFO DE LA CALLE, YUSUF LEBLEBICI, AND VIKTOR
OWALL A NEW OPTIMIZED HIGH-SPEED LOW-POWER DATA-DRIVEN DYNAMIC (D3L)
32-BIT KOGGE-STONE ADDER 357 FABIO FRUSTACI AND MARCO LANUZZA AUTHOR
INDEX 367 |
| any_adam_object | 1 |
| building | Verbundindex |
| bvnumber | BV036055050 |
| callnumber-first | T - Technology |
| callnumber-label | TK7874 |
| callnumber-raw | TK7874.75 |
| callnumber-search | TK7874.75 |
| callnumber-sort | TK 47874.75 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | SS 4800 |
| classification_tum | DAT 190f |
| ctrlnum | (OCoLC)502033384 (DE-599)DNB1000035484 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Maschinenbau / Maschinenwesen Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Conference Proceeding Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00000nam a2200000 cb4500</leader><controlfield tag="001">BV036055050</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20100611</controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">100301s2010 xx ad|| |||| 10||| eng d</controlfield><datafield tag="015" ind1=" " ind2=" "><subfield code="a">10,N06</subfield><subfield code="2">dnb</subfield></datafield><datafield tag="016" ind1="7" ind2=" "><subfield code="a">1000035484</subfield><subfield code="2">DE-101</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9783642118012</subfield><subfield code="c">kart. : EUR 57.78 (freier Pr.), sfr 84.00 (freier Pr.)</subfield><subfield code="9">978-3-642-11801-2</subfield></datafield><datafield tag="024" ind1="3" ind2=" "><subfield code="a">9783642118012</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">12844012</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)502033384</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)DNB1000035484</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-706</subfield><subfield code="a">DE-91G</subfield><subfield code="a">DE-11</subfield><subfield code="a">DE-83</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7874.75</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.395</subfield><subfield code="2">22/ger</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">004</subfield><subfield code="2">sdnb</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">620</subfield><subfield code="2">sdnb</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 190f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Integrated circuit and system design</subfield><subfield code="b">power and timing modeling, optimization and simulation ; 19th international workshop, PATMOS 2009, Delft, The Netherlands, September 9 - 11, 2009 ; revised selected papers</subfield><subfield code="c">José Monteiro ... (eds.)</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Berlin [u.a.]</subfield><subfield code="b">Springer</subfield><subfield code="c">2010</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XIII, 368 S.</subfield><subfield code="b">Ill., graph. Darst.</subfield><subfield code="c">24 cm</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Lecture notes in computer science</subfield><subfield code="v">5953</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Literaturangaben</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Computer-aided design</subfield><subfield code="v">Congresses</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurfsautomation</subfield><subfield code="0">(DE-588)4312536-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)1071861417</subfield><subfield code="a">Konferenzschrift</subfield><subfield code="y">2009</subfield><subfield code="z">Delft</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Entwurfsautomation</subfield><subfield code="0">(DE-588)4312536-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Monteiro, José</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="711" ind1="2" ind2=" "><subfield code="a">PATMOS</subfield><subfield code="n">19</subfield><subfield code="d">2009</subfield><subfield code="c">Delft</subfield><subfield code="j">Sonstige</subfield><subfield code="0">(DE-588)16057629-5</subfield><subfield code="4">oth</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Lecture notes in computer science</subfield><subfield code="v">5953</subfield><subfield code="w">(DE-604)BV000000607</subfield><subfield code="9">5953</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">DNB Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018946651&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-018946651</subfield></datafield></record></collection> |
| genre | (DE-588)1071861417 Konferenzschrift 2009 Delft gnd-content |
| genre_facet | Konferenzschrift 2009 Delft |
| id | DE-604.BV036055050 |
| illustrated | Illustrated |
| indexdate | 2025-01-10T15:11:52Z |
| institution | BVB |
| institution_GND | (DE-588)16057629-5 |
| isbn | 9783642118012 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-018946651 |
| oclc_num | 502033384 |
| open_access_boolean | |
| owner | DE-706 DE-91G DE-BY-TUM DE-11 DE-83 |
| owner_facet | DE-706 DE-91G DE-BY-TUM DE-11 DE-83 |
| physical | XIII, 368 S. Ill., graph. Darst. 24 cm |
| publishDate | 2010 |
| publishDateSearch | 2010 |
| publishDateSort | 2010 |
| publisher | Springer |
| record_format | marc |
| series | Lecture notes in computer science |
| series2 | Lecture notes in computer science |
| spelling | Integrated circuit and system design power and timing modeling, optimization and simulation ; 19th international workshop, PATMOS 2009, Delft, The Netherlands, September 9 - 11, 2009 ; revised selected papers José Monteiro ... (eds.) Berlin [u.a.] Springer 2010 XIII, 368 S. Ill., graph. Darst. 24 cm txt rdacontent n rdamedia nc rdacarrier Lecture notes in computer science 5953 Literaturangaben Integrated circuits Very large scale integration Computer-aided design Congresses Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 2009 Delft gnd-content Entwurfsautomation (DE-588)4312536-0 s DE-604 Monteiro, José Sonstige oth PATMOS 19 2009 Delft Sonstige (DE-588)16057629-5 oth Lecture notes in computer science 5953 (DE-604)BV000000607 5953 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018946651&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Integrated circuit and system design power and timing modeling, optimization and simulation ; 19th international workshop, PATMOS 2009, Delft, The Netherlands, September 9 - 11, 2009 ; revised selected papers Lecture notes in computer science Integrated circuits Very large scale integration Computer-aided design Congresses Entwurfsautomation (DE-588)4312536-0 gnd |
| subject_GND | (DE-588)4312536-0 (DE-588)1071861417 |
| title | Integrated circuit and system design power and timing modeling, optimization and simulation ; 19th international workshop, PATMOS 2009, Delft, The Netherlands, September 9 - 11, 2009 ; revised selected papers |
| title_auth | Integrated circuit and system design power and timing modeling, optimization and simulation ; 19th international workshop, PATMOS 2009, Delft, The Netherlands, September 9 - 11, 2009 ; revised selected papers |
| title_exact_search | Integrated circuit and system design power and timing modeling, optimization and simulation ; 19th international workshop, PATMOS 2009, Delft, The Netherlands, September 9 - 11, 2009 ; revised selected papers |
| title_full | Integrated circuit and system design power and timing modeling, optimization and simulation ; 19th international workshop, PATMOS 2009, Delft, The Netherlands, September 9 - 11, 2009 ; revised selected papers José Monteiro ... (eds.) |
| title_fullStr | Integrated circuit and system design power and timing modeling, optimization and simulation ; 19th international workshop, PATMOS 2009, Delft, The Netherlands, September 9 - 11, 2009 ; revised selected papers José Monteiro ... (eds.) |
| title_full_unstemmed | Integrated circuit and system design power and timing modeling, optimization and simulation ; 19th international workshop, PATMOS 2009, Delft, The Netherlands, September 9 - 11, 2009 ; revised selected papers José Monteiro ... (eds.) |
| title_short | Integrated circuit and system design |
| title_sort | integrated circuit and system design power and timing modeling optimization and simulation 19th international workshop patmos 2009 delft the netherlands september 9 11 2009 revised selected papers |
| title_sub | power and timing modeling, optimization and simulation ; 19th international workshop, PATMOS 2009, Delft, The Netherlands, September 9 - 11, 2009 ; revised selected papers |
| topic | Integrated circuits Very large scale integration Computer-aided design Congresses Entwurfsautomation (DE-588)4312536-0 gnd |
| topic_facet | Integrated circuits Very large scale integration Computer-aided design Congresses Entwurfsautomation Konferenzschrift 2009 Delft |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018946651&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV000000607 |
| work_keys_str_mv | AT monteirojose integratedcircuitandsystemdesignpowerandtimingmodelingoptimizationandsimulation19thinternationalworkshoppatmos2009delftthenetherlandsseptember9112009revisedselectedpapers AT patmosdelft integratedcircuitandsystemdesignpowerandtimingmodelingoptimizationandsimulation19thinternationalworkshoppatmos2009delftthenetherlandsseptember9112009revisedselectedpapers |