Analysis and design of resilient VLSI circuits: Mitigating soft errors and process variations
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York u.a.
Springer
2010
|
| Schlagworte: | |
| Beschreibung: | XXII, 212 S. Ill., graph. Darst. 235 mm x 155 mm |
| ISBN: | 9781441909305 |
Internformat
MARC
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| 001 | BV035960973 | ||
| 003 | DE-604 | ||
| 005 | 20100209 | ||
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| 015 | |a 09,N23,2035 |2 dnb | ||
| 016 | 7 | |a 994283717 |2 DE-101 | |
| 020 | |a 9781441909305 |c GB. : ca. EUR 105.93 (freier Pr.), ca. sfr 165.00 (freier Pr.) |9 978-1-4419-0930-5 | ||
| 024 | 3 | |a 9781441909305 | |
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| 082 | 0 | |a 621.395 | |
| 084 | |a ELT 355f |2 stub | ||
| 084 | |a 620 |2 sdnb | ||
| 100 | 1 | |a Garg, Rajesh |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Analysis and design of resilient VLSI circuits |b Mitigating soft errors and process variations |c Rajesh Garg ; Sunil P. Khatri |
| 264 | 1 | |a New York u.a. |b Springer |c 2010 | |
| 300 | |a XXII, 212 S. |b Ill., graph. Darst. |c 235 mm x 155 mm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
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| 689 | 0 | 0 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
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| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Khatri, Sunil P. |e Verfasser |4 aut | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-018855138 | ||
Datensatz im Suchindex
| _version_ | 1804140979129679872 |
|---|---|
| any_adam_object | |
| author | Garg, Rajesh Khatri, Sunil P. |
| author_facet | Garg, Rajesh Khatri, Sunil P. |
| author_role | aut aut |
| author_sort | Garg, Rajesh |
| author_variant | r g rg s p k sp spk |
| building | Verbundindex |
| bvnumber | BV035960973 |
| classification_tum | ELT 355f |
| ctrlnum | (OCoLC)552137659 (DE-599)DNB994283717 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Maschinenbau / Maschinenwesen Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV035960973 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T22:08:34Z |
| institution | BVB |
| isbn | 9781441909305 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-018855138 |
| oclc_num | 552137659 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM |
| owner_facet | DE-91 DE-BY-TUM |
| physical | XXII, 212 S. Ill., graph. Darst. 235 mm x 155 mm |
| publishDate | 2010 |
| publishDateSearch | 2010 |
| publishDateSort | 2010 |
| publisher | Springer |
| record_format | marc |
| spelling | Garg, Rajesh Verfasser aut Analysis and design of resilient VLSI circuits Mitigating soft errors and process variations Rajesh Garg ; Sunil P. Khatri New York u.a. Springer 2010 XXII, 212 S. Ill., graph. Darst. 235 mm x 155 mm txt rdacontent n rdamedia nc rdacarrier Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 s VLSI (DE-588)4117388-0 s DE-604 Khatri, Sunil P. Verfasser aut |
| spellingShingle | Garg, Rajesh Khatri, Sunil P. Analysis and design of resilient VLSI circuits Mitigating soft errors and process variations Integrierte Schaltung (DE-588)4027242-4 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4027242-4 (DE-588)4117388-0 |
| title | Analysis and design of resilient VLSI circuits Mitigating soft errors and process variations |
| title_auth | Analysis and design of resilient VLSI circuits Mitigating soft errors and process variations |
| title_exact_search | Analysis and design of resilient VLSI circuits Mitigating soft errors and process variations |
| title_full | Analysis and design of resilient VLSI circuits Mitigating soft errors and process variations Rajesh Garg ; Sunil P. Khatri |
| title_fullStr | Analysis and design of resilient VLSI circuits Mitigating soft errors and process variations Rajesh Garg ; Sunil P. Khatri |
| title_full_unstemmed | Analysis and design of resilient VLSI circuits Mitigating soft errors and process variations Rajesh Garg ; Sunil P. Khatri |
| title_short | Analysis and design of resilient VLSI circuits |
| title_sort | analysis and design of resilient vlsi circuits mitigating soft errors and process variations |
| title_sub | Mitigating soft errors and process variations |
| topic | Integrierte Schaltung (DE-588)4027242-4 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Integrierte Schaltung VLSI |
| work_keys_str_mv | AT gargrajesh analysisanddesignofresilientvlsicircuitsmitigatingsofterrorsandprocessvariations AT khatrisunilp analysisanddesignofresilientvlsicircuitsmitigatingsofterrorsandprocessvariations |