Introduction to system-on-package (SOP): miniaturization of the entire system
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, NY [u.a.]
McGraw-Hill
2008
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis Inhaltsverzeichnis |
| Beschreibung: | Includes bibliographical references and index |
| Beschreibung: | XX, 785 S. Ill., graph. Darst. 25 cm |
| ISBN: | 0071459065 9780071459068 |
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| 245 | 1 | 0 | |a Introduction to system-on-package (SOP) |b miniaturization of the entire system |c Rao R. Tummala ; Madhavan Swaminathan |
| 264 | 1 | |a New York, NY [u.a.] |b McGraw-Hill |c 2008 | |
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| 500 | |a Includes bibliographical references and index | ||
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Datensatz im Suchindex
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| adam_text | INTRODUCTION TO SYSTEM-ON-PACKAGE (SOP) MINIATURIZATION OF THE ENTIRE
SYSTEM RAO R. TUMMALA MADHAVAN SWAMINATHAN NEW YORK CHICAGO SAN
FRANCISCO LISBON LONDON MADRID MEXICO CITY MILAN NEW DELHI SAN JUAN
SEOUL SINGAPORE SYDNEY TORONTO CONTENTS FOREWORD XVII PREFACE XIX 1
INTRODUCTION TO THE SYSTEM-ON-PACKAGE (SOP) TECHNOLOGY 3 1.1
INTRODUCTION 4 1.2 ELECTRONIC SYSTEM TREND TO DIGITAL CONVERGENCE 5 1.3
BUILDING BLOCKS OF AN ELECTRONIC SYSTEM 7 1.4 SYSTEM TECHNOLOGIES
EVOLUTION 8 1.5 FIVE MAJOR SYSTEM TECHNOLOGIES 11 1.5.1 SYSTEM-ON-BOARD
(SOB) TECHNOLOGY WITH DISCRETE COMPONENTS 11 1.5.2 SYSTEM-ON-CHIP (SOC)
WITH TWO OR MORE SYSTEM FUNCTIONS ON A SINGLE CHIP 11 1.5.3 MULTICHIP
MODULE (MCM): PACKAGE-ENABLED INTEGRATION OF TWO OR MORE CHIPS
INTERCONNECTED HORIZONTALLY 13 1.5.4 STACKED ICS AND PACKAGES (SIP):
PACKAGE-ENABLED IC INTEGRATION WITH TWO OR MORE CHIP STACKING (MOORE S
LAW IN THE THIRD DIMENSION) 13 1.6 SYSTEM-ON-PACKAGE TECHNOLOGY (MODULE
WITH THE BEST OF IC AND SYSTEM INTEGRATION) 18 1.6.1 MINIATURIZATION
TREND 22 1.7 COMPARISON OF THE FIVE SYSTEM TECHNOLOGIES 23 1.8 STATUS OF
SOP AROUND THE GLOBE 26 1.8.1 OPTO SOP 26 1.8.2 RF SOP 28 1.8.3 EMBEDDED
PASSIVES SOP 29 1.8.4 MEMS SOP 29 1.9 SOP TECHNOLOGY IMPLEMENTATIONS 29
1.10 SOP TECHNOLOGIES 33 1.11 SUMMARY 34 ACKNOWLEDGMENT 34 REFERENCES 34
2 INTRODUCTION TO SYSTEM-ON-CHIP (SOC) 39 2.1 INTRODUCTION 40 2.2 KEY
CUSTOMER REQUIREMENTS 42 2.3 SOC ARCHITECTURE 44 2.4 SOC DESIGN
CHALLENGE 50 2.4.1 SOC DESIGN PHASE 1*SOC DEFINITION AND CHALLENGES ...
50 2.4.2 SOC DESIGN PHASE II*SOC CREATE PROCESS AND CHALLENGES 57 IX
CONTENTS 2.5 SUMMARY 76 REFERENCES 76 3 STACKED ICS AND PACKAGES (SIP)
81 3.1 SIP DEFINITION 82 3.1.1 DEFINITION 82 3.1.2 APPLICATIONS 82 3.1.3
CEO FIGURE AND SIP CATEGORIES 82 3.2 SIP CHALLENGES 85 3.2.1 MATERIALS
AND PROCESS CHALLENGES 85 3.2.2 MECHANICAL CHALLENGES 87 3.2.3
ELECTRICAL CHALLENGES 88 3.2.4 THERMAL CHALLENGES 89 3.3 NON-TSV SIP 93
3.3.1 HISTORICAL EVOLUTION OF NON-TSV SIP 93 3.3.2 CHIP STACKING 96
3.3.3 PACKAGE STACKING 113 3.3.4 CHIP STACKING VERSUS PACKAGE STACKING
120 3.4 TSV SIP 121 3.4.1 INTRODUCTION 121 3.4.2 HISTORICAL EVOLUTION OF
3D TSV TECHNOLOGY 124 3.4.3 BASIC TSV TECHNOLOGIES 126 3.4.4 DIFFERENT
3D INTEGRATION TECHNOLOGIES USING TSV 134 3.4.5 SI CARRIER TECHNOLOGY
141 3.5 FUTURE TRENDS 143 ACKNOWLEDGMENTS 144 REFERENCES 144 4
MIXED-SIGNAL (SOP) DESIGN 151 4.1 INTRODUCTION 152 4.1.1 MIXED-SIGNAL
DEVICES AND SYSTEMS 153 4.1.2 IMPORTANCE OF INTEGRATION IN MOBILE
APPLICATIONS 155 4.1.3 MIXED-SIGNAL ARCHITECTURE 156 4.1.4 MIXED-SIGNAL
DESIGN CHALLENGES 157 4.1.5 FABRICATION TECHNOLOGIES 159 4.2 DESIGN OF
EMBEDDED PASSIVES IN RF FRONT END 160 4.2.1 EMBEDDED INDUCTORS 161 4.2.2
EMBEDDED CAPACITORS 166 4.2.3 EMBEDDED FILTERS 167 4.2.4 EMBEDDED BALUNS
171 4.2.5 FILTER-BALUN NETWORKS 175 4.2.6 TUNABLE FILTERS 178 4.3
CHIP-PACKAGE CODESIGN 180 4.3.1 LOW NOISE AMPLIFIER DESIGN 181 4.3.2
CONCURRENT OSCILLATOR DESIGN 184 4.4 DESIGN OF WLAN FRONT-END MODULE 191
CONTENTS XI 4.5 DESIGN TOOLS 194 4.5.1 SYNTHESIS OF EMBEDDED RF CIRCUITS
195 4.5.2 MODELING OF SIGNAL AND POWER DELIVERY NETWORKS 198 4.5.3
RATIONAL FUNCTIONS, NETWORK SYNTHESIS, AND TRANSIENT SIMULATION 204
4.5.4 DESIGN FOR MANUFACTURING 208 4.6 COUPLING 214 4.6.1
ANALOG-TO-ANALOG COUPLING 214 4.6.2 DIGITAL-TO-ANALOG COUPLING 222 4.7
DECOUPLING 227 4.7.1 NEED FOR DECOUPLING IN DIGITAL APPLICATIONS 228
4.7.2 ISSUES WITH SMD CAPACITORS 229 4.7.3 EMBEDDED DECOUPLING 230 4.7.4
CHARACTERIZATION OF EMBEDDED CAPACITORS 235 4.8 ELECTROMAGNETIC BANDGAP
(EBG) STRUCTURES 239 4.8.1 ANALYSIS AND DESIGN OF EBG STRUCTURES 242
4.8.2 APPLICATION OF EBGS IN POWER SUPPLY NOISE SUPPRESSION 246 4.8.3
RADIATION ANALYSIS OF EBGS 248 4.9 SUMMARY 250 ACKNOWLEDGMENTS 251
REFERENCES 251 5 RADIO FREQUENCY SYSTEM-ON-PACKAGE (RF SOP) 261 5.1
INTRODUCTION 262 5.2 RFSOPCONCEPT 262 5.3 HISTORICAL EVOLUTION OF RF
PACKAGING TECHNOLOGIES 265 5.4 RF SOP TECHNOLOGIES 267 5.4.1 MODELING
AND OPTIMIZATION 267 5.4.2 RF SUBSTRATE MATERIALS TECHNOLOGIES 268 5.4.3
ANTENNAS 269 5.4.4 INDUCTORS 278 5.4.5 RF CAPACITORS 282 5.4.6 RESISTORS
288 5.4.7 FILTERS 295 5.4.8 BALUNS 297 5.4.9 COMBINERS 298 5.4.10 RF
MEMS SWITCHES 300 5.4.11 RFIDS 305 5.5 INTEGRATED RF MODULES 308 5.5.1
WLAN 308 5.5.2 INTELLIGENT NETWORK COMMUNICATOR (INC) 310 5.6 FUTURE
TRENDS 312 ACKNOWLEDGMENTS 313 REFERENCES 314 CONTENTS 6 INTEGRATED
CHIP-TO-CHIP OPTOELECTRONIC SOP 321 6.1 INTRODUCTION 322 6.2
APPLICATIONS OF OPTOELECTRONIC SOP 323 6.2.1 HIGH-SPEED DIGITAL SYSTEMS
AND HIGH-PERFORMANCE COMPUTING 323 6.2.2 RF-OPTICAL COMMUNICATION
SYSTEMS 324 6.3 INTEGRATION CHALLENGES IN THIN-FILM OPTOELECTRONIC SOP
325 6.3.1 OPTICAL ALIGNMENT 326 6.3.2 KEY PHYSICAL AND OPTICAL
PROPERTIES OF THIN-FILM OPTICAL WAVEGUIDE MATERIALS 326 6.4 ADVANTAGES
OF OPTOELECTRONIC SOP 331 6.4.1 COMPARISON OF HIGH-SPEED ELECTRICAL AND
OPTICAL WIRING PERFORMANCE 331 6.4.2 WIRING DENSITY 332 6.4.3 POWER
DISSIPATION 334 6.4.4 RELIABILITY 335 6.5 EVOLUTION OF OPTOELECTRONIC
SOP TECHNOLOGY 336 6.5.1 BOARD-TO-BOARD OPTICAL WIRING 336 6.5.2
CHIP-TO-CHIP OPTICAL INTERCONNECTS 339 6.6 OPTOELECTRONIC SOP THIN-FILM
COMPONENTS 341 6.6.1 PASSIVE THIN-FILM LIGHTWAVE CIRCUITS 342 6.6.2
ACTIVE OPTOELECTRONIC SOP THIN-FILM COMPONENTS 354 6.6.3 OPPORTUNITIES
FOR 3D LIGHTWAVE CIRCUITS 355 6.7 SOP INTEGRATION: INTERFACE OPTICAL
COUPLING 357 6.8 ON-CHIP OPTICAL CIRCUITS 363 6.9 FUTURE TRENDS IN
OPTOELECTRONIC SOP 365 6.10 SUMMARY 365 REFERENCES 366 TABLE 6.1
REFERENCES 374 7 SOP SUBSTRATE WITH MULTILAYER WIRING AND THIN-FILM
EMBEDDED COMPONENTS 377 7.1 INTRODUCTION 378 7.2 HISTORICAL EVOLUTION OF
SUBSTRATE INTEGRATION TECHNOLOGIES 380 7.3 SOP SUBSTRATE 381 7.3.1
DRIVERS AND CHALLENGES 381 7.3.2 ULTRATHIN-FILM WIRING WITH EMBEDDED
LOW-K DIELECTRICS, CORES, AND CONDUCTORS 384 7.3.3 EMBEDDED PASSIVES 415
7.3.4 EMBEDDED ACTIVES 430 7.3.5 MINIATURIZED THERMAL MATERIALS AND
STRUCTURES 434 7.4 FUTURE SOP SUBSTRATE INTEGRATION 435 ACKNOWLEDGMENTS
437 REFERENCES 437 CONTENTS XIUE 8 MIXED-SIGNAL (SOP) RELIABILITY 443 8.1
SYSTEM-LEVEL RELIABILITY CONSIDERATIONS 445 8.1.1 FAILURE MECHANISMS 446
8.1.2 DESIGN-FOR-RELIABILITY 447 8.1.3 RELIABILITY VERIFICATION 449 8.2
RELIABILITY OF MULTIFUNCTION SOP SUBSTRATE 450 8.2.1 MATERIALS AND
PROCESS RELIABILITY 450 8.2.2 DIGITAL FUNCTION RELIABILITY AND
VERIFICATION 458 8.2.3 RF FUNCTION RELIABILITY AND VERIFICATION 461
8.2.4 OPTICAL FUNCTION RELIABILITY AND VERIFICATION 463 8.2.5
MULTIFUNCTION SYSTEM RELIABILITY 467 8.3 SUBSTRATE-TO-IC INTERCONNECTION
RELIABILITY 468 8.3.1 FACTORS AFFECTING THE SUBSTRATE-TO-IC
INTERCONNECTION RELIABILITY 469 8.3.2 100-UM FLIP-CHIP ASSEMBLY
RELIABILITY 471 8.3.3 RELIABILITY AGAINST DIE CRACKING 476 8.3.4 SOLDER
JOINT RELIABILITY 476 8.3.5 INTERFACIAL ADHESION AND EFFECT OF MOISTURE
ON UNDERFILL RELIABILITY 478 8.4 FUTURE TRENDS AND DIRECTIONS 482 8.4.1
EXTENDING SOLDER 483 8.4.2 COMPLAINT INTERCONNECTS 484 8.4.3 ALTERNATIVE
TO SOLDER AND NANO INTERCONNECTS 484 8.5 SUMMARY 486 REFERENCES 487 9
MEMS PACKAGING 495 9.1 INTRODUCTION 496 9.2 CHALLENGES IN MEMS PACKAGING
496 9.3 CHIP-SCALE VERSUS WAFER-SCALE PACKAGING 497 9.4 WAFER BONDING
TECHNIQUES 499 9.4.1 DIRECT BONDING 500 9.4.2 BONDING USING INTERMEDIATE
LAYERS 500 9.5 SACRIFICIAL FILM-BASED SEALING TECHNIQUES 505 9.5.1
ETCHING THE SACRIFICIAL MATERIAL 505 9.5.2 DECOMPOSITION OF SACRIFICIAL
POLYMERS 509 9.6 LOW-LOSS POLYMER ENCAPSULATION TECHNIQUES 514 9.7
TECHNIQUES UTILIZING GETTERS 516 9.7.1 NONEVAPORABLE GETTERS 516 9.7.2
THIN-FILM GETTERS 517 9.7.3 IMPROVING MEMS RELIABILITY THROUGH GETTERS
520 9.8 INTERCONNECTIONS 522 9.9 ASSEMBLY 524 9.10 SUMMARY AND FUTURE
TRENDS 527 REFERENCES 528 WAFER-LEVEL SOP 535 10.1 INTRODUCTION 536
10.1.1 DEFINITION 536 10.1.2 WAFER-LEVEL PACKAGING*HISTORICAL EVOLUTION
537 10.2 BUILDUP WIRING AND REDISTRIBUTION 540 10.2.1 IC-PACKAGE PITCH
GAP 540 10.2.2 REDISTRIBUTION LAYERS ON SI TO CLOSE THE PITCH GAP 543
10.3 WAFER-LEVEL THIN-FILM EMBEDDED COMPONENTS 544 10.3.1 EMBEDDED
THIN-FILM COMPONENTS IN THE REDISTRIBUTION LAYER (RDL) 544 10.4
WAFER-LEVEL PACKAGING AND INTERCONNECTIONS (WLPI) 548 10.4.1 CLASSES OF
WAFER-LEVEL PACKAGING AND INTERCONNECTIONS (WLPI) 552 10.4.2 RIGID
INTERCONNECTIONS 560 10.4.3 WLSOPASSEMBLY 585 10.4.3 WLSOP 590 10.5
WAFER-LEVEL PROBING AND BURN-IN 591 10.6 SUMMARY 595 ACKNOWLEDGMENTS 595
REFERENCES 595 THERMAL SOP 605 11.1 FUNDAMENTALS OF THERMAL SOP 606
11.1.1 THERMAL IMPLICATIONS OF SOP 607 11.1.2 SYSTEM-LEVEL THERMAL
CONSTRAINTS IN SOP- BASED PORTABLES 609 11.2 THERMAL SOURCES IN SOP
MODULES 610 11.2.1 DIGITAL SOP 611 11.2.2 RFSOP 613 11.2.3
OPTOELECTRONIC SOP 615 11.2.4 MEMSSOP 617 11.3 FUNDAMENTAL HEAT TRANSFER
MODES 618 11.3.1 CONDUCTION 618 11.3.2 CONVECTION 623 11.3.3 RADIATION
626 11.4 FUNDAMENTALS OF THERMAL CHARACTERIZATION 629 11.4.1 NUMERICAL
METHODS FOR THERMAL CHARACTERIZATION 629 11.4.2 EXPERIMENTAL METHODS FOR
THERMAL CHARACTERIZATION 637 11.5 THERMAL MANAGEMENT TECHNOLOGIES 637
11.5.1 THERMAL DESIGN METHODOLOGIES 638 11.6 POWER MINIMIZATION
METHODOLOGIES 648 11.6.1 PARALLEL PROCESSING 649 11.6.2 DYNAMIC VOLTAGE
AND FREQUENCY SCALING (DVFS) 649 CONTENTS XV 11.6.3 APPLICATION-SPECIFIC
PROCESSORS (ASP) 650 11.6.4 CACHE POWER MINIMIZATION 650 11.6.5 POWER
HARNESSING 651 11.7 SUMMARY 651 ACKNOWLEDGMENT 651 REFERENCES 652 12
ELECTRICAL TEST OF SOP MODULES AND SYSTEMS 659 12.1 SOP ELECTRICAL TEST
CHALLENGES 660 12.1.1 OBJECTIVES OF THE HVM TEST PROCESS AND CHALLENGES
FOR SOPS 662 12.1.2 HVM TEST FLOW FOR SOPS 663 12.2 KNOWN GOOD EMBEDDED
SUBSTRATE TEST 664 12.2.1 SUBSTRATE INTERCONNECT TESTS 664 12.2.2
TESTING EMBEDDED PASSIVES 671 12.3 KNOWN GOOD EMBEDDED MODULE TEST OF
DIGITAL SUBSYSTEMS 677 12.3.1 BOUNDARY SCAN*IEEE 1149.1 677 12.3.2
MULTI-GIGAHERTZ DIGITAL TEST: RECENT DEVELOPMENTS . . . 681 12.4 KGEM
TEST OF MIXED-SIGNAL AND RF SUBSYSTEMS 685 12.4.1 TEST STRATEGIES 685
12.4.2 FAULT MODELS AND TEST QUALITY 688 12.4.3 DIRECT MEASUREMENT OF
SPECIFICATIONS USING DEDICATED CIRCUITRY 689 12.4.4 ALTERNATE TESTING
METHODS FOR MIXED-SIGNAL AND RF CIRCUITS 690 12.5 SUMMARY 707
ACKNOWLEDGMENTS 707 REFERENCES 707 13 BIOSENSOR SOP 717 13.1
INTRODUCTION TO BIOSENSOR SOP 717 13.1.1 SOP: A HIGHLY MINIATURIZED
ELECTRONIC SYSTEM TECHNOLOGY 717 13.1.2 BIOSENSOR SOP FOR MINIATURIZED
BIOMEDICAL IMPLANTS AND SENSOR SYSTEMS 718 13.1.3 BUILDING BLOCKS OF
BIOSENSOR SOP 723 13.2 BIOSENSING 723 13.2.1 MICROCHANNELS FOR BIOFLUID
TRANSPORT 723 13.2.2 BIOSENSING ELEMENT (PROBE) DESIGN AND PREPARATION .
. 724 13.2.3 PROBE-TARGET MOLECULAR HYBRIDIZATION 727 13.3 SIGNAL
CONVERSION 730 13.3.1 NANOMATERIALS AND NANOSTRUCTURES FOR SIGNAL
CONVERSION COMPONENTS 730 13.3.2 SURFACE MODIFICATION AND
BIOFUNCTIONALIZATION OF SIGNAL CONVERSION COMPONENT 734 13.3.3 SIGNAL
CONVERSION METHODS 735 XVJ CONTENTS 13.4 SIGNAL DETECTION AND ELECTRONIC
PROCESSING 741 13.4.1 LOW-POWER APPLICATION-SPECIFIC INTEGRATED CIRCUITS
(ASICS) AND MIXED-SIGNAL DESIGN FOR BIOSENSOR SOP 741 13.4.2 BIO- SOP
SUBSTRATE INTEGRATION TECHNOLOGIES 744 13.5 SUMMARY AND FUTURE TRENDS
745 13.5.1 NANO BIO-SOP INTEGRATION CHALLENGES 745 REFERENCES 746 INDEX
749 -;
|
| any_adam_object | 1 |
| author | Tummala, Rao R. 1942- Swaminathan, Madhavan |
| author_GND | (DE-588)138318735 |
| author_facet | Tummala, Rao R. 1942- Swaminathan, Madhavan |
| author_role | aut aut |
| author_sort | Tummala, Rao R. 1942- |
| author_variant | r r t rr rrt m s ms |
| building | Verbundindex |
| bvnumber | BV035957512 |
| callnumber-first | T - Technology |
| callnumber-label | TK7870 |
| callnumber-raw | TK7870.15 |
| callnumber-search | TK7870.15 |
| callnumber-sort | TK 47870.15 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4900 |
| ctrlnum | (OCoLC)636255986 (DE-599)GBV564713775 |
| dewey-full | 621.381/046 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.381/046 |
| dewey-search | 621.381/046 |
| dewey-sort | 3621.381 246 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV035957512 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T22:08:04Z |
| institution | BVB |
| isbn | 0071459065 9780071459068 |
| language | English |
| lccn | 2008016996 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-018814532 |
| oclc_num | 636255986 |
| open_access_boolean | |
| owner | DE-83 |
| owner_facet | DE-83 |
| physical | XX, 785 S. Ill., graph. Darst. 25 cm |
| publishDate | 2008 |
| publishDateSearch | 2008 |
| publishDateSort | 2008 |
| publisher | McGraw-Hill |
| record_format | marc |
| spelling | Tummala, Rao R. 1942- Verfasser (DE-588)138318735 aut Introduction to system-on-package (SOP) miniaturization of the entire system Rao R. Tummala ; Madhavan Swaminathan New York, NY [u.a.] McGraw-Hill 2008 XX, 785 S. Ill., graph. Darst. 25 cm txt rdacontent n rdamedia nc rdacarrier Includes bibliographical references and index Multichip modules (Microelectronics) / Design and construction Microelectronic packaging Multichip modules (Microelectronics) Design and construction Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Multichiptechnik (DE-588)4267925-4 gnd rswk-swf Mixed-Signal-Schaltung (DE-588)4756481-7 gnd rswk-swf MEMS (DE-588)4824724-8 gnd rswk-swf Mikrosystemtechnik (DE-588)4221617-5 gnd rswk-swf System-on-Chip (DE-588)4740357-3 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 s System-on-Chip (DE-588)4740357-3 s Multichiptechnik (DE-588)4267925-4 s Mikrosystemtechnik (DE-588)4221617-5 s MEMS (DE-588)4824724-8 s Mixed-Signal-Schaltung (DE-588)4756481-7 s DE-604 Swaminathan, Madhavan Verfasser aut http://www.gbv.de/dms/ilmenau/toc/564713775.PDF lizenzfrei Inhaltsverzeichnis GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018814532&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Tummala, Rao R. 1942- Swaminathan, Madhavan Introduction to system-on-package (SOP) miniaturization of the entire system Multichip modules (Microelectronics) / Design and construction Microelectronic packaging Multichip modules (Microelectronics) Design and construction Integrierte Schaltung (DE-588)4027242-4 gnd Multichiptechnik (DE-588)4267925-4 gnd Mixed-Signal-Schaltung (DE-588)4756481-7 gnd MEMS (DE-588)4824724-8 gnd Mikrosystemtechnik (DE-588)4221617-5 gnd System-on-Chip (DE-588)4740357-3 gnd |
| subject_GND | (DE-588)4027242-4 (DE-588)4267925-4 (DE-588)4756481-7 (DE-588)4824724-8 (DE-588)4221617-5 (DE-588)4740357-3 |
| title | Introduction to system-on-package (SOP) miniaturization of the entire system |
| title_auth | Introduction to system-on-package (SOP) miniaturization of the entire system |
| title_exact_search | Introduction to system-on-package (SOP) miniaturization of the entire system |
| title_full | Introduction to system-on-package (SOP) miniaturization of the entire system Rao R. Tummala ; Madhavan Swaminathan |
| title_fullStr | Introduction to system-on-package (SOP) miniaturization of the entire system Rao R. Tummala ; Madhavan Swaminathan |
| title_full_unstemmed | Introduction to system-on-package (SOP) miniaturization of the entire system Rao R. Tummala ; Madhavan Swaminathan |
| title_short | Introduction to system-on-package (SOP) |
| title_sort | introduction to system on package sop miniaturization of the entire system |
| title_sub | miniaturization of the entire system |
| topic | Multichip modules (Microelectronics) / Design and construction Microelectronic packaging Multichip modules (Microelectronics) Design and construction Integrierte Schaltung (DE-588)4027242-4 gnd Multichiptechnik (DE-588)4267925-4 gnd Mixed-Signal-Schaltung (DE-588)4756481-7 gnd MEMS (DE-588)4824724-8 gnd Mikrosystemtechnik (DE-588)4221617-5 gnd System-on-Chip (DE-588)4740357-3 gnd |
| topic_facet | Multichip modules (Microelectronics) / Design and construction Microelectronic packaging Multichip modules (Microelectronics) Design and construction Integrierte Schaltung Multichiptechnik Mixed-Signal-Schaltung MEMS Mikrosystemtechnik System-on-Chip |
| url | http://www.gbv.de/dms/ilmenau/toc/564713775.PDF http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018814532&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT tummalaraor introductiontosystemonpackagesopminiaturizationoftheentiresystem AT swaminathanmadhavan introductiontosystemonpackagesopminiaturizationoftheentiresystem |
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