Verfügbarkeit: The definitive guide to the ARM Cortex-M3

The definitive guide to the ARM Cortex-M3:

Gespeichert in:

Bibliographische Detailangaben
1. Verfasser:	Yiu, Joseph (VerfasserIn)
Format:	Buch
Sprache:	English
Veröffentlicht:	Amsterdam Elsevier [u.a.] [20]08
Ausgabe:	[Nachdr.]
Schriftenreihe:	Embedded technology series
Schlagworte:	Embedded computer systems Microprocessors ARM Cortex-M4 ARM Cortex-M3 Mikroprozessor Eingebettetes System Mikrocontroller ARM > Computerarchitektur
Online-Zugang:	Inhaltsverzeichnis
Beschreibung:	XIX, 359 S. graph. Darst. 24 cm
ISBN:	9780750685344

Internformat

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Datensatz im Suchindex

DE-BY-862_location	2000
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adam_text	THE DEFINITIVE GUIDE TO THE ARM CORTEX-M3 JOSEPH YIU AMSTERDAM * BOSTON * HEIDELBERG * LONDON * NEW YORK OXFORD * PARIS * SAN DIEGO * SAN FRANCISCO SINGAPORE * SYDNEY * TOKYO NEWNES IS AN IMPRINT OF ELSEVIER NEWNES TABLE OF CONTENTS FOREWOPD XIII PREFACE XIV ACKNOWLEDGMENTS XV TERMS AND ABBREVIATIONS XVI CONVENTIONS XVIII REFERENCES XIX CHAPTER 1 - INTRODUCTION 7 WHAT IS THE ARM CORTEX-M3 PROCESSOR? 1 BACKGROUND OF ARM AND ARM ARCHITECTURE 3 A BRIEF HISTORY 3 ARCHITECTURE VERSIONS 4 PROCESSOR NAMING 6 INSTRUCTION SET DEVELOPMENT 8 THE THUMB-2 INSTRUCTION SET ARCHITECTURE (ISA) 9 CORTEX-M3 PROCESSOR APPLICATIONS 10 ORGANIZATION OF THIS BOOK 11 FURTHER READINGS 11 CHAPTER 2 * OVERVIEW OFTHE CORTEX-M3 13 FUNDAMENTALS 13 REGISTERS 14 R0 TO R12: GENERAL-PURPOSE REGISTERS 14 R13: STACK POINTERS 14 R14: THE LINK REGISTER 15 R15: THE PROGRAM COUNTER 15 SPECIAL REGISTERS 15 OPERATION MODES 16 THE BUILT-IN NESTED VECTORED INTERRUPT CONTROLLER 17 NESTED INTERRUPT SUPPORT 18 VECTORED INTERRUPT SUPPORT 18 DYNAMIC PRIORITY CHANGES SUPPORT 18 REDUCTION OF INTERRUPT LATENCY 18 INTERRUPT MASKING 18 V TABLE OFCONTENTS THE MEMORY MAP 19 THE BUS INTERFACE 20 THE MEMORY PROTECTION UNIT 20 THE INSTRUCTION SET 20 INTERRUPTS AND EXCEPTIONS 22 DEBUGGING SUPPORT 24 CHARACTERISTICS SUMMARY 25 HIGH PERFORMANCE 25 ADVANCED INTERRUPT-HANDLING FEATURES 25 LOW POWER CONSUMPTION 26 SYSTEM FEATURES 26 DEBUG SUPPORTS 26 CHAPTER 3 - CORTEX-M3 BASICS 29 REGISTERS 29 GENERAL-PURPOSE REGISTERS R0-R7 29 GENERAL-PURPOSE REGISTERS R8-R12 29 STACK POINTER RL3 30 LINK REGISTER R14 32 PROGRAM COUNTER R15 33 SPECIAL REGISTERS 33 PROGRAM STATUS REGISTERS (PSRS) 33 PRIMASK, FAULTMASK, AND BASEPRI REGISTERS 35 THE CONTROL REGISTER 36 OPERATION MODE 37 EXCEPTIONS AND INTERRUPTS 39 VECTORTABLES 40 STACK MEMORY OPERATIONS 41 BASIC OPERATIONS OF THE STACK 41 CORTEX-M3 STACK IMPLEMENTATION 42 THE TWO-STACK MODEL IN THE CORTEX-M3 43 RESET SEQUENCE 44 CHAPTER 4 - INSTRUCTION SETS 47 ASSEMBLY BASICS 47 ASSEMBLER LANGUAGE: BASIC SYNTAX 47 ASSEMBLER LANGUAGE: USE OF SUFFIXES 48 ASSEMBLER LANGUAGE: UNIFIED ASSEMBLER LANGUAGE 49 INSTRUCTION LIST 50 UNSUPPORTED INSTRUCTIONS 55 INSTRUCTION DESCRIPTIONS 57 ASSEMBLER LANGUAGE: MOVING DATA 57 LDR AND ADR PSEUDO INSTRUCTIONS 60 VI TABLE OFCONTENTS ASSEMBLER LANGUAGE: PROCESSING DATA 61 ASSEMBLER LANGUAGE: CALL AND UNCONDITIONAL BRANCH 66 ASSEMBLER LANGUAGE: DECISIONS AND CONDITIONAL BRANCHES 67 ASSEMBLER LANGUAGE: COMBINED COMPARE AND CONDITIONAL BRANCH 70 ASSEMBLER LANGUAGE: CONDITIONAL BRANCHES USING IT INSTRUCTIONS 71 ASSEMBLER LANGUAGE: INSTRUCTION BARRIER AND MEMORY BARRIER INSTRUCTIONS 72 ASSEMBLY LANGUAGE: SATURATION OPERATIONS 73 SEVERAL USEFUL INSTRUCTIONS IN THE CORTEX-M3 75 MSRANDMRS 75 IF-THEN 76 CBZANDCBNZ 77 SDIVANDUDIV 78 REV, REVH, AND REVSH 78 RBIT 78 SXTB, SXTH, UXTB, AND UXTH 79 BFCANDBFI 79 UBFXANDSBFX 79 LDRDANDSTRD 80 TBBANDTBH 80 CHAPTER 5 * MEMORY SYSTEMS 83 MEMORY SYSTEM FEATURES OVERVIEW 83 MEMORY MAPS 83 MEMORY ACCESS ATTRIBUTES 86 DEFAULT MEMORY ACCESS PERMISSIONS 88 BIT-BAND OPERATIONS 88 ADVANTAGES OF BIT-BAND OPERATIONS 92 BIT-BAND OPERATION OF DIFFERENT DATA SIZES 95 BIT-BAND OPERATIONS IN C PROGRAMS 95 UNALIGNED TRANSFERS 96 EXCLUSIVE ACCESSES 98 ENDIANMODE 100 CHAPTER 6 - CORTEX-M3 IMPLEMENTATION OVERVIEW 703 THE PIPELINE 103 A DETAILED BLOCK DIAGRAM 105 BUS INTERFACES ON THE CORTEX-M3 108 THEL-CODEBUS 108 THE D-CODE BUS 108 THE SYSTEM BUS 109 THE EXTERNAL PRIVATE PERIPHERAL BUS 109 THEDEBUG ACCESS PORT BUS 109 OTHER INTERFACES ON THE CORTEX-M3 109 VII TABLE OF CONTENTS THE EXTERNAL PRIVATE PERIPHERAL BUS 109 TYPICAL CONNECTIONS 111 RESET SIGNALS 112 CHAPTER 7 * EXCEPTIONS 115 EXCEPTION TYPES 115 DEFINITIONS OF PRIORITY 117 VECTORTABLES 123 INTERRUPT INPUTS AND PENDING BEHAVIOR 124 FAULT EXCEPTIONS 127 BUSFAULTS..: 127 MEMORY MANAGEMENT FAULTS 129 USAGEFAULTS 130 HARD FAULTS 132 DEALING WITH FAULTS 132 SVCANDPENDSV 133 CHAPTER 8- THE NVIC AND INTERRUPT CONTROI 137 NVICOVERVIEW 137 THE BASIC INTERRUPT CONFIGURATION 138 INTERRUPT ENABLE AND CLEAR ENABLE 138 INTERRUPT PENDING AND CLEAR PENDING 138 PRIORITY LEVELS 140 ACTIVE STATUS 141 PRIMASK AND FAULTMASK SPECIAL REGISTERS 141 THE BASEPRI SPECIAL REGISTER 142 CONFIGURATION REGISTERS FOR OTHER EXCEPTIONS 143 EXAMPLE PROCEDURES OF SETTING UP AN INTERRUPT 144 SOFTWARE INTERRUPTS 146 THE SYSTICK TIMER 147 CHAPTER 9 * INTERRUPT BEHAVIOR 749 INTERRUPT/EXCEPTION SEQUENCES 149 STACKING 149 VECTOR FETCHES 150 REGISTER UPDATES 151 EXCEPTION EXITS 151 NESTED INTERRUPTS 152 TAIL-CHAINING INTERRUPTS 152 LATE ARRIVALS 153 MORE ON THE EXCEPTION RETURN VALUE 153 INTERRUPT LATENCY 154 FAULTS RELATED TO INTERRUPTS 156 VIII TABLE OF CONTENTS STACKING 156 UNSTACKING 157 VECTOR FETCHES 157 INVALID RETURNS 157 CHAPTER 10 - CORTEX-M3 PROGRAMMING 159 OVERVIEW 159 USING ASSEMBLY 159 USINGC 160 THE INTERFACE BETWEEN ASSEMBLY AND C 161 ATYPICAL DEVELOPMENT FLOW 162 THE FIRST STEP 162 PRODUCING OUTPUTS 164 THE HELLO WORLD EXAMPLE 165 USING DATA MEMORY 169 USING EXCLUSIVE ACCESS FOR SEMAPHORES 170 USING BIT BAND FOR SEMAPHORES 172 WORKING WITH BIT FIELD EXTRACT AND TABLE BRANCH 173 CHAPTER 11 - EXCEPTIONS PROGRAMMING 775 USING INTERRUPTS 175 STACK SETUP 175 VECTOR TABLE SETUP 176 INTERRUPT PRIORITY SETUP 177 ENABLE THE INTERRUPT 178 EXCEPTION/INTERRUPT HANDLERS 179 SOFTWARE INTERRUPTS 180 EXAMPLE WITH EXCEPTION HANDLERS 181 USING SVC 184 SVC EXAMPLE: USE FOR OUTPUT FUNCTIONS 186 USING SVC WITH C 189 CHAPTER 12 * ADVANCED PROGRAMMING FEATURES AND SYSTEM BEHAVIOR 193 RUNNING A SYSTEM WITH TWO SEPARATE STACKS 193 DOUBLE-WORD STACK ALIGNMENT 196 NONBASE THREAD ENABLE 197 PERFORMANCE CONSIDERATIONS 200 LOCKUP SITUATIONS 201 WHAT HAPPENS DURING LOCKUP? 201 AVOIDING LOCKUP 202 CHAPTER 13 - THE MEMORY PROTECTION UNIT 205 OVERVIEW 205 MPU REGISTERS 206 IX TABLE OF CONTENTS SETTING UP THE MPU 211 TYPICAL SETUP 217 EXAMPLE USE OF THE SUBREGION DISABLE 217 CHAPTER 14 * OTHER CORTEX-M3 FEATURES 223 THE SYSTICK TIMER 223 POWER MANAGEMENT 227 MULTIPROCESSOR COMMUNICATION 229 SELF-RESET CONTROL 231 CHAPTER 15 - DEBUG ARCHITECTURE 233 DEBUGGING FEATURES OVERVIEW 233 CORESIGHT OVERVIEW 234 PROCESSOR DEBUGGING INTERFACE 234 THE DEBUG HOST INTERFACE 235 DP MODULE, AP MODULE, AND DAP 235 TRACE INTERFACE 236 CORESIGHT CHARACTERISTICS 237 DEBUG MODES 239 DEBUGGING EVENTS 241 BREAKPOINT IN THE CORTEX-M3 243 ACCESSING REGISTER CONTENT IN DEBUG 244 OTHER CORE DEBUGGING FEATURES 245 CHAPTER 16 - DEBUGGING COMPONENTS 247 INTRODUCTION 247 THE TRACE SYSTEM IN THE CORTEX-M3 247 TRACE COMPONENTS: DATA WATCHPOINT AND TRACE 248 TRACE COMPONENTS: INSTRUMENTATION TRACE MACROCELL 250 SOFTWARE TRACE WITH THE ITM 251 HARDWARE TRACE WITH ITM AND DWT 251 ITMTIMESTAMP 251 TRACE COMPONENTS: EMBEDDED TRACE MACROCELL 252 TRACE COMPONENTS: TRACE PORT INTERFACE UNIT 253 THE FLASH PATCH AND BREAKPOINT UNIT 253 THE AHB ACCESS PORT 256 ROM TABLE 257 CHAPTER 17 * CETTING STARTED WITH CORTEX-M3 DEVELOPMENT 259 CHOOSING A CORTEX-M3 PRODUCT 259 DIFFERENCES BETWEEN CORTEX-M3 REVISION 0 AND REVISION 1 260 REVISION 1 CHANGE: MOVING FROM JTAG-DP TO SWJ-DP 261 DEVELOPMENT TOOLS 262 C COMPILER 262 EMBEDDED OPERATING SYSTEM SUPPORT 263 TABLE OF CONTENTS CHAPTER 18 * PORTING APPLICATIONS FROM THE ARM7 TO THE CORTEX-M3 265 OVERVIEW 265 SYSTEM CHARACTERISTICS 266 MEMORY MAP 266 INTERRUPTS 266 MPU 267 SYSTEM CONTROL 267 OPERATION MODES 267 ASSEMBLY LANGUAGE FILES 268 THUMB STATE 268 ARM STATE 268 C PROGRAM FILES 271 PRECOMPILED OBJECT FILES 271 OPTIMIZATION 271 CHAPTER 19 - STARTING CORTEX-M3 DEVELOPMENT USING THE GNU TOOL CHAIN 273 BACKGROUND 273 GETTING THE GNU TOOL CHAIN 273 DEVELOPMENT FLOW 274 EXAMPLES 275 EXAMPLE 1: THE FIRST PROGRAM 275 EXAMPLE 2: LINKING MULTIPLE FILES 277 EXAMPLE 3: A SIMPLE HELLO WORLD PROGRAM 278 EXAMPLE 4: DATA IN RAM 280 EXAMPLE 5: C ONLY, WITHOUT ASSEMBLY FILE 281 EXAMPLE 6: C ONLY, WITH STANDARD C STARTUP CODE 285 ACCESSING SPECIAL REGISTERS 287 USING UNSUPPORTED INSTRUCTIONS 287 INLINE ASSEMBLER IN THE GNUC COMPILER 287 CHAPTER 20 - GETTING STARTED WITH THE KEIL REALVIEW MICROCONTROLLER DEVELOPMENT KIT 289 OVERVIEW 289 GETTING STARTED WITH PVISION 290 OUTPUTTING THE HELLO WORLD MESSAGE VIA UART 295 TESTING THE SOFTWARE 298 USING THE DEBUGGER 300 THE INSTRUCTION SET SIMULATOR 303 MODIFYING THE VECTOR TABLE 305 STOPWATCH EXAMPLE WITH INTERRUPTS 306 APPENDIX A - CORTEX-M3 INSTRUCTIONS SUMMARY 375 SUPPORTED 16-BIT THUMB INSTRUCTIONS 315 SUPPORTED 32-BIT THUMB-2 INSTRUCTIONS 319 VI TABLE OF CONTENTS APPENDIX B * 16-BIT THUMB INSTRUCTIONS AND ARCHITECTURE VERSIONS 329 APPENDIX C * CORTEX-M3 EXCEPTIONS QUICK REFERENCE 331 EXCEPTION TYPES ANDENABLES 331 STACK CONTENTS AFTER EXCEPTION STACKING 332 APPENDIX D - NVIC REGISTERS QUICK REFERENCE 333 APPENDIX E * CORTEX-M3 TROUBLESHOOTING GUIDE 347 OVERVIEW J 347 DEVELOPING FAUIT HANDLERS 348 REPORT FAULT STATUS REGISTERS 349 REPORT STACKED PC 349 READ FAULT ADDRESS REGISTER 350 CLEAR FAULT STATUS BITS 350 OTHERS 350 UNDERSTANDING THE CAUSE OFTHE FAULT 351 OTHER POSSIBLE PROBLEMS 354 INDEX 355
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indexdate	2025-02-20T06:37:19Z
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language	English
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physical	XIX, 359 S. graph. Darst. 24 cm
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spellingShingle	Yiu, Joseph The definitive guide to the ARM Cortex-M3 Embedded computer systems Microprocessors ARM Cortex-M4 (DE-588)1129794342 gnd ARM Cortex-M3 (DE-588)1129794318 gnd Mikroprozessor (DE-588)4039232-6 gnd Eingebettetes System (DE-588)4396978-1 gnd Mikrocontroller (DE-588)4127438-6 gnd ARM Computerarchitektur (DE-588)4706184-4 gnd
subject_GND	(DE-588)1129794342 (DE-588)1129794318 (DE-588)4039232-6 (DE-588)4396978-1 (DE-588)4127438-6 (DE-588)4706184-4
title	The definitive guide to the ARM Cortex-M3
title_auth	The definitive guide to the ARM Cortex-M3
title_exact_search	The definitive guide to the ARM Cortex-M3
title_full	The definitive guide to the ARM Cortex-M3 Joseph Yiu
title_fullStr	The definitive guide to the ARM Cortex-M3 Joseph Yiu
title_full_unstemmed	The definitive guide to the ARM Cortex-M3 Joseph Yiu
title_short	The definitive guide to the ARM Cortex-M3
title_sort	the definitive guide to the arm cortex m3
topic	Embedded computer systems Microprocessors ARM Cortex-M4 (DE-588)1129794342 gnd ARM Cortex-M3 (DE-588)1129794318 gnd Mikroprozessor (DE-588)4039232-6 gnd Eingebettetes System (DE-588)4396978-1 gnd Mikrocontroller (DE-588)4127438-6 gnd ARM Computerarchitektur (DE-588)4706184-4 gnd
topic_facet	Embedded computer systems Microprocessors ARM Cortex-M4 ARM Cortex-M3 Mikroprozessor Eingebettetes System Mikrocontroller ARM Computerarchitektur
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018713998&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT yiujoseph thedefinitiveguidetothearmcortexm3

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