VHDL for engineers:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Upper Saddle River, NJ [u.a.]
Pearson Prentice Hall
2009
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis Klappentext |
| Beschreibung: | XXXII, 685 S. graph. Darst. 1 CD-ROM (12 cm) |
| ISBN: | 9780131424784 0131424785 |
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| 100 | 1 | |a Short, Kenneth L. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a VHDL for engineers |c Kenneth L. Short |
| 264 | 1 | |a Upper Saddle River, NJ [u.a.] |b Pearson Prentice Hall |c 2009 | |
| 300 | |a XXXII, 685 S. |b graph. Darst. |e 1 CD-ROM (12 cm) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Dispositifs logiques programmables | |
| 650 | 4 | |a VHDL (Langage de description de matériel informatique) | |
| 650 | 4 | |a VHDL (Computer hardware description language) | |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VHDL |0 (DE-588)4254792-1 |D s |
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Datensatz im Suchindex
| _version_ | 1804139339514380288 |
|---|---|
| adam_text | Contents
List of
Figures
XI
List of
Programs
xix
Preface
xxv
1
Digi
tal
Design Using VHDL and PLDs
1
1.1
VHDL/PLD Design Methodology
7
1.2
Requirements Analysis and Specification
5
1.3
VHDL Design Description
6
1.4
Verification Using Simulation
11
1.5
Testbenches
13
1.6
Functional (Behavioral) Simulation
16
1.7
Programmable Logic Devices (PLDs)
18
1.8
SPLDs and the 22V1
0
21
1.9
Logic Synthesis for the Target
PLD
27
1.10
Place-and-Route and Timing Simulation
31
1.11
Programming and Verifying a Target
PLD
37
1.12
VHDL/PLD Design Methodology Advantages
38
1.13
VHDL s Development
39
1.14
VHDL for Synthesis versus VHDL for Simulation
39
1.15
This Book s Primary Objective
40
vi
Contents
2
Entities, Architectures, and Coding Styles
44
2.1
Design Units, Library Units, and Design Entities
44
2.2
Entity Declaration
45
2.3
VHDL Syntax Definitions
47
2.4
Port Modes
50
2.5
Architecture Body
53
2.6
Coding Styles
55
2.7
Synthesis Results versus Coding Style
66
2.8
Levels of Abstraction and Synthesis
69
2.9
Design Hierarchy and Structural Style
71
3
Sign
als
and Data Types
82
3.1
Object Classes and Object Types
82
3.2
Signal Objects
84
3.3
Scalar Types
88
3.4
Type Std_Logic
93
3.5
Scalar Literals and Scalar Constants
99
3.6
Composite Types
100
3.7
Arrays
101
3.8
Types Unsigned and Signed
107
3.9
Composite Literals and Composite Constants
no
3.10
Integer Types
112
3.11
Port Types for Synthesis
116
3.12
Operators and Expressions
118
4
Dati
iflow Style Combinational Design
123
4.1
Logical Operators
123
4.2
Signal Assignments in Dataflow Style Architectures
127
4.3
Selected Signal Assignment
130
A A Type Boolean and the Relational Operators
7 32
4.5
Conditional Signal Assignment
134
4.6
Priority Encoders
139
4.7
Don t Care Inputs and Outputs
740
4.8
Decoders
144
4.9
Table Lookup
747
4.10
Three-state Buffers
757
4.11
Avoiding Combinational Loops
755
Contents
vii
5
Behavioral Style Combinational Design
165
5.1
Behavioral Style Architecture
765
5.2
Process Statement
769
5.3
Sequential Statements
170
5.4
Case Statement
777
5.5
If Statement
776
5.6
Loop Statement
787
5.7
Variables
785
5.8
Parity Detector Example
788
5.9
Synthesis of Processes Describing Combinational Systems
193
6
Even
t-Driven Simulation
201
6.1
Simulator Approaches
201
6.2
Elaboration
203
6.3
Signal Drivers
208
6.4
Simulator Kernel Process
210
6.5
Simulation Initialization
212
6.6
Simulation Cycles
215
6.7
Signals versus Variables
223
6.8
Delta Delays
230
6.9
Delta Delays and Combinational Feedback
235
6.10
Multiple Drivers
239
6.11
Signal Attributes
241
7
Test
benches for Combinational Designs
25 1
7.1
Design Verification
257
7.2
Functional Verification of Combinational Designs
255
7.3
A Simple Testbench
255
7.4
Physical Types
258
7.5
Single Process Testbench
260
7.6
Wait Statements
263
7.7
Assertion and Report Statements
265
7.8
Records and Table Lookup Testbenches
268
7.9
Testbenches That Compute Stimulus and Expected Results
272
7.10
Predefined Shift Operators
274
7.11
Stimulus Order Based on
UUT
Functionality
276
7.12
Comparing a UUT to a Behavioral Intent Model
279
7.13
Code Coverage and Branch Coverage
287
viii Contents
7.14
Post-Synthesis and Timing Verifications for Combinational
Designs
284
7.15
Timing Models Using VITAL and SDF
288
8
Latches and Flip-flops
304
8.1
Sequential Systems and Their Memory Elements
304
8.2
D
Latch
308
8.3
Detecting Clock Edges
315
8.4
D
Flip-flops
317
8.5
Enabled (Gated) Flip-flop
324
8.6
Other Flip-flop Types
328
8.7
PLD
Primitive Memory Elements
337
8.8
Timing Requirements and Synchronous Input Data
332
9
M u 11 i b i t
Latches, Registers, Counters,
a n d
Memory
337
9.1
Multibit Latches and Registers
337
9.2
Shift Registers
340
9.3
Shift Register Counters
346
9.4
Counters
348
9.5
Detecting Non-clock Signal Edges
360
9.6
Microprocessor Compatible Pulse Width Modulated Signal
Generator
366
9.7
Memories
370
10
Finit
e
State Machines
380
10.1
Finite State Machines
380
10.2
FSM State Diagrams
386
10.3
Three Process FSM VHDL Template
388
10.4
State Diagram Development
392
10.5
Decoder for an Optical Shaft Encoder
403
10.6
State Encoding and State Assignment
409
10.7
Supposedly Safe FSMs
414
10.8
Inhibit Logic FSM Example
418
10.9
Counters as Moore FSMs
422
11
ASM
Charts and
RTL
Design
431
11.1
Algorithmic State Machine Charts
431
11.2
Converting ASM Charts to VHDL
438
Contents ix
11.3 System
Architecture
441
11.4
Successive
Approximation Register Design
Example
445
11.5
Sequential Multiplier
Design 457
12
Subprograms
469
12.1
Subprograms
469
12.2
Functions
473
12.3
Procedures
480
12.4
Array Attributes and Unconstrained Arrays
484
12.5
Overloading Subprograms and Operators
491
12.6
Type Conversions
494
13
Packages
50Î
13.1
Packages and Package Bodies
507
13.2
Standard and
De
Facto Standard Packages
505
13.3
Package STD_LOC ICJ
164 510
13.4
Package NUMERIC_STD (IEEE Std
1076.3) 576
13.5
Package STDJ-OGIC.ARITH
523
13.6
Packages for VHDL Text Output
524
14
Testbenches for Sequential Systems
526
14.1
Simple Sequential Testbenches
526
14.2
Generating a System Clock
527
14.3
Generating the System Reset
537
14.4
Synchronizing Stimulus Generation and Monitoring
532
14.5
Testbench for Successive Approximation Register
538
14.6
Determining a Testbench Stimulus for a Sequential System
542
14.7
Using Procedures for Stimulus Generation
545
14.8
Output Verification in Stimulus Procedures
550
14.9
Bus Functional Models
552
14.10
Response Monitors
560
15
Modular Design and Hierarchy
566
15.1
Modular Design, Partitioning, and Hierarchy
566
15.2
Design Units and Library Units
577
15.3
Design Libraries
573
15.4
Using Library Units
574
15.5
Direct Design Entity Instantiation
577
15.6
Components and Indirect Design Entity Instantiation
580
χ
Contents
15.7
Configuration
Declarations
587
15.8
Component
Connections
594
15.9
Parameterized Design Entities
598
15.10
Library of Parameterized Modules (LPM)
602
15.11
Generate Statement
605
16
More Design Examples
615
16.1
Microprocessor-Compatible Quadrature
Decoder/Counter Design
675
16.2
Verification of Quadrature Decoder/Counter
624
16.3
Parameterized Quadrature Decoder/Counter
628
16.4
Electronic Safe Design
630
16.5
Verification of Electronic Safe
644
16.6
Encoder for RF Transmitter Design
649
Appendix VHDL Attributes
659
Bibliography
663
Index
665
VHDL
d
FOR ENGINEERS
KENNETH
L.
SHORT
VHDL for Engineers teaches readers how to design and simulate digital systems using
the hardware description language VHDL. These systems are designed for implementation
using programmable logic devices (PLDs) such as complex programmable logic devices
(CPLDs) and field programmable gate arrays (FPGAs). The book focuses on writing VHDL
design descriptions and VHDL testbenches. The steps in VHDL/PLD design methodology
are another key focus.
This book is suitable for anyone with a basic understanding of logic design and a minimal
background in programming who desires to learn how to design digital systems using VHDL.
No prior experience with VHDL is required. Readers can begin producing synthesizable
designs quickly because mastery of the VHDL language and usage progresses in step-wise
fashion from simple to complex.
More than
275
block diagrams, logic diagrams, and timing waveforms and
180+
program
listings illustrate the design concepts. Programming examples are compliant with the IEEE
standard
1076-2002
for simulation and the IEEE standard
1076.6-2004
for synthesis.
Readers can evaluate their mastery of the material through working the wealth of
end-of-chapter problems.
The book includes the Aldec Active-HDL™
7.2
Student Edition Software, an ideal design and
simulation environment for learning VHDL.
|
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| author | Short, Kenneth L. |
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| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| id | DE-604.BV035653022 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T21:42:31Z |
| institution | BVB |
| isbn | 9780131424784 0131424785 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017707574 |
| oclc_num | 191258680 |
| open_access_boolean | |
| owner | DE-703 |
| owner_facet | DE-703 |
| physical | XXXII, 685 S. graph. Darst. 1 CD-ROM (12 cm) |
| publishDate | 2009 |
| publishDateSearch | 2009 |
| publishDateSort | 2009 |
| publisher | Pearson Prentice Hall |
| record_format | marc |
| spelling | Short, Kenneth L. Verfasser aut VHDL for engineers Kenneth L. Short Upper Saddle River, NJ [u.a.] Pearson Prentice Hall 2009 XXXII, 685 S. graph. Darst. 1 CD-ROM (12 cm) txt rdacontent n rdamedia nc rdacarrier Dispositifs logiques programmables VHDL (Langage de description de matériel informatique) VHDL (Computer hardware description language) VHDL (DE-588)4254792-1 gnd rswk-swf VHDL (DE-588)4254792-1 s DE-604 Digitalisierung UB Bayreuth application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017707574&sequence=000003&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis Digitalisierung UB Bayreuth application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017707574&sequence=000004&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA Klappentext |
| spellingShingle | Short, Kenneth L. VHDL for engineers Dispositifs logiques programmables VHDL (Langage de description de matériel informatique) VHDL (Computer hardware description language) VHDL (DE-588)4254792-1 gnd |
| subject_GND | (DE-588)4254792-1 |
| title | VHDL for engineers |
| title_auth | VHDL for engineers |
| title_exact_search | VHDL for engineers |
| title_full | VHDL for engineers Kenneth L. Short |
| title_fullStr | VHDL for engineers Kenneth L. Short |
| title_full_unstemmed | VHDL for engineers Kenneth L. Short |
| title_short | VHDL for engineers |
| title_sort | vhdl for engineers |
| topic | Dispositifs logiques programmables VHDL (Langage de description de matériel informatique) VHDL (Computer hardware description language) VHDL (DE-588)4254792-1 gnd |
| topic_facet | Dispositifs logiques programmables VHDL (Langage de description de matériel informatique) VHDL (Computer hardware description language) VHDL |
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