Digital VLSI chip design with cadence and synopsys CAD tools:
Saved in:
| Main Author: | |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Boston [u.a.]
Pearson, Addison-Wesley
2010
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| Subjects: | |
| Physical Description: | XVI, 571 S. Ill., graph. Darst. |
| ISBN: | 9780321547996 0321547993 |
Staff View
MARC
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| id | DE-604.BV035562313 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T21:40:29Z |
| institution | BVB |
| isbn | 9780321547996 0321547993 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017618035 |
| oclc_num | 308171006 |
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| owner | DE-29T DE-83 |
| owner_facet | DE-29T DE-83 |
| physical | XVI, 571 S. Ill., graph. Darst. |
| publishDate | 2010 |
| publishDateSearch | 2010 |
| publishDateSort | 2010 |
| publisher | Pearson, Addison-Wesley |
| record_format | marc |
| spelling | Brunvand, Erik Verfasser aut Digital VLSI chip design with cadence and synopsys CAD tools Erik Brunvand Boston [u.a.] Pearson, Addison-Wesley 2010 XVI, 571 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier Integrated circuits Very large scale integration Computer-aided design VLSI (DE-588)4117388-0 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Entwurfsautomation (DE-588)4312536-0 s DE-604 |
| spellingShingle | Brunvand, Erik Digital VLSI chip design with cadence and synopsys CAD tools Integrated circuits Very large scale integration Computer-aided design VLSI (DE-588)4117388-0 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4312536-0 |
| title | Digital VLSI chip design with cadence and synopsys CAD tools |
| title_auth | Digital VLSI chip design with cadence and synopsys CAD tools |
| title_exact_search | Digital VLSI chip design with cadence and synopsys CAD tools |
| title_full | Digital VLSI chip design with cadence and synopsys CAD tools Erik Brunvand |
| title_fullStr | Digital VLSI chip design with cadence and synopsys CAD tools Erik Brunvand |
| title_full_unstemmed | Digital VLSI chip design with cadence and synopsys CAD tools Erik Brunvand |
| title_short | Digital VLSI chip design with cadence and synopsys CAD tools |
| title_sort | digital vlsi chip design with cadence and synopsys cad tools |
| topic | Integrated circuits Very large scale integration Computer-aided design VLSI (DE-588)4117388-0 gnd Entwurfsautomation (DE-588)4312536-0 gnd |
| topic_facet | Integrated circuits Very large scale integration Computer-aided design VLSI Entwurfsautomation |
| work_keys_str_mv | AT brunvanderik digitalvlsichipdesignwithcadenceandsynopsyscadtools |