Planar double-gate transistor: from technology to circuit
Gespeichert in:
| Weitere Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Berlin u.a.
Springer
2009
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | VII, 209 S. 235 mm x 155 mm |
| ISBN: | 9781402093272 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV035562306 | ||
| 003 | DE-604 | ||
| 005 | 20100208 | ||
| 007 | t | ||
| 008 | 090615s2009 gw |||| 00||| eng d | ||
| 015 | |a 08,N39,0847 |2 dnb | ||
| 016 | 7 | |a 990359492 |2 DE-101 | |
| 020 | |a 9781402093272 |c Gb. : EUR 106.95 (freier Pr.), sfr 166.00 (freier Pr.) |9 978-1-402-09327-2 | ||
| 020 | |a 9781402093272 |9 978-1-4020-9327-2 | ||
| 028 | 5 | 2 | |a 11895749 |
| 035 | |a (OCoLC)268798220 | ||
| 035 | |a (DE-599)DNB990359492 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 044 | |a gw |c XA-DE-BE | ||
| 049 | |a DE-91 |a DE-11 | ||
| 050 | 0 | |a TK7871.95 | |
| 082 | 0 | |a 621.3815/28 |2 22 | |
| 084 | |a ZN 4960 |0 (DE-625)157426: |2 rvk | ||
| 084 | |a ELT 315f |2 stub | ||
| 084 | |a 620 |2 sdnb | ||
| 245 | 1 | 0 | |a Planar double-gate transistor |b from technology to circuit |c Amara Amara, Olivier Rozeau, eds. |
| 264 | 1 | |a Berlin u.a. |b Springer |c 2009 | |
| 300 | |a VII, 209 S. |c 235 mm x 155 mm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Metal oxide semiconductor field-effect transistors | |
| 650 | 4 | |a Metal oxide semiconductors, Complementary | |
| 650 | 4 | |a Planar transistors | |
| 650 | 0 | 7 | |a Planartransistor |0 (DE-588)4174786-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Digitale integrierte Schaltung |0 (DE-588)4113313-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a CMOS-Schaltung |0 (DE-588)4148111-2 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a MOS-FET |0 (DE-588)4207266-9 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Analoge integrierte Schaltung |0 (DE-588)4112519-8 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Planartransistor |0 (DE-588)4174786-0 |D s |
| 689 | 0 | 1 | |a MOS-FET |0 (DE-588)4207266-9 |D s |
| 689 | 0 | 2 | |a CMOS-Schaltung |0 (DE-588)4148111-2 |D s |
| 689 | 0 | 3 | |a Analoge integrierte Schaltung |0 (DE-588)4112519-8 |D s |
| 689 | 0 | 4 | |a Digitale integrierte Schaltung |0 (DE-588)4113313-4 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Amara, Amara |4 edt | |
| 856 | 4 | 2 | |m GBV Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017618028&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-017618028 | ||
Datensatz im Suchindex
| _version_ | 1804139211745394688 |
|---|---|
| adam_text | AMARA AMARA * OLIVIER ROZEAU EDITORS PLANAR DOUBLE-GATE TRANSISTOR FROM
TECHNOLOGY TO CIRCUIT SPRINGER CONTENTS INTRODUCTION 1 1 MULTIPLE GATE
TECHNOLOGIES 3 THIERRY POIROUX, MAUD VINET, AND SIMON DELEONIBUS 1.1
INTRODUCTION 3 1.2 ADVANTAGES OF MULTIPLE GATE TECHNOLOGIES 4 1.2.1
REQUIREMENTS FOR FUTURE TECHNOLOGY NODES 4 1.2.2 MOSFET ELECTROSTATICS
CONTROL 6 1.2.3 VARIABILITY 8 1.2.4 GATE STACK 9 1.2.5 CARRIER TRANSPORT
11 1.2.6 SERIES RESISTANCES 11 1.3 PLANAR DOUBLE GATE TECHNOLOGIES 12
1.3.1 DOUBLE GATE TRANSISTORS BY LAYER DEPOSITION 13 1.3.2 NON
SELF-ALIGNED TRANSISTORS BY WAFER BONDING 13 1.3.3 SELF-ALIGNED
TRANSISTORS BY WAFER BONDING 15 1.3.4 SUSPENDED CHANNEL BASED APPROACHES
15 1.4 NON PLANAR MULTIPLE GATE TECHNOLOGIES 16 1.4.1 FINFET DEVICES 17
1.4.2 TRIGATE TRANSISTORS 18 1.4.3 SURROUNDING GATE TRANSISTORS 19 1.5
CONCLUSIONS AND PERSPECTIVES 20 REFERENCES 20 2 COMPACT MODELING OF
INDEPENDENT DOUBLE-GATE MOSFET: A PHYSICAL APPROACH 27 DANIELA MUNTEANU
AND JEAN-LUC AUTRAN 2.1 INTRODUCTION 27 2.2 DRIFT-DIFFUSION DRAIN
CURRENT MODELING 30 2.2.1 2-D POTENTIAL DISTRIBUTION 30 2.2.2 INVERSION
CHARGE CALCULATION 34 V CONTENTS 2.2.3 DRIFT-DIFFUSION DRAIN CURRENT 38
2.2.4 MODEL VALIDATION 39 2.3 BALLISTIC CURRENT IN THE SUBTHRESHOLD
REGIME 42 2.3.1 PHYSICS OF THE BALLISTIC TRANSPORT 42 2.3.2 POTENTIAL
PROFILE IN THE SUBTHRESHOLD REGIME 44 2.3.3 BALLISTIC CURRENT MODELING
45 2.3.4 MODEL VALIDATION 47 2.3.5 DISCUSSION: IMPACT OF THE
SOURCE-TO-DRAIN TUNNELLING CURRENT 48 2.4 CONCLUSION 50 REFERENCES 51
COMPACT MODELING OF DOUBLE GATE MOSFET FOR 1* DESIGN 55 MARINA REYBOZ,
OLIVIER ROZEAU, AND THIERRY POIROUX 3.1 INTRODUCTION 55 3.2 MODELING OF
DOUBLE GATE MOSFET WITH INDEPENDENT DRIVEN GATES 56 3.2.1 CHALLENGE OF
THE SURFACE POTENTIAL BASED MODEL IN COMPACT MODEL FOR 1* DESIGN 56
3.2.2 HOW TO MODEL IDG MODEL WITH A THRESHOLD VOLTAGE BASED MODEL 58 3.3
LONG CHANNEL IDG MOSFET THRESHOLD VOLTAGE BASED MODEL 60 3.3.1
SUBTHRESHOLD SLOPE FACTOR (N) 60 3.3.2 THRESHOLD VOLTAGE MODELING (V,,,)
63 3.3.3 OFFSET VOLTAGE IN STRONG INVERSION {V N JF) 67 3.3.4 DRAIN
SATURATION VOLTAGE 70 3.3.5 THE TRANSCONDUCTANCE BEHAVIOR IN IDG MOS 72
3.3.6 THE DRAIN CONDUCTANCE BEHAVIOR IN IDG MOS 73 3.3.7 MOBILITY 73
3.3.8 CHARGES MODELING 75 3.4 SHORT CHANNEL EFFECTS 77 3.4.1
INTRODUCTION 77 3.4.2 SUBTHRESHOLD SLOPE 79 3.4.3 THRESHOLD VOLTAGE AND
THE SUBTHRESHOLD FACTOR MODELING 80 3.4.4 SHORT CHANNEL EFFECT IN STRONG
INVERSION 82 3.5 CONCLUSION 83 REFERENCES 84 LOW FREQUENCY NOISE IN
DOUBLE-GATE SOI CMOS DEVICES 89 JALAL JOMAAH AND GERARD GHIBAUDO 4.1
INTRODUCTION 89 4.2 LOW FREQUENCY NOISE ANALYSIS 90 4.2.1 CARRIER NUMBER
FLUCTUATIONS AND CORRELATED MOBILITY FLUCTUATIONS 90 4.2.2 HOOGE S
MOBILITY FLUCTUATIONS 91 4.2.3 COUPLING IMPACT ON FLUCTUATIONS 91
CONTENTS VII 4.3 RESULTS AND DISCUSSIONS 93 4.4 CONCLUSION 103
REFERENCES 103 5 ANALOG CIRCUIT DESIGN 105 PHILIPPE FREITAS, DAVID
NAVARRO, IAN O CONNOR, GERARD BILLIOT, HERVE LAPUYADE, AND JEAN-BAPTISTE
BEGUERET 5.1 DOUBLE GATE MOSFET IN ANALOG DESIGN 105 5.1.1 DOUBLE GATE
TRANSISTORS CHARACTERISTICS 106 5.2 CURRENT MIRRORS 109 5.2.1 THRESHOLD
VOLTAGE MODULATION 110 5.2.2 PERFORMANCE TUNABILITY 112 5.3 DIFFERENTIAL
PAIRS 113 5.3.1 BACK GATES IN DIFFERENTIAL MODE 114 5.3.2 BACK GATES IN
COMMON MODE 115 5.4 LOW VOLTAGE OTAS 119 5.4.1 IDGMOS DIFFERENTIAL
CURRENT MIRROR 119 5.4.2 FULLY DIFFERENTIAL IDGMOS LOW VOLTAGE OTA 124
5.5 HIGH SPEED COMPARATORS 133 5.6 CONCLUSION 135 REFERENCES 135 6 LOGIC
CIRCUIT DESIGN WITH DGMOS DEVICES 13 7 IAN O CONNOR, ILHAM HASSOUNE, XI
YANG, AND DAVID NAVARRO 6.1 DGMOS CHARACTERISTICS AND IMPACT ON DIGITAL
DESIGN 137 6.2 STANDARD CELLS USING DGMOS 139 6.2.1 BENCHMARK STRUCTURES
AND SIMULATION CONDITIONS 140 6.2.2 RESULTS ON FDSOI DGMOS TECHNOLOGY
141 6.2.3 SUMMARY 144 6.3 ULTRA LOW POWER FULL-ADDER USING DOUBLE GATE
SOI DEVICES 145 6.3.1 DGMOS NDR DEVICE 145 6.3.2 ULTRA-LOW POWER FULL
ADDER (ULPFA) AND SIMULATION RESULTS IN FDSOI DGMOS TECHNOLOGY 148 6.3.3
SUMMARY 150 6.4 DGMOS DEVICE BASED RECONFIGURABLE CELLS 151 6.4.1
GENERIC M-INPUT RECONFIGURABLE CELL 152 6.4.2 STATIC-LOGIC
RECONFIGURABLE CELL DG-SLRC 154 6.4.3 TESTS WITH TWO-INPUT DG-XLRC 156
6.4.4 COMPARISON TO CONVENTIONAL LUT 159 6.4.5 SUMMARY 164 REFERENCES
164 VIII CONTENTS 7 SRAM CIRCUIT DESIGN 167 BASTIEN GIRAUD, OLIVIER
THOMAS, AMARA AMARA, ANDREI VLADIMIRESCU, AND MARC BELLEVILLE 7.1
INTRODUCTION 167 7.2 SRAM MEMORIES 169 7.2.1 SRAM ARCHITECTURE 169 7.2.2
BASIC OPERATION OF AN SRAM MEMORY 171 7.2.3 SRAM MEMORY CELL DESIGN
PARAMETERS 172 7.3 DOUBLE GATE 6T SRAM MEMORIES 179 7.3.1 DGMOS WITH
TIED GATES 180 7.3.2 INNOVATIVE 6T SRAM CELL ARCHITECTURES 182 7.3.3
SUMMARY AND DISCUSSIONS 193 7.4 DOUBLE GATE 4T & 5T SRAM MEMORIES 195
7.4.1 DGMOS WITH TIED GATES 195 7.4.2 DGMOS WITH INDEPENDENT GATE
BIASING 197 7.4.3 ELECTRICALLY ASYMMETRICAL DGMOS 199 7.4.4 SUMMARY AND
DISCUSSIONS 201 REFERENCES 202 CONCLUSION 205 APPENDIX 207 INDEX 211
|
| any_adam_object | 1 |
| author2 | Amara, Amara |
| author2_role | edt |
| author2_variant | a a aa |
| author_facet | Amara, Amara |
| building | Verbundindex |
| bvnumber | BV035562306 |
| callnumber-first | T - Technology |
| callnumber-label | TK7871 |
| callnumber-raw | TK7871.95 |
| callnumber-search | TK7871.95 |
| callnumber-sort | TK 47871.95 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4960 |
| classification_tum | ELT 315f |
| ctrlnum | (OCoLC)268798220 (DE-599)DNB990359492 |
| dewey-full | 621.3815/28 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815/28 |
| dewey-search | 621.3815/28 |
| dewey-sort | 3621.3815 228 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Maschinenbau / Maschinenwesen Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02202nam a2200553 c 4500</leader><controlfield tag="001">BV035562306</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20100208 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">090615s2009 gw |||| 00||| eng d</controlfield><datafield tag="015" ind1=" " ind2=" "><subfield code="a">08,N39,0847</subfield><subfield code="2">dnb</subfield></datafield><datafield tag="016" ind1="7" ind2=" "><subfield code="a">990359492</subfield><subfield code="2">DE-101</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781402093272</subfield><subfield code="c">Gb. : EUR 106.95 (freier Pr.), sfr 166.00 (freier Pr.)</subfield><subfield code="9">978-1-402-09327-2</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781402093272</subfield><subfield code="9">978-1-4020-9327-2</subfield></datafield><datafield tag="028" ind1="5" ind2="2"><subfield code="a">11895749</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)268798220</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)DNB990359492</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">gw</subfield><subfield code="c">XA-DE-BE</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield><subfield code="a">DE-11</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7871.95</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815/28</subfield><subfield code="2">22</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4960</subfield><subfield code="0">(DE-625)157426:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 315f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">620</subfield><subfield code="2">sdnb</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Planar double-gate transistor</subfield><subfield code="b">from technology to circuit</subfield><subfield code="c">Amara Amara, Olivier Rozeau, eds.</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Berlin u.a.</subfield><subfield code="b">Springer</subfield><subfield code="c">2009</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">VII, 209 S.</subfield><subfield code="c">235 mm x 155 mm</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Metal oxide semiconductor field-effect transistors</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Metal oxide semiconductors, Complementary</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Planar transistors</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Planartransistor</subfield><subfield code="0">(DE-588)4174786-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitale integrierte Schaltung</subfield><subfield code="0">(DE-588)4113313-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CMOS-Schaltung</subfield><subfield code="0">(DE-588)4148111-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">MOS-FET</subfield><subfield code="0">(DE-588)4207266-9</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Analoge integrierte Schaltung</subfield><subfield code="0">(DE-588)4112519-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Planartransistor</subfield><subfield code="0">(DE-588)4174786-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">MOS-FET</subfield><subfield code="0">(DE-588)4207266-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">CMOS-Schaltung</subfield><subfield code="0">(DE-588)4148111-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="3"><subfield code="a">Analoge integrierte Schaltung</subfield><subfield code="0">(DE-588)4112519-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="4"><subfield code="a">Digitale integrierte Schaltung</subfield><subfield code="0">(DE-588)4113313-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Amara, Amara</subfield><subfield code="4">edt</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">GBV Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017618028&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-017618028</subfield></datafield></record></collection> |
| id | DE-604.BV035562306 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T21:40:29Z |
| institution | BVB |
| isbn | 9781402093272 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017618028 |
| oclc_num | 268798220 |
| open_access_boolean | |
| owner | DE-91 DE-BY-TUM DE-11 |
| owner_facet | DE-91 DE-BY-TUM DE-11 |
| physical | VII, 209 S. 235 mm x 155 mm |
| publishDate | 2009 |
| publishDateSearch | 2009 |
| publishDateSort | 2009 |
| publisher | Springer |
| record_format | marc |
| spelling | Planar double-gate transistor from technology to circuit Amara Amara, Olivier Rozeau, eds. Berlin u.a. Springer 2009 VII, 209 S. 235 mm x 155 mm txt rdacontent n rdamedia nc rdacarrier Metal oxide semiconductor field-effect transistors Metal oxide semiconductors, Complementary Planar transistors Planartransistor (DE-588)4174786-0 gnd rswk-swf Digitale integrierte Schaltung (DE-588)4113313-4 gnd rswk-swf CMOS-Schaltung (DE-588)4148111-2 gnd rswk-swf MOS-FET (DE-588)4207266-9 gnd rswk-swf Analoge integrierte Schaltung (DE-588)4112519-8 gnd rswk-swf Planartransistor (DE-588)4174786-0 s MOS-FET (DE-588)4207266-9 s CMOS-Schaltung (DE-588)4148111-2 s Analoge integrierte Schaltung (DE-588)4112519-8 s Digitale integrierte Schaltung (DE-588)4113313-4 s DE-604 Amara, Amara edt GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017618028&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Planar double-gate transistor from technology to circuit Metal oxide semiconductor field-effect transistors Metal oxide semiconductors, Complementary Planar transistors Planartransistor (DE-588)4174786-0 gnd Digitale integrierte Schaltung (DE-588)4113313-4 gnd CMOS-Schaltung (DE-588)4148111-2 gnd MOS-FET (DE-588)4207266-9 gnd Analoge integrierte Schaltung (DE-588)4112519-8 gnd |
| subject_GND | (DE-588)4174786-0 (DE-588)4113313-4 (DE-588)4148111-2 (DE-588)4207266-9 (DE-588)4112519-8 |
| title | Planar double-gate transistor from technology to circuit |
| title_auth | Planar double-gate transistor from technology to circuit |
| title_exact_search | Planar double-gate transistor from technology to circuit |
| title_full | Planar double-gate transistor from technology to circuit Amara Amara, Olivier Rozeau, eds. |
| title_fullStr | Planar double-gate transistor from technology to circuit Amara Amara, Olivier Rozeau, eds. |
| title_full_unstemmed | Planar double-gate transistor from technology to circuit Amara Amara, Olivier Rozeau, eds. |
| title_short | Planar double-gate transistor |
| title_sort | planar double gate transistor from technology to circuit |
| title_sub | from technology to circuit |
| topic | Metal oxide semiconductor field-effect transistors Metal oxide semiconductors, Complementary Planar transistors Planartransistor (DE-588)4174786-0 gnd Digitale integrierte Schaltung (DE-588)4113313-4 gnd CMOS-Schaltung (DE-588)4148111-2 gnd MOS-FET (DE-588)4207266-9 gnd Analoge integrierte Schaltung (DE-588)4112519-8 gnd |
| topic_facet | Metal oxide semiconductor field-effect transistors Metal oxide semiconductors, Complementary Planar transistors Planartransistor Digitale integrierte Schaltung CMOS-Schaltung MOS-FET Analoge integrierte Schaltung |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017618028&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT amaraamara planardoublegatetransistorfromtechnologytocircuit |