Verfügbarkeit: A practical introduction to computer architecture

A practical introduction to computer architecture:

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Bibliographische Detailangaben
1. Verfasser:	Page, Daniel (VerfasserIn)
Format:	Medienkombination Buch
Sprache:	English
Veröffentlicht:	London Springer 2009
Schriftenreihe:	Texts in computer science
Schlagworte:	Computerarchitektur Einführung
Online-Zugang:	Inhaltsverzeichnis
Beschreibung:	XXII, 641 S. Ill., graph. Darst 235 mm x 155 mm
ISBN:	9781848822559 9781848822566

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Datensatz im Suchindex

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adam_text	Contents Parti Tools and Techniques 1 Mathematical Preliminaries ..................................... 3 1.1 Propositions and Predicates .................................. 3 1.1.1 Connectives ......................................... 5 1.1.2 Quantifiers .......................................... 7 1.1.3 Manipulation ........................................ 8 1.2 Sets and Functions ......................................... 10 1.2.1 Construction ........................................ 11 1.2.2 Operations .......................................... 12 1.2.3 Numeric Sets ........................................ 14 1.2.4 Functions ........................................... 14 1.2.5 Relations ........................................... 17 1.3 Boolean Algebra ........................................... 18 1.3.1 Boolean Functions ................................... 21 1.3.2 Normal Forms ....................................... 22 1.4 Number Systems ........................................... 23 1.4.1 Converting Between Bases ............................ 25 1.4.2 Bits, Bytes and Words ................................ 27 1.4.3 Representing Numbers and Characters .................. 29 1.5 Toward a Digital Logic ...................................... 40 1.6 Further Reading ............................................ 41 1.7 Example Questions ......................................... 42 2 Basks of Digital Logic .......................................... 43 2.1 Switches and Transistors .................................... 43 2.1.1 Basic Physics ....................................... 43 2.1.2 Building and Packaging Transistors ..................... 44 2.2 Combinatorial Logic ........................................ 48 2.2.1 Bask Logic Gates .................................... 48 2.2.2 3-state Logic ........................................ 50 Contents XVI 2.2.3 Designing Circuits ................................... 51 2.2.4 Simplifying Circuits .................................. 53 2.2.5 Physical Circuit Properties ............................ 61 2.2.6 Basic Building Blocks ................................ 63 2.3 Clocked and Stateftil Logic .................................. 74 2.3.1 Clocks ............................................. 75 2.3.2 Latches ............................................ 77 2.3.3 Hip-Flops .......................................... 80 2.3.4 State Machines ...................................... 81 2.4 Implementation and Fabrication Technologies ................... 87 2.4.1 Silicon Fabrication ................................... 87 2.4.2 Programmable Logic Arrays ........................... 90 2.4.3 Field Programmable Gate Arrays ....................... 92 2.5 Further Reading ............................................ 93 2.6 Example Questions ......................................... 93 3 Hardware Design Using Verflog.................................. 97 3.1 Introduction ............................................... 97 3.1.1 The Problem of Design Complexity ..................... 97 3.1.2 Design Automation as a Solution ....................... 98 3.2 Structural Design ...........................................100 3.2.1 Modules ............................................100 3.2.2 Wires ..............................................101 3.2.3 Values and Constants .................................103 3.2.4 Comments ..........................................104 3.2.5 Basic Instantiation ...................................105 3.2.6 Nested Instantiation ..................................108 3.2.7 User-Defined Primitives ...............................108 3.3 Higher-level Constructs .....................................109 3.3.1 Continuous Assignments ..............................110 3.3.2 Selection and Concatenation ...........................112 3.3.3 Reduction ..........................................114 3.3.4 Timing and Delays ...................................114 3.4 State and Clocked Design ....................................115 3.4.1 Registers ...........................................115 3.4.2 Processes and Triggers ................................117 3.4.3 Procedural Assignments ..............................118 3.4.4 Timing and Delays ...................................120 3.4.5 Further Behavioural Statements ........................121 3.4.6 Tasks and Functions ..................................126 3.5 Effective Development ......................................127 3.5.1 System Tasks ........................................128 3.5.2 Using the Pre-processor ...............................129 3.5.3 Parameters ..........................................131 3.5.4 Named Port lists ....................................132 Contents xvii 3.5.5 Generate Statements..................................133 3.5.6 Simulation and Stimuli ...............................134 3.6 Further Reading ............................................136 3.7 Example Questions .........................................137 Part Π Processor Design 4 A Historical and Functional Perspective ..........................143 4.1 Introduction ...............................................143 4.2 Special-Purpose Computers ..................................144 4.3 General-Purpose Computers .................................146 4.4 Stored Program Computers ..................................150 4.5 Toward Modern Computers ..................................158 4.5.1 The von Neumann Bottleneck ..........................160 4.5.2 Data-Dependent Control-Flow .........................160 4.5.3 Self-Modifying Programs .............................161 4.6 Further Reading ............................................166 4.7 Example Questions .........................................166 5 Basic Processor Design .........................................169 5.1 A Concrete Stored Program Architecture .......................169 5.1.1 Major Data-path Components ..........................171 5.1.2 Describing Instruction Behaviour .......................174 5.1.3 The Fetch-Decode-Execute Cycle ......................176 5.1.4 Controlling the Data-path .............................176 5.2 Buses ....................................................177 5.2.1 Synchronous Buses ..................................177 5.2.2 Asynchronous Buses .................................178 5.3 Addressing Modes ..........................................179 5.3.1 Immediate Addressing ................................180 5.3.2 Register Addressing ..................................180 5.3.3 Memory Addressing ..................................180 5.4 Instruction Encoding ........................................183 5.4.1 Instruction Selection .................................183 5.4.2 Instruction Formats ..................................186 5.4.3 Basic Encoding and Decoding .........................186 5.4.4 More Complicated Encoding Issues .....................189 5.5 Control-How ..............................................192 5.5.1 Predicated Execution .................................194 5.5.2 Function Calls .......................................197 5.6 Some Design Philosophy ....................................198 5.6.1 Moore s Law ........................................198 5.6.2 RISC versus CISC ...................................199 5.7 Putting It All Together ......................................200 5.8 Further Reading ............................................208 5.9 Example Questions .........................................209 Contents Measuring Performance ........................................213 6.1 Measuring Performance.....................................213 6.1.1 Estimating Execution Time ............................214 6.1.2 Measuring Execution Time ............................216 6.1.3 Benchmark Programs .................................218 6.1.4 Measuring Improvement ..............................219 6.2 Further Reading ............................................220 6.3 Example Questions .........................................220 Arithmetic and Logic ...........................................223 7.1 Introduction ...............................................223 7.2 Comparisons ..............................................224 7.2.1 Unsigned Comparisons ...............................225 7.2.2 Signed Comparisons .................................228 7.3 Addition and Subtraction ....................................228 7.3.1 Addition ............................................228 7.3.2 Subtraction .........................................233 7.4 Shift and Rotate ............................................236 7.4.1 Bit-Serial Shifter .....................................238 7.4.2 Logarithmic Shifter ..................................241 7.5 Multiplication .............................................243 7.5.1 Bit-Serial Multiplier ..................................245 7.5.2 Tree Multiplier ......................................249 7.5.3 Digit-Serial Multiplier ................................250 7.5.4 Early Termination ....................................251 7.5.5 Wallace and Dadda Trees .............................253 7.5.6 Booth Recoding .....................................257 7.6 Putting It All Together ......................................259 7.6.1 Comparison ALU....................................259 7.6.2 Arithmetic ALU.....................................262 7.7 Further Reading ............................................265 7.8 Example Questions .........................................266 Memory and Storage ...........................................269 8.1 Introduction ...............................................269 8.1.1 Historical Memory and Storage ........................271 8.1.2 A Modern Memory Hierarchy .........................277 8.1.3 Basic Organisation and Implementation .................279 8.1.4 Memory Banking ....................................288 8.1.5 Access Locality .....................................290 8.2 Memory and Storage Specifics ...............................291 8.2.1 Static RAM (SRAM) and Dynamic RAM (DRAM) .......291 8.2.2 Non-volatile RAM and ROM ..........................293 8.2.3 Magnetic Disks ......................................294 Contents xix 8.2.4 Optical Disks .......................................296 8.2.5 Error Correction .....................................297 8.3 Basic Cache Memories ......................................300 8.3.1 Fetch Policy ........................................303 8.3.2 Write Policy ........................................304 8.3.3 Direct-Mapped Caches ...............................305 8.3.4 Fully-Associative Caches .............................310 8.3.5 Set-Associative Caches ...............................312 8.3.6 Cache Organisation ..................................315 8.4 Advanced Cache Memories ..................................316 8.4.1 Victim Caches .......................................316 8.4.2 Gated and Drowsy Caches .............................319 8.5 Putting It All Together ......................................321 8.5.1 Register File ........................................322 8.5.2 Main Memory .......................................323 8.5.3 Cache Memory ......................................324 8.6 Further Reading ............................................329 8.7 Example Questions .........................................329 9 Advanced Processor Design .....................................331 9.1 Introduction ...............................................331 9.1.1 A Taxonomy of Parallelism ............................332 9.1.2 Instruction-Level Parallelism (ШР) .....................335 9.2 Pipelined Processors ........................................339 9.2.1 Pipelined Circuits ....................................343 9.2.2 Pipelined Processors .................................347 9.2.3 Pipeline Hazards .....................................350 9.2.4 Stalls and Hazard Resolution ..........................352 9.3 Superscalar Processors ......................................360 9.3.1 Basic Concept .......................................360 9.3.2 Step 1: Scoreboard-based Design .......................361 9.3.3 Step 2: Reservation Station-based Design ................370 9.3.4 Further Improvements ................................378 9.4 Vector Processors ..........................................380 9.4.1 Basic Concept .......................................380 9.4.2 A Dedicated Vector Processor ..........................382 9.4.3 SIMD Within A Register (SWAR) ......................384 9.4.4 Issues of Vectorisation ................................386 9.5 VLIW Processors ..........................................389 9.5.1 BasicConcept .......................................389 9.6 Further Reading ............................................390 9.7 Example Questions .........................................390 Contents XX Part in The Hardware/Software Interface 10 Linkers and Assemblers ........................................ 397 10.1 Introduction ............................................... 397 10.2 The Memory Model ........................................400 10.2.1 Stack Section .......................................401 10.2.2 Static Data Section ...................................402 10.2.3 Dynamic Data Section ................................403 10.3 Executable Versus Object Files ...............................407 10.4 Linkers ................................................... 410 10.4.1 Static and Dynamic Linkage ...........................413 10.4.2 Boot-strap Functions .................................415 10.4.3 Symbol Relocation ...................................416 10.4.4 Symbol Resolution ...................................417 10.5 Assemblers ................................................417 10.5.1 Basic Assembly Language Statements ...................418 10.5.2 Using Machine Instructions ............................420 10.5.3 Using Assembler Aliases ..............................429 10.5.4 Using Assembler Directives ...........................431 10.5.5 Peephole Optimisation ................................434 10.5.6 Some Short Example Programs ........................435 10.5.7 The Forward Referencing Problem ......................439 10.5.8 An Example Assembler ...............................441 10.6 Further Reading ............................................449 10.7 Example Questions .........................................449 11 Compilers .....................................................451 11.1 Introduction ...............................................451 11.2 Compiler Bootstrapping and Re-Hosting .......................453 11.3 Intermediate Representation ..................................454 11.4 Register Allocation .........................................457 11.4.1 An Example Allocation ...............................461 11.4.2 Uses for Pre-colouring ................................463 11.4.3 Avoiding Error Cases via Spilling ......................464 11.5 Instruction Selection and Scheduling ..........................467 11.5.1 Instruction Selection .................................468 11.5.2 Instruction Scheduling ................................470 11.5.3 Scheduling Basic Blocks ..............................470 11.5.4 Scheduling Instructions ...............................471 11.6 Template Code Generation for High-Level Statements ..........473 11.6.1 Conditional Statements ...............................475 11.6.2 Loop Statements .....................................477 11.6.3 Multi-way Branch Statements ..........................478 11.7 Template Code Generation for High-Level Function Calk .......479 11.7.1 Basic Stack Frames ..................................481 Contents xxi 11.7.2 Advanced Stack Frames...............................485 11.8 Further Reading ............................................491 11.9 Example Questions .........................................492 12 Operating Systems .............................................495 12.1 Introduction ...............................................495 12.2 The Hardware/Software Interface .............................497 12.2.1 MPS32 Co-processor Registers ........................497 12.2.2 MIPS32 Processor Modes .............................499 12.2.3 MIPS32 Assembly Language ..........................500 12.3 Boot-Strapping ............................................501 12.4 Event Management .........................................502 12.4.1 Handling Interrupts ..................................503 12.4.2 Handling Exceptions .................................505 12.4.3 Handling Traps ......................................506 12.4.4 An Example Exception Handler ........................510 12.5 Memory Management .......................................511 12.5.1 Basic Concept .......................................512 12.5.2 Pages and Frames ....................................515 12.5.3 Address Translation and Memory Access ................518 12.5.4 Page Eviction and Replacement ........................520 12.5.5 Translation Look-aside Buffer (TLB) ...................521 12.6 Process Management .......................................522 12.6.1 Storing and Switching Process Context ..................523 12.6.2 Process Scheduling ...................................524 12.6.3 An Example Scheduler ...............................529 12.7 Further Reading ............................................533 12.8 Example Questions .........................................534 13 Efficient Programming .........................................535 13.1 Introduction ...............................................535 13.2 Space Conscious Programming .............................536 13.2.1 Reducing Register Pressure ............................536 13.2.2 Reducing Memory Allocation ..........................537 13.3 Time Conscious Programming ..............................540 13.3.1 Effective Short-circuiting .............................540 13.3.2 Branch Elimination ..................................541 13.3.3 Loop Fusion and Fission ..............................542 13.3.4 Loop Unrolling ......................................545 13.3.5 Loop Hoisting .......................................546 13.3.6 Loop Interchange ....................................548 13.3.7 Loop Blocking ......................................549 13.3.8 Function Inlining ....................................551 13.3.9 Software Pipelining ..................................554 13.4 Example Questions .........................................556 xxii Contents Part IV Appendices SPIM: A MPS32 Simulator .........................................561 A.1 Introduction ...............................................561 A.2 Configuring SPIM ..........................................562 A.3 Controlling SPIM ..........................................563 A.4 Example Program Execution .................................565 A.5 Using System Calls .........................................570 Example Solutions ..................................................573 References .........................................................629 Index .............................................................633
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