System level design model with re-use of system IP:
Gespeichert in:
| Format: | Elektronisch E-Book |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Boston
Kluwer Academic Publishers
2003
|
| Schlagworte: | |
| Online-Zugang: | URL des Erstveröffentlichers |
| Beschreibung: | Includes bibliographical references |
| Beschreibung: | 1 Online-Ressource (211 Seiten) Illustrationen 25 cm |
| ISBN: | 0306487330 |
Internformat
MARC
| LEADER | 00000nmm a2200000 c 4500 | ||
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| 003 | DE-604 | ||
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| 008 | 090403s2003 |||| o||u| ||||||eng d | ||
| 020 | |a 0306487330 |c ebk |9 0-306-48733-0 | ||
| 035 | |a (OCoLC)645590700 | ||
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| 050 | 0 | |a TK7895.E42 | |
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| 245 | 1 | 0 | |a System level design model with re-use of system IP |c edited by Patrizia Cavallor, Christophe Gendarm, Klaus Kronlöf, Jean Mermet, J. van Sas, Kari Tiensyrjä, Nikolaos Voros |
| 264 | 1 | |a Boston |b Kluwer Academic Publishers |c 2003 | |
| 300 | |a 1 Online-Ressource (211 Seiten) |b Illustrationen |c 25 cm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Includes bibliographical references | ||
| 533 | |a Online_Ausgabe |b Boulder, Colo |c NetLibrary |d 2004 |f E-Books von NetLibrary |n Sonstige Standardnummer des Gesamttitels: 22382847 |7 s2004 | ||
| 650 | 4 | |a Modularity (Engineering) | |
| 650 | 4 | |a System design | |
| 650 | 4 | |a Systems on a chip - Design and construction | |
| 650 | 4 | |a Modularity (Engineering) | |
| 650 | 4 | |a System design | |
| 650 | 4 | |a Systems on a chip |x Design and construction | |
| 650 | 0 | 7 | |a Formale Spezifikationstechnik |0 (DE-588)4299725-2 |2 gnd |9 rswk-swf |
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| 653 | |a Electronic books | ||
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| 689 | 0 | 2 | |a Formale Spezifikationstechnik |0 (DE-588)4299725-2 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Cavalloro, Patrizia |e Sonstige |4 oth | |
| 700 | 1 | |a Gendarme, Christophe |e Sonstige |4 oth | |
| 700 | 1 | |a Kronlöf, Klaus |e Sonstige |4 oth | |
| 700 | 1 | |a Mermet, Jean |e Sonstige |4 oth | |
| 700 | 1 | |a Sas, J. van |e Sonstige |4 oth | |
| 700 | 1 | |a Tiensyrjä, Kar |e Sonstige |4 oth | |
| 700 | 1 | |a Voros, Nikolaos S. |e Sonstige |0 (DE-588)1173625798 |4 oth | |
| 776 | 0 | 8 | |i Reproduktion von |t System level design model with re-use of system IP |d 2003 |
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Datensatz im Suchindex
| DE-BY-FWS_katkey | 342073 |
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| any_adam_object | |
| author_GND | (DE-588)1173625798 |
| building | Verbundindex |
| bvnumber | BV035413332 |
| callnumber-first | T - Technology |
| callnumber-label | TK7895 |
| callnumber-raw | TK7895.E42 |
| callnumber-search | TK7895.E42 |
| callnumber-sort | TK 47895 E42 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| collection | ZDB-1-NEL ZDB-4-NLEBK |
| ctrlnum | (OCoLC)645590700 (DE-599)GBVNLM003525317 |
| dewey-full | 004.6 |
| dewey-hundreds | 000 - Computer science, information, general works |
| dewey-ones | 004 - Computer science |
| dewey-raw | 004.6 |
| dewey-search | 004.6 |
| dewey-sort | 14.6 |
| dewey-tens | 000 - Computer science, information, general works |
| discipline | Informatik |
| format | Electronic eBook |
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| id | DE-604.BV035413332 |
| illustrated | Not Illustrated |
| indexdate | 2024-08-01T11:39:10Z |
| institution | BVB |
| isbn | 0306487330 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017333857 |
| oclc_num | 645590700 |
| open_access_boolean | |
| owner | DE-12 DE-384 DE-473 DE-BY-UBG DE-824 DE-19 DE-BY-UBM DE-91 DE-BY-TUM DE-739 DE-355 DE-BY-UBR DE-20 DE-706 DE-Aug4 DE-1046 DE-1102 DE-858 DE-1050 DE-1028 DE-573 DE-859 DE-M347 DE-1049 DE-92 DE-863 DE-BY-FWS DE-37 DE-128 DE-22 DE-BY-UBG DE-70 DE-Di1 DE-150 DE-210 DE-521 DE-522 DE-Eb1 DE-898 DE-BY-UBR DE-860 DE-29 DE-703 DE-1043 DE-1047 DE-1051 DE-862 DE-BY-FWS DE-634 DE-2070s DE-155 DE-BY-UBR DE-83 DE-W89 DE-Re13 DE-BY-UBR DE-523 |
| owner_facet | DE-12 DE-384 DE-473 DE-BY-UBG DE-824 DE-19 DE-BY-UBM DE-91 DE-BY-TUM DE-739 DE-355 DE-BY-UBR DE-20 DE-706 DE-Aug4 DE-1046 DE-1102 DE-858 DE-1050 DE-1028 DE-573 DE-859 DE-M347 DE-1049 DE-92 DE-863 DE-BY-FWS DE-37 DE-128 DE-22 DE-BY-UBG DE-70 DE-Di1 DE-150 DE-210 DE-521 DE-522 DE-Eb1 DE-898 DE-BY-UBR DE-860 DE-29 DE-703 DE-1043 DE-1047 DE-1051 DE-862 DE-BY-FWS DE-634 DE-2070s DE-155 DE-BY-UBR DE-83 DE-W89 DE-Re13 DE-BY-UBR DE-523 |
| physical | 1 Online-Ressource (211 Seiten) Illustrationen 25 cm |
| psigel | ZDB-1-NEL ZDB-4-NLEBK |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | Kluwer Academic Publishers |
| record_format | marc |
| spellingShingle | System level design model with re-use of system IP Modularity (Engineering) System design Systems on a chip - Design and construction Systems on a chip Design and construction Formale Spezifikationstechnik (DE-588)4299725-2 gnd Eingebettetes System (DE-588)4396978-1 gnd Hardwareentwurf (DE-588)4159103-3 gnd |
| subject_GND | (DE-588)4299725-2 (DE-588)4396978-1 (DE-588)4159103-3 |
| title | System level design model with re-use of system IP |
| title_auth | System level design model with re-use of system IP |
| title_exact_search | System level design model with re-use of system IP |
| title_full | System level design model with re-use of system IP edited by Patrizia Cavallor, Christophe Gendarm, Klaus Kronlöf, Jean Mermet, J. van Sas, Kari Tiensyrjä, Nikolaos Voros |
| title_fullStr | System level design model with re-use of system IP edited by Patrizia Cavallor, Christophe Gendarm, Klaus Kronlöf, Jean Mermet, J. van Sas, Kari Tiensyrjä, Nikolaos Voros |
| title_full_unstemmed | System level design model with re-use of system IP edited by Patrizia Cavallor, Christophe Gendarm, Klaus Kronlöf, Jean Mermet, J. van Sas, Kari Tiensyrjä, Nikolaos Voros |
| title_short | System level design model with re-use of system IP |
| title_sort | system level design model with re use of system ip |
| topic | Modularity (Engineering) System design Systems on a chip - Design and construction Systems on a chip Design and construction Formale Spezifikationstechnik (DE-588)4299725-2 gnd Eingebettetes System (DE-588)4396978-1 gnd Hardwareentwurf (DE-588)4159103-3 gnd |
| topic_facet | Modularity (Engineering) System design Systems on a chip - Design and construction Systems on a chip Design and construction Formale Spezifikationstechnik Eingebettetes System Hardwareentwurf |
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