Retargetable processor system integration into multi-processor system-on-chip platforms:
Gespeichert in:
1. Verfasser: | |
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Format: | Abschlussarbeit Buch |
Sprache: | English |
Veröffentlicht: |
2007
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Schlagworte: | |
Beschreibung: | XIV, 162 S. graph. Darst. |
Internformat
MARC
LEADER | 00000nam a2200000 c 4500 | ||
---|---|---|---|
001 | BV035300088 | ||
003 | DE-604 | ||
005 | 00000000000000.0 | ||
007 | t | ||
008 | 090209s2007 d||| m||| 00||| eng d | ||
035 | |a (OCoLC)553048681 | ||
035 | |a (DE-599)BVBBV035300088 | ||
040 | |a DE-604 |b ger |e rakwb | ||
041 | 0 | |a eng | |
049 | |a DE-91 | ||
100 | 1 | |a Wieferink, Andreas |d 1972- |e Verfasser |0 (DE-588)135976855 |4 aut | |
245 | 1 | 0 | |a Retargetable processor system integration into multi-processor system-on-chip platforms |c vorgelegt von Andreas Wieferink |
264 | 1 | |c 2007 | |
300 | |a XIV, 162 S. |b graph. Darst. | ||
336 | |b txt |2 rdacontent | ||
337 | |b n |2 rdamedia | ||
338 | |b nc |2 rdacarrier | ||
502 | |a Aachen, Techn. Hochsch., Diss., 2007 | ||
650 | 4 | |a Entwurfsautomation ; IND: s | |
650 | 4 | |a Integrierte Schaltung ; IND: s | |
650 | 4 | |a Mikroprozessor ; IND: s | |
650 | 4 | |a System-on-Chip ; IND: s | |
650 | 4 | |a System-on-Chip - Mehrprozessorsystem - Entwurfsautomation | |
650 | 4 | |a System-on-Chip - Mehrprozessorsystem - Systemplattform | |
650 | 0 | 7 | |a Systemplattform |0 (DE-588)4674460-5 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a System-on-Chip |0 (DE-588)4740357-3 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Entwurfsautomation |0 (DE-588)4312536-0 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Mehrprozessorsystem |0 (DE-588)4038397-0 |2 gnd |9 rswk-swf |
655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
689 | 0 | 0 | |a System-on-Chip |0 (DE-588)4740357-3 |D s |
689 | 0 | 1 | |a Mehrprozessorsystem |0 (DE-588)4038397-0 |D s |
689 | 0 | 2 | |a Entwurfsautomation |0 (DE-588)4312536-0 |D s |
689 | 0 | |5 DE-604 | |
689 | 1 | 0 | |a System-on-Chip |0 (DE-588)4740357-3 |D s |
689 | 1 | 1 | |a Mehrprozessorsystem |0 (DE-588)4038397-0 |D s |
689 | 1 | 2 | |a Systemplattform |0 (DE-588)4674460-5 |D s |
689 | 1 | |5 DE-604 | |
999 | |a oai:aleph.bib-bvb.de:BVB01-017104966 |
Datensatz im Suchindex
_version_ | 1804138600072216576 |
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any_adam_object | |
author | Wieferink, Andreas 1972- |
author_GND | (DE-588)135976855 |
author_facet | Wieferink, Andreas 1972- |
author_role | aut |
author_sort | Wieferink, Andreas 1972- |
author_variant | a w aw |
building | Verbundindex |
bvnumber | BV035300088 |
ctrlnum | (OCoLC)553048681 (DE-599)BVBBV035300088 |
format | Thesis Book |
fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01819nam a2200481 c 4500</leader><controlfield tag="001">BV035300088</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">090209s2007 d||| m||| 00||| eng d</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)553048681</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV035300088</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Wieferink, Andreas</subfield><subfield code="d">1972-</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)135976855</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Retargetable processor system integration into multi-processor system-on-chip platforms</subfield><subfield code="c">vorgelegt von Andreas Wieferink</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2007</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XIV, 162 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="502" ind1=" " ind2=" "><subfield code="a">Aachen, Techn. Hochsch., Diss., 2007</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Entwurfsautomation ; IND: s</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrierte Schaltung ; IND: s</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Mikroprozessor ; IND: s</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">System-on-Chip ; IND: s</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">System-on-Chip - Mehrprozessorsystem - Entwurfsautomation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">System-on-Chip - Mehrprozessorsystem - Systemplattform</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Systemplattform</subfield><subfield code="0">(DE-588)4674460-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">System-on-Chip</subfield><subfield code="0">(DE-588)4740357-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurfsautomation</subfield><subfield code="0">(DE-588)4312536-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Mehrprozessorsystem</subfield><subfield code="0">(DE-588)4038397-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)4113937-9</subfield><subfield code="a">Hochschulschrift</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">System-on-Chip</subfield><subfield code="0">(DE-588)4740357-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Mehrprozessorsystem</subfield><subfield code="0">(DE-588)4038397-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">Entwurfsautomation</subfield><subfield code="0">(DE-588)4312536-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">System-on-Chip</subfield><subfield code="0">(DE-588)4740357-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Mehrprozessorsystem</subfield><subfield code="0">(DE-588)4038397-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="2"><subfield code="a">Systemplattform</subfield><subfield code="0">(DE-588)4674460-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-017104966</subfield></datafield></record></collection> |
genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
genre_facet | Hochschulschrift |
id | DE-604.BV035300088 |
illustrated | Illustrated |
indexdate | 2024-07-09T21:30:46Z |
institution | BVB |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017104966 |
oclc_num | 553048681 |
open_access_boolean | |
owner | DE-91 DE-BY-TUM |
owner_facet | DE-91 DE-BY-TUM |
physical | XIV, 162 S. graph. Darst. |
publishDate | 2007 |
publishDateSearch | 2007 |
publishDateSort | 2007 |
record_format | marc |
spelling | Wieferink, Andreas 1972- Verfasser (DE-588)135976855 aut Retargetable processor system integration into multi-processor system-on-chip platforms vorgelegt von Andreas Wieferink 2007 XIV, 162 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Aachen, Techn. Hochsch., Diss., 2007 Entwurfsautomation ; IND: s Integrierte Schaltung ; IND: s Mikroprozessor ; IND: s System-on-Chip ; IND: s System-on-Chip - Mehrprozessorsystem - Entwurfsautomation System-on-Chip - Mehrprozessorsystem - Systemplattform Systemplattform (DE-588)4674460-5 gnd rswk-swf System-on-Chip (DE-588)4740357-3 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf Mehrprozessorsystem (DE-588)4038397-0 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content System-on-Chip (DE-588)4740357-3 s Mehrprozessorsystem (DE-588)4038397-0 s Entwurfsautomation (DE-588)4312536-0 s DE-604 Systemplattform (DE-588)4674460-5 s |
spellingShingle | Wieferink, Andreas 1972- Retargetable processor system integration into multi-processor system-on-chip platforms Entwurfsautomation ; IND: s Integrierte Schaltung ; IND: s Mikroprozessor ; IND: s System-on-Chip ; IND: s System-on-Chip - Mehrprozessorsystem - Entwurfsautomation System-on-Chip - Mehrprozessorsystem - Systemplattform Systemplattform (DE-588)4674460-5 gnd System-on-Chip (DE-588)4740357-3 gnd Entwurfsautomation (DE-588)4312536-0 gnd Mehrprozessorsystem (DE-588)4038397-0 gnd |
subject_GND | (DE-588)4674460-5 (DE-588)4740357-3 (DE-588)4312536-0 (DE-588)4038397-0 (DE-588)4113937-9 |
title | Retargetable processor system integration into multi-processor system-on-chip platforms |
title_auth | Retargetable processor system integration into multi-processor system-on-chip platforms |
title_exact_search | Retargetable processor system integration into multi-processor system-on-chip platforms |
title_full | Retargetable processor system integration into multi-processor system-on-chip platforms vorgelegt von Andreas Wieferink |
title_fullStr | Retargetable processor system integration into multi-processor system-on-chip platforms vorgelegt von Andreas Wieferink |
title_full_unstemmed | Retargetable processor system integration into multi-processor system-on-chip platforms vorgelegt von Andreas Wieferink |
title_short | Retargetable processor system integration into multi-processor system-on-chip platforms |
title_sort | retargetable processor system integration into multi processor system on chip platforms |
topic | Entwurfsautomation ; IND: s Integrierte Schaltung ; IND: s Mikroprozessor ; IND: s System-on-Chip ; IND: s System-on-Chip - Mehrprozessorsystem - Entwurfsautomation System-on-Chip - Mehrprozessorsystem - Systemplattform Systemplattform (DE-588)4674460-5 gnd System-on-Chip (DE-588)4740357-3 gnd Entwurfsautomation (DE-588)4312536-0 gnd Mehrprozessorsystem (DE-588)4038397-0 gnd |
topic_facet | Entwurfsautomation ; IND: s Integrierte Schaltung ; IND: s Mikroprozessor ; IND: s System-on-Chip ; IND: s System-on-Chip - Mehrprozessorsystem - Entwurfsautomation System-on-Chip - Mehrprozessorsystem - Systemplattform Systemplattform System-on-Chip Entwurfsautomation Mehrprozessorsystem Hochschulschrift |
work_keys_str_mv | AT wieferinkandreas retargetableprocessorsystemintegrationintomultiprocessorsystemonchipplatforms |