Mixed signal circuit verification using symbolic model checking techniques:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Buch |
| Sprache: | German |
| Veröffentlicht: |
München
Verl. Dr. Hut
2008
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| Ausgabe: | 1. Aufl. |
| Schriftenreihe: | Informatik
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXVI, 202 S. Ill., graph. Darst. 21 cm, 351 gr. |
| ISBN: | 9783899638417 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV035294046 | ||
| 003 | DE-604 | ||
| 005 | 20100219 | ||
| 007 | t | ||
| 008 | 090205s2008 ad|| m||| 00||| ger d | ||
| 016 | 7 | |a 992162858 |2 DE-101 | |
| 020 | |a 9783899638417 |c kart. : EUR 45.00 |9 978-3-89963-841-7 | ||
| 024 | 3 | |a 9783899638417 | |
| 035 | |a (OCoLC)436274450 | ||
| 035 | |a (DE-599)DNB992162858 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a ger | |
| 049 | |a DE-12 |a DE-91G | ||
| 082 | 0 | |a 621.381548 |2 22/ger | |
| 084 | |a 620 |2 sdnb | ||
| 084 | |a ELT 343d |2 stub | ||
| 100 | 1 | |a Jesser, Alexander |d 1974- |e Verfasser |0 (DE-588)136678084 |4 aut | |
| 245 | 1 | 0 | |a Mixed signal circuit verification using symbolic model checking techniques |c von Alexander Jesser |
| 250 | |a 1. Aufl. | ||
| 264 | 1 | |a München |b Verl. Dr. Hut |c 2008 | |
| 300 | |a XXVI, 202 S. |b Ill., graph. Darst. |c 21 cm, 351 gr. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Informatik | |
| 502 | |a Zugl.: Frankfurt (Main), Univ., Diss., 2008 | ||
| 650 | 4 | |a Mixed-Signal-Schaltung - Model Checking | |
| 650 | 0 | 7 | |a Model Checking |0 (DE-588)4434799-6 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Mixed-Signal-Schaltung |0 (DE-588)4756481-7 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
| 689 | 0 | 0 | |a Mixed-Signal-Schaltung |0 (DE-588)4756481-7 |D s |
| 689 | 0 | 1 | |a Model Checking |0 (DE-588)4434799-6 |D s |
| 689 | 0 | |5 DE-604 | |
| 856 | 4 | 2 | |m DNB Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017099042&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-017099042 | ||
Datensatz im Suchindex
| _version_ | 1804138591656345600 |
|---|---|
| adam_text | TABLE OF CONTENTS LIST OF FIGURES XV LIST OF TABLES XIX LIST OF
ALGORITHMS XXI LIST OF SYMBOLS AND ABBREVIATIONS XXIII 1 INTRODUCTION 1
1.1 FUNDAMENTALS OF HARDWARE DESIGN VALIDATION 4 1.2 GOAL OF THIS WORK 7
1.3 ORGANIZATION 9 2 MODEL CHECKING PRELIMINARIES 11 2.1 AUTOMATA
APPROACH.ES 11 2.2 PROPERTY SPOCIFICATIONS AND LOGICS 19 2.2.1 TEMPORAL
LOGICS 19 2.2.2 LINEAR TEMPORAL LOGIC 20 2.2.3 BRANDUNG TIME LOGIC 22
2.2.4 EXPRESSIVENESS 20 2.2.5 FAST SPECIFICATION MODALITIES 27 2.3
SYMBOLIC CTL MODEL CHECKING 27 2.3.1 STATE SPACE TRAVERSAL 28 2.3.2
QUANTIFICATION SCHEDULING 33 2.3.2.1 PARTITIONING THE TRANSITION
RELATION 33 2.3.2.2 SPLITTING 34 2.3.3 CHECKING CTL FORMULAS 34 2.3.3.1
FIXPOINT COMPUTATION 36 2.3.3.2 SYMBOLIC MODEL CHECKING ALGORITHMS 37
2.3.3.3 COUNTEREXAMPLE GENERATION 39 2.3.4 COMPLEXITY ANALYSIS 39
BIBLIOGRAFISCHE INFORMATIONEN HTTP://D-NB.INFO/992162858 DIGITALISIERT
DURCH TADLE OF CONTENTS 2.4 SYMBOLIC REPRESENTATIONS 40 2.4.1 BHIARY
DECISION DIAGRAMS 41 2.4.1.1 COMPLEXITY OF BINARY DECISION DIAGRAMS 45
2.4.2 MULTI TERMINAL BINARY DECISION DIAGRAMS 46 2.4.3 VARIANTS OF
BINAI-Y DECISION DIAGRAMS 48 3 HYBRID SYSTEM VERIFICATION AT A GLANCE 49
3.1 REAL TIME SYSTEMS 49 3.1.1 TIMED AUTOMATA 49 3.2 DEFINITION OF
HYBRID SYSTEMS 51 3.3 HYBRID SYSTEM MODEIMG 54 3.3.1 HYBRID AUTOMATA 54
3.3.2 HYBRID PETRI NETS 56 3.4 COMPLEXITY ANALYSIS 58 3.5 HYBRID SYSTEM
VERIFICATION TOOLS 58 3.5.1 MIXED-SIGNAL MODEL CHECKING TOOLS 60 4
MODELING MIXED-SIGNAL CIRCUITS 63 4.1 MIXED-SIGNAL SYSTEM DECOMPOSITION
63 4.2 ANALOG STATE SPACE DISCRETIZATION 65 4.2.1 TRANSITION TIME
APPROXIMATION 69 4.2.2 ANALOG INPUT REPRAESENTATION 70 4.2.3 ANALOG
FIXPOINTS 70 4.3 SYMBOLIC TIMED TRANSITION REPRESENTATION 70 4.4
COMPUTATIONAL DATASTRUCTURE 74 4.4.1 REAL TIMED TRANSITION
REPRESENTATION 75 4.5 SYMBOLIC ANALOG STATE SPACE REPRESENTATION 78
4.5.1 HYPER-BOX ENCODING 78 4.0 DIGITAL STATE SPACE REPRESENTATION 80
4.7 MIXED-SIGNAL STATE SPACE REPRESENTATION 83 4.8 GENERATION OF
TRANSITION MTBDDS 85 4.9 CONFLATION OF TRANSITION MTBDDS 87 4.9.1
TRANSITION DELAY TIME ABSTRACTION 88 4.9.2 CONFLATING STUTTERED
TRANSITION MTBDDS 93 4.9.3 RUN TIME ANALYSIS 94 5 TADLE OF CONTENTS 5.2
CTL-AMS EVALUATION 100 5.2.1 DIGITAL EVALUATION 109 5.2.2 ANALOG
EVALUATION 114 5.3 MIXED-SIGNAL MODEL CHECKING STRATEGIES 120 5.3.1
PARTITIONED VERIFICATION ANALYSIS 120 5.3.2 MODEL CHECKING OF CONFLATED
TRANSITION MTBDDS 134 5.4 RUN TIME ANALYSIS 134 5.4.1 CONFLATED
TRANSITION MTBDD ANALYSIS 138 5.5 MODEL CHECKING FLOWS 141 5.5.1
PARTIT.IONED TRANSITION STRATEGY 142 5.5.2 CONFLATED TRANSITION STRATEGY
143 6 EXPERIMENTAL RESULTS 145 0.1 EXPERIMENTAL ENVIRONMENT 145 0.2
A/S-MODULATOR 146 6.2.1 VERIFICATION RESULTS 151 6.2.2 RUN TIME ANALYSIS
154 6.2.2.1 DISCRETIZATION EFFORT 154 0.2.2.2 PARTITIONED VS. CONFLATED
TRANSITION STRATEGY 158 0.2.2.3 CONFLATED TRANSITION STRATEGY
INVESTIGATIONS 160 6.3 PHASE LOCKET! LOOP 102 G.3.1 VERIFICATION RESULTS
160 6.3.2 RUN TIME ANALYSIS 168 6.3.3 LOOSELY COUPLED LOOP 169 0.4 FINAL
REMARKS 170 7 CONCLUSION 175 7.1 SUMMARY 175 7.2 FUTURE RESEARCH
DIRECTIONS 177 A APPENDIX A 179 A.L CTL-AMS EQUIVALENCES 179 A.2 PAST
TIME EQUIVALENCES 181 BIBLIOGRAPHY 184 INDEX 199
|
| any_adam_object | 1 |
| author | Jesser, Alexander 1974- |
| author_GND | (DE-588)136678084 |
| author_facet | Jesser, Alexander 1974- |
| author_role | aut |
| author_sort | Jesser, Alexander 1974- |
| author_variant | a j aj |
| building | Verbundindex |
| bvnumber | BV035294046 |
| classification_tum | ELT 343d |
| ctrlnum | (OCoLC)436274450 (DE-599)DNB992162858 |
| dewey-full | 621.381548 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.381548 |
| dewey-search | 621.381548 |
| dewey-sort | 3621.381548 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Maschinenbau / Maschinenwesen Elektrotechnik Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 1. Aufl. |
| format | Thesis Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01743nam a2200445 c 4500</leader><controlfield tag="001">BV035294046</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20100219 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">090205s2008 ad|| m||| 00||| ger d</controlfield><datafield tag="016" ind1="7" ind2=" "><subfield code="a">992162858</subfield><subfield code="2">DE-101</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9783899638417</subfield><subfield code="c">kart. : EUR 45.00</subfield><subfield code="9">978-3-89963-841-7</subfield></datafield><datafield tag="024" ind1="3" ind2=" "><subfield code="a">9783899638417</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)436274450</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)DNB992162858</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">ger</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-12</subfield><subfield code="a">DE-91G</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.381548</subfield><subfield code="2">22/ger</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">620</subfield><subfield code="2">sdnb</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ELT 343d</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Jesser, Alexander</subfield><subfield code="d">1974-</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)136678084</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Mixed signal circuit verification using symbolic model checking techniques</subfield><subfield code="c">von Alexander Jesser</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">1. Aufl.</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">München</subfield><subfield code="b">Verl. Dr. Hut</subfield><subfield code="c">2008</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXVI, 202 S.</subfield><subfield code="b">Ill., graph. Darst.</subfield><subfield code="c">21 cm, 351 gr.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">Informatik</subfield></datafield><datafield tag="502" ind1=" " ind2=" "><subfield code="a">Zugl.: Frankfurt (Main), Univ., Diss., 2008</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Mixed-Signal-Schaltung - Model Checking</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Model Checking</subfield><subfield code="0">(DE-588)4434799-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Mixed-Signal-Schaltung</subfield><subfield code="0">(DE-588)4756481-7</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="655" ind1=" " ind2="7"><subfield code="0">(DE-588)4113937-9</subfield><subfield code="a">Hochschulschrift</subfield><subfield code="2">gnd-content</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Mixed-Signal-Schaltung</subfield><subfield code="0">(DE-588)4756481-7</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Model Checking</subfield><subfield code="0">(DE-588)4434799-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">DNB Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017099042&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-017099042</subfield></datafield></record></collection> |
| genre | (DE-588)4113937-9 Hochschulschrift gnd-content |
| genre_facet | Hochschulschrift |
| id | DE-604.BV035294046 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T21:30:38Z |
| institution | BVB |
| isbn | 9783899638417 |
| language | German |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017099042 |
| oclc_num | 436274450 |
| open_access_boolean | |
| owner | DE-12 DE-91G DE-BY-TUM |
| owner_facet | DE-12 DE-91G DE-BY-TUM |
| physical | XXVI, 202 S. Ill., graph. Darst. 21 cm, 351 gr. |
| publishDate | 2008 |
| publishDateSearch | 2008 |
| publishDateSort | 2008 |
| publisher | Verl. Dr. Hut |
| record_format | marc |
| series2 | Informatik |
| spelling | Jesser, Alexander 1974- Verfasser (DE-588)136678084 aut Mixed signal circuit verification using symbolic model checking techniques von Alexander Jesser 1. Aufl. München Verl. Dr. Hut 2008 XXVI, 202 S. Ill., graph. Darst. 21 cm, 351 gr. txt rdacontent n rdamedia nc rdacarrier Informatik Zugl.: Frankfurt (Main), Univ., Diss., 2008 Mixed-Signal-Schaltung - Model Checking Model Checking (DE-588)4434799-6 gnd rswk-swf Mixed-Signal-Schaltung (DE-588)4756481-7 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Mixed-Signal-Schaltung (DE-588)4756481-7 s Model Checking (DE-588)4434799-6 s DE-604 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017099042&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Jesser, Alexander 1974- Mixed signal circuit verification using symbolic model checking techniques Mixed-Signal-Schaltung - Model Checking Model Checking (DE-588)4434799-6 gnd Mixed-Signal-Schaltung (DE-588)4756481-7 gnd |
| subject_GND | (DE-588)4434799-6 (DE-588)4756481-7 (DE-588)4113937-9 |
| title | Mixed signal circuit verification using symbolic model checking techniques |
| title_auth | Mixed signal circuit verification using symbolic model checking techniques |
| title_exact_search | Mixed signal circuit verification using symbolic model checking techniques |
| title_full | Mixed signal circuit verification using symbolic model checking techniques von Alexander Jesser |
| title_fullStr | Mixed signal circuit verification using symbolic model checking techniques von Alexander Jesser |
| title_full_unstemmed | Mixed signal circuit verification using symbolic model checking techniques von Alexander Jesser |
| title_short | Mixed signal circuit verification using symbolic model checking techniques |
| title_sort | mixed signal circuit verification using symbolic model checking techniques |
| topic | Mixed-Signal-Schaltung - Model Checking Model Checking (DE-588)4434799-6 gnd Mixed-Signal-Schaltung (DE-588)4756481-7 gnd |
| topic_facet | Mixed-Signal-Schaltung - Model Checking Model Checking Mixed-Signal-Schaltung Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017099042&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT jesseralexander mixedsignalcircuitverificationusingsymbolicmodelcheckingtechniques |