Development of a fast DRAM analyzer and measurement of typical and critical memory access sequences in applications:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
München
Verl. Dr. Hut
2008
|
| Ausgabe: | 1. Aufl. |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | VIII, 119 S. graph. Darst. 24 cm, 264 gr. |
| ISBN: | 9783899638882 |
Internformat
MARC
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| 003 | DE-604 | ||
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| 016 | 7 | |a 992163323 |2 DE-101 | |
| 020 | |a 9783899638882 |c kart. : EUR 66.00 |9 978-3-89963-888-2 | ||
| 024 | 3 | |a 9783899638882 | |
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| 100 | 1 | |a Albert, Simon |d 1977- |e Verfasser |0 (DE-588)137176066 |4 aut | |
| 245 | 1 | 0 | |a Development of a fast DRAM analyzer and measurement of typical and critical memory access sequences in applications |c Simon Albert |
| 250 | |a 1. Aufl. | ||
| 264 | 1 | |a München |b Verl. Dr. Hut |c 2008 | |
| 300 | |a VIII, 119 S. |b graph. Darst. |c 24 cm, 264 gr. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 502 | |a Zugl.: München, Techn. Univ., Diss., 2008 | ||
| 650 | 4 | |a SDRAM - Leistungsbewertung - Speicherzugriff | |
| 650 | 0 | 7 | |a Leistungsbewertung |0 (DE-588)4167271-9 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a SDRAM |0 (DE-588)7663868-6 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Speicherzugriff |0 (DE-588)4182148-8 |2 gnd |9 rswk-swf |
| 655 | 7 | |0 (DE-588)4113937-9 |a Hochschulschrift |2 gnd-content | |
| 689 | 0 | 0 | |a SDRAM |0 (DE-588)7663868-6 |D s |
| 689 | 0 | 1 | |a Leistungsbewertung |0 (DE-588)4167271-9 |D s |
| 689 | 0 | 2 | |a Speicherzugriff |0 (DE-588)4182148-8 |D s |
| 689 | 0 | |5 DE-604 | |
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| 999 | |a oai:aleph.bib-bvb.de:BVB01-017086263 | ||
Datensatz im Suchindex
| _version_ | 1804138573403783168 |
|---|---|
| adam_text | CONTENTS 1 INTRODUCTION 1 1.1 EVOLUTION OF COMPUTER SYSTEMS 1 1.2
OUTLINE 2 2 MEMORY SYSTEMS 5 2.1 MEMORY HIERARCHIES 5 2.2 RANDOM ACCESS
ELECTRICALLY REWRITABLE MEMORY 5 2.2.1 SRAM 7 2.2.2 FLASH MEMORY 7 2.2.3
SDRAM 8 2.3 HITTING THE MEMORY WALL 8 2.4 COMPUTER SYSTEM ARCHITECTURE 9
2.4.1 MODERN COMPUTER SYSTEMS 9 2.4.2 OPERATION MODES OF DDR-SDRAM 13
2.4.3 OPTIONS FOR SDRAM CONTROLLERS 20 3 EVALUATION OF MEMORY ACCESS
SEQUENCES 25 3.1 EXECUTION DRIVEN SIMULATION 26 3.2 TTACE DRIVEN
SIMULATION 28 3.3 MEASUREMENT 30 4 MEASUREMENT HARDWARE 33 4.1 OVERVIEW
33 4.1.1 PROBE HEAD 33 4.1.2 FPGA BOARD 33 4.1.3 PC BACKEND 41 4.1.4
EXTERNAL TRIGGERING 43 4.2 VERIFICATION 43 5 DRAM PERFORMANCE ANALYSIS
45 5.1 CRITICAL DRAM TIMINGS 45 BIBLIOGRAFISCHE INFORMATIONEN
HTTP://D-NB.INFO/992163323 DIGITALISIERT DURCH II CONTENTS 5.1.1
METHODOLOGY 46 5.1.2 RESULTS 48 5.1.3 PERFORMANCE LIMITATIONS OF FUTURE
MEMORY SYSTEMS 52 5.2 STATISTICAL MODELLING OF SDRAM PARAMETER CHANGES
53 5.2.1 CHANGING SDRAM TIMINGS 53 5.2.2 CHANGING THE SDRAM OPERATION
FREQUENCY 62 5.2.3 ESTIMATING INTERCOMMAND SPACING 71 6 REPRODUCIBILITY
79 6.1 DEVIATION OF KEY FIGURES 81 6.2 LOCAL DISTRIBUTION OF ACCESSES 85
6.3 REPRODUCIBILITY AND SDRAM TIMINGS 90 7 CONCLUSION 95 7.1 SUMMARY 95
7.2 LIMITATIONS 97 7.3 RELATEDWORK 98 7.4 EXTENSIONS AND FUTURE WORK 99
A DRAM TIMINGS 103 A.L INTRA BANK TIMINGS 103 A.1.1 RAS TO CAS DELAY (T
RCD ) 103 A.L.2 CAS LATENCY (CL) 103 A.1.3 ROW ACTIVE STROBE (TJWS) 105
A.1.4 ROW PRECHARGE TIME (T RP ) 105 A.1.5 ROW CYCLE TIME (T RC ) 105
A.1.6 WRITE TO READ DELAY {TWTR 105 A.L.7 WRITE RECOVERY TIME (T WR )
105 A.1.8 REFRESH CYCLE TIME (WC) 105 A.2 INTER BANK TIMINGS 105 A.2.1
CAS TO CAS DELAY {TCCUE) CONTENTS III C CALCULATIONS 111
|
| any_adam_object | 1 |
| author | Albert, Simon 1977- |
| author_GND | (DE-588)137176066 |
| author_facet | Albert, Simon 1977- |
| author_role | aut |
| author_sort | Albert, Simon 1977- |
| author_variant | s a sa |
| building | Verbundindex |
| bvnumber | BV035281051 |
| ctrlnum | (OCoLC)427644336 (DE-599)DNB992163323 |
| dewey-full | 621.3973 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3973 |
| dewey-search | 621.3973 |
| dewey-sort | 3621.3973 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Maschinenbau / Maschinenwesen Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 1. Aufl. |
| format | Thesis Book |
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| id | DE-604.BV035281051 |
| illustrated | Illustrated |
| indexdate | 2024-07-09T21:30:20Z |
| institution | BVB |
| isbn | 9783899638882 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-017086263 |
| oclc_num | 427644336 |
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| physical | VIII, 119 S. graph. Darst. 24 cm, 264 gr. |
| publishDate | 2008 |
| publishDateSearch | 2008 |
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| publisher | Verl. Dr. Hut |
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| spelling | Albert, Simon 1977- Verfasser (DE-588)137176066 aut Development of a fast DRAM analyzer and measurement of typical and critical memory access sequences in applications Simon Albert 1. Aufl. München Verl. Dr. Hut 2008 VIII, 119 S. graph. Darst. 24 cm, 264 gr. txt rdacontent n rdamedia nc rdacarrier Zugl.: München, Techn. Univ., Diss., 2008 SDRAM - Leistungsbewertung - Speicherzugriff Leistungsbewertung (DE-588)4167271-9 gnd rswk-swf SDRAM (DE-588)7663868-6 gnd rswk-swf Speicherzugriff (DE-588)4182148-8 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content SDRAM (DE-588)7663868-6 s Leistungsbewertung (DE-588)4167271-9 s Speicherzugriff (DE-588)4182148-8 s DE-604 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017086263&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Albert, Simon 1977- Development of a fast DRAM analyzer and measurement of typical and critical memory access sequences in applications SDRAM - Leistungsbewertung - Speicherzugriff Leistungsbewertung (DE-588)4167271-9 gnd SDRAM (DE-588)7663868-6 gnd Speicherzugriff (DE-588)4182148-8 gnd |
| subject_GND | (DE-588)4167271-9 (DE-588)7663868-6 (DE-588)4182148-8 (DE-588)4113937-9 |
| title | Development of a fast DRAM analyzer and measurement of typical and critical memory access sequences in applications |
| title_auth | Development of a fast DRAM analyzer and measurement of typical and critical memory access sequences in applications |
| title_exact_search | Development of a fast DRAM analyzer and measurement of typical and critical memory access sequences in applications |
| title_full | Development of a fast DRAM analyzer and measurement of typical and critical memory access sequences in applications Simon Albert |
| title_fullStr | Development of a fast DRAM analyzer and measurement of typical and critical memory access sequences in applications Simon Albert |
| title_full_unstemmed | Development of a fast DRAM analyzer and measurement of typical and critical memory access sequences in applications Simon Albert |
| title_short | Development of a fast DRAM analyzer and measurement of typical and critical memory access sequences in applications |
| title_sort | development of a fast dram analyzer and measurement of typical and critical memory access sequences in applications |
| topic | SDRAM - Leistungsbewertung - Speicherzugriff Leistungsbewertung (DE-588)4167271-9 gnd SDRAM (DE-588)7663868-6 gnd Speicherzugriff (DE-588)4182148-8 gnd |
| topic_facet | SDRAM - Leistungsbewertung - Speicherzugriff Leistungsbewertung SDRAM Speicherzugriff Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=017086263&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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