Issues on efficient network-on-chip design: = Aspekte des effizienten Network-on-Chip Entwurfs
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
Kaiserslautern
Techn. Univ. Kaiserslautern
2008
|
| Ausgabe: | Als Ms. gedr. |
| Schriftenreihe: | Forschungsberichte Mikroelektronik
12 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XI, 228 S. graph. Darst. |
| ISBN: | 9783939432845 |
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Datensatz im Suchindex
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| adam_text | / * TECHNISCHE UNIVERSITAET * KAISERSLAUTERN CHRISTIAN NEEB ISSUES ON
EFFICIENT NETWORK-ON-CHIP DESIGN ASPEKTE DES EFFIZIENTEN NETWORK-ON-CHIP
ENTWURFS FORSCHUNGSBERICHTE MIKROELEKTRONIK * BAND 12 HERAUSGEGEBEN VON
PROF. DR.-ING. N. WEHN CONTENTS 1 INTRODUCTION 1 1.1 TRENDS IN
SYSTEM-ON-CHIP DESIGN 2 1.1.1 CHARACTERISTICS OF FUTURE APPLICATIONS 2
1.1.2 TECHNOLOGY SCALING 2 1.1.3 THE DESIGN PRODUCTIVITY GAP 4 1.1.4
COMMUNICATION CENTRIC DESIGN 6 1.2 OBJECTIVES AND CHAPTER OVERVIEW 9 2
NETWORKING CONCEPTS 11 2.1 COMMUNICATION MODELING 11 2.1.1 ABSTRACT
COMMUNICATION LAYERS 11 2.1.2 QUALITY OF SERVICE 15 2.2 NETWORK TOPOLOGY
17 2.2.1 TERMS AND DEFINITIONS 17 2.2.2 DIRECT NETWORKS 18 2.3 ROUTING
ALGORITHM 19 2.3.1 DETERMINISTIC ROUTING 20 2.3.2 OBLIVIOUS ROUTING 20
2.3.3 ADAPTIVE ROUTING 21 2.3.4 VIRTUAL CHANNEL ROUTING 21 2.3.5
IMPLEMENTATION ISSUES 23 2.4 SWITCHING TECHNIQUES 23 2.4.1 CIRCUIT
SWITCHING 24 2.4.2 PACKET SWITCHING 26 2.5 ROUTER ARCHITECTURE 30 VII
VIII CONTENTS 2.5.1 BASIC OPERATION 30 2.5.2 CROSSBAR SWITCH 33 2.5.3
ARBITRATION AND SELECTION 35 2.5.4 ALLOCATION 36 2.6 DEADLOCK HANDLING ,
38 2.6.1 IMPACT OF SWITCHING TECHNIQUE 40 2.6.2 DEPENDENCY GRAPHS 41
2.6.3 DEADLOCK AVOIDANCE TECHNIQUES 42 3 PERFORMANCE ANALYSIS 45 3.1
METRICS 46 3.1.1 THROUGHPUT 48 3.1.2 LATENCY 49 3.2 APPLICATION
COMMUNICATION MODEL 49 3.2.1 TERMS AND DEFINITIONS 50 3.2.2 SYNTHETIC
MODELS 52 3.3 NETWORK FLOW ANALYSIS 52 3.3.1 CHANNEL LOAD 53 3.3.2
FORWARDING PROBABILITY 56 3.4 QUEUING NETWORK ANALYSIS 58 3.4.1 BASIC
IDEA 59 3.4.2 SINGLE QUEUE MODEL 59 3.4.3 NETWORK MODEL 62 3.4.4
ITERATIVE SOLUTION METHOD 71 3.5 EXPERIMENTAL RESULTS 72 3.5.1 ROUTER
PERFORMANCE 74 3.5.2 NETWORK PERFORMANCE 77 3.6 RELATED WORK 79 CONTENTS
IX 4 CUSTOM NETWORK-ON-CHIP DESIGN 83 4.1 THE INOC ARCHITECTURE 84 4.2
ROUTING IN IRREGULAER NETWORKS 86 4.2.1 BASIC ROUTING SCHEME 87 4.2.2
EXTENDED ROUTING SCHEME 88 4.2.3 CONSTRUCTING THE ROUTING TABLES 90 4.3
NETWORK GENERATION 92 4.3.1 BASIC IDEA 94 4.3.2 PROBLEM STATEMENT 96
4.3.3 OBJECTIVE FUNCTION 97 4.3.4 INITIAL TOPOLOGY 99 4.4 NETWORK
GROWING STRATEGIES 102 4.4.1 DETERMINISTIC GREEDY EXPLORATION 102 4.4.2
PROBABILISTIC LOCAL SEARCH 103 4.5 HEURISTIC IMPROVEMENTS 104 4.5.1 FLOW
BASED METHODS 104 4.5.2 SATURATEDCUTMETHOD 105 4.5.3 CLUSTERING 106 4.6
EXPERIMENTAL RESULTS 107 4.6.1 GROWING STRATEGY EFFLCIENCY 108 4.6.2
PERFORMANCE COMPARISON 111 4.6.3 INOCSCALING 116 4.6.4 IMPACT OF PACKET
LENGTH 117 4.6.5 BASIC VS. EXTENDED ROUTING 120 4.7 SUMMARY 122 4.8
RELATED WORK 123 5 COMMUNICATION-CENTRIC DESIGN OF PARALLEL
TURBO-DECODERS 125 5.1 INTRODUCTION 125 5.2 TURBO-CODES V 127 5.2.1
TURBO-ENCODING 127 5.2.2 TURBO-DECODING 128 5.3 PARALLEL DECODER
ARCHITECTURES 130 X CONTENTS 5.3.1 DISTRIBUTED SERIAL MAP-DECODER (SMAP)
130 5.3.2 X-ARCHITECTURE BASED DECODER (XMAP) 132 5.4 INTERLEAVING IN
PARALLEL ARCHITECTURES 134 5.4.1 CONFLICT HANDLING 136 5.4.2 MEMORY
ACCESS PROBABILITY 137 5.5 NETWORK-ON-CHIP BASED INTERLEAVING 138 5.5.1
REQUIREMENTS 140 5.5.2 TOPOLOGY SELECTION 142 5.5.3 ROUTING AND
SCHEDULING 143 5.5.4 SWITCH SPEEDUP 151 5.5.5 INPUT VS. OUTPUT-QUEUING
153 5.5.6 BUFFER SIZING 155 5.5.7 BUFFERING EFFICIENCY 160 5.5.8
COMPARISON WITH INOC 161 5.5.9 SUMMARY 161 5.6 IMPLEMENTATION RESULTS
162 5.6.1 PARAMETRIC COST MODEL 163 5.6.2 NETWORK AREA 170 5.6.3 NETWORK
DELAY 171 5.7 APPLICATION SCENARIO: 3GPP UMTS TURBO-DECODING 173 5.7.1
3GPP COMPLIANT INTERLEAVING 174 5.7.2 NETWORK PERFORMANCE 175 5.7.3
IMPLEMENTATION RESULTS 180 5.8 RELATED WORK 182 6 CONCLUSIONS 185 7
ZUSAMMENFASSUNG 187 A TURBO DECODING ALGORITHMS 195 B SYMBOLS 197 C
ABBREVIATIONS 201 CONTENTS U BIBLIOGRAPHY 203 LIST OF FIGURES 215
LISTOFTABLES 223 LIST OF ALGORITHMS 225
|
| adam_txt |
/ * TECHNISCHE UNIVERSITAET * KAISERSLAUTERN CHRISTIAN NEEB ISSUES ON
EFFICIENT NETWORK-ON-CHIP DESIGN ASPEKTE DES EFFIZIENTEN NETWORK-ON-CHIP
ENTWURFS FORSCHUNGSBERICHTE MIKROELEKTRONIK * BAND 12 HERAUSGEGEBEN VON
PROF. DR.-ING. N. WEHN CONTENTS 1 INTRODUCTION 1 1.1 TRENDS IN
SYSTEM-ON-CHIP DESIGN 2 1.1.1 CHARACTERISTICS OF FUTURE APPLICATIONS 2
1.1.2 TECHNOLOGY SCALING 2 1.1.3 THE DESIGN PRODUCTIVITY GAP 4 1.1.4
COMMUNICATION CENTRIC DESIGN 6 1.2 OBJECTIVES AND CHAPTER OVERVIEW 9 2
NETWORKING CONCEPTS 11 2.1 COMMUNICATION MODELING 11 2.1.1 ABSTRACT
COMMUNICATION LAYERS 11 2.1.2 QUALITY OF SERVICE 15 2.2 NETWORK TOPOLOGY
17 2.2.1 TERMS AND DEFINITIONS 17 2.2.2 DIRECT NETWORKS 18 2.3 ROUTING
ALGORITHM 19 2.3.1 DETERMINISTIC ROUTING 20 2.3.2 OBLIVIOUS ROUTING 20
2.3.3 ADAPTIVE ROUTING 21 2.3.4 VIRTUAL CHANNEL ROUTING 21 2.3.5
IMPLEMENTATION ISSUES 23 2.4 SWITCHING TECHNIQUES 23 2.4.1 CIRCUIT
SWITCHING 24 2.4.2 PACKET SWITCHING 26 2.5 ROUTER ARCHITECTURE 30 ' VII
VIII CONTENTS 2.5.1 BASIC OPERATION 30 2.5.2 CROSSBAR SWITCH 33 2.5.3
ARBITRATION AND SELECTION 35 2.5.4 ALLOCATION 36 2.6 DEADLOCK HANDLING ,
38 2.6.1 IMPACT OF SWITCHING TECHNIQUE 40 2.6.2 DEPENDENCY GRAPHS 41
2.6.3 DEADLOCK AVOIDANCE TECHNIQUES 42 3 PERFORMANCE ANALYSIS 45 3.1
METRICS 46 3.1.1 THROUGHPUT 48 3.1.2 LATENCY 49 3.2 APPLICATION
COMMUNICATION MODEL 49 3.2.1 TERMS AND DEFINITIONS 50 3.2.2 SYNTHETIC
MODELS 52 3.3 NETWORK FLOW ANALYSIS 52 3.3.1 CHANNEL LOAD 53 3.3.2
FORWARDING PROBABILITY 56 3.4 QUEUING NETWORK ANALYSIS 58 3.4.1 BASIC
IDEA 59 3.4.2 SINGLE QUEUE MODEL 59 3.4.3 NETWORK MODEL 62 3.4.4
ITERATIVE SOLUTION METHOD 71 3.5 EXPERIMENTAL RESULTS 72 3.5.1 ROUTER
PERFORMANCE 74 3.5.2 NETWORK PERFORMANCE 77 3.6 RELATED WORK 79 CONTENTS
IX 4 CUSTOM NETWORK-ON-CHIP DESIGN 83 4.1 THE INOC ARCHITECTURE 84 4.2
ROUTING IN IRREGULAER NETWORKS 86 4.2.1 BASIC ROUTING SCHEME 87 4.2.2
EXTENDED ROUTING SCHEME 88 4.2.3 CONSTRUCTING THE ROUTING TABLES 90 4.3
NETWORK GENERATION 92 4.3.1 BASIC IDEA 94 4.3.2 PROBLEM STATEMENT 96
4.3.3 OBJECTIVE FUNCTION 97 4.3.4 INITIAL TOPOLOGY 99 4.4 NETWORK
GROWING STRATEGIES 102 4.4.1 DETERMINISTIC GREEDY EXPLORATION 102 4.4.2
PROBABILISTIC LOCAL SEARCH 103 4.5 HEURISTIC IMPROVEMENTS 104 4.5.1 FLOW
BASED METHODS 104 4.5.2 SATURATEDCUTMETHOD 105 4.5.3 CLUSTERING 106 4.6
EXPERIMENTAL RESULTS 107 4.6.1 GROWING STRATEGY EFFLCIENCY 108 4.6.2
PERFORMANCE COMPARISON 111 4.6.3 INOCSCALING 116 4.6.4 IMPACT OF PACKET
LENGTH 117 4.6.5 BASIC VS. EXTENDED ROUTING 120 4.7 SUMMARY 122 4.8
RELATED WORK 123 5 COMMUNICATION-CENTRIC DESIGN OF PARALLEL
TURBO-DECODERS 125 5.1 INTRODUCTION 125 5.2 TURBO-CODES V 127 5.2.1
TURBO-ENCODING 127 5.2.2 TURBO-DECODING 128 5.3 PARALLEL DECODER
ARCHITECTURES 130 X CONTENTS 5.3.1 DISTRIBUTED SERIAL MAP-DECODER (SMAP)
130 5.3.2 X-ARCHITECTURE BASED DECODER (XMAP) 132 5.4 INTERLEAVING IN
PARALLEL ARCHITECTURES 134 5.4.1 CONFLICT HANDLING 136 5.4.2 MEMORY
ACCESS PROBABILITY 137 5.5 NETWORK-ON-CHIP BASED INTERLEAVING 138 5.5.1
REQUIREMENTS 140 5.5.2 TOPOLOGY SELECTION 142 5.5.3 ROUTING AND
SCHEDULING 143 5.5.4 SWITCH SPEEDUP 151 5.5.5 INPUT VS. OUTPUT-QUEUING
153 5.5.6 BUFFER SIZING 155 5.5.7 BUFFERING EFFICIENCY 160 5.5.8
COMPARISON WITH INOC 161 5.5.9 SUMMARY 161 5.6 IMPLEMENTATION RESULTS
162 5.6.1 PARAMETRIC COST MODEL 163 5.6.2 NETWORK AREA 170 5.6.3 NETWORK
DELAY 171 5.7 APPLICATION SCENARIO: 3GPP UMTS TURBO-DECODING 173 5.7.1
3GPP COMPLIANT INTERLEAVING 174 5.7.2 NETWORK PERFORMANCE 175 5.7.3
IMPLEMENTATION RESULTS 180 5.8 RELATED WORK 182 6 CONCLUSIONS 185 7
ZUSAMMENFASSUNG 187 A TURBO DECODING ALGORITHMS 195 B SYMBOLS 197 C
ABBREVIATIONS 201 CONTENTS U BIBLIOGRAPHY 203 LIST OF FIGURES 215
LISTOFTABLES 223 LIST OF ALGORITHMS 225 |
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| author | Neeb, Christian 1974- |
| author_GND | (DE-588)136185010 |
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| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | Als Ms. gedr. |
| format | Thesis Book |
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| id | DE-604.BV035180626 |
| illustrated | Illustrated |
| index_date | 2024-07-02T22:57:45Z |
| indexdate | 2024-07-09T21:26:50Z |
| institution | BVB |
| isbn | 9783939432845 |
| language | English |
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| physical | XI, 228 S. graph. Darst. |
| publishDate | 2008 |
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| publisher | Techn. Univ. Kaiserslautern |
| record_format | marc |
| series | Forschungsberichte Mikroelektronik |
| series2 | Forschungsberichte Mikroelektronik |
| spelling | Neeb, Christian 1974- Verfasser (DE-588)136185010 aut Issues on efficient network-on-chip design = Aspekte des effizienten Network-on-Chip Entwurfs Christian Neeb Aspekte des effizienten Network-on-Chip Entwurfs Als Ms. gedr. Kaiserslautern Techn. Univ. Kaiserslautern 2008 XI, 228 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Forschungsberichte Mikroelektronik 12 Zugl.: Kaiserslautern, Univ., Diss., 2008 Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Elektrisches Netzwerk (DE-588)4014214-0 gnd rswk-swf System-on-Chip (DE-588)4740357-3 gnd rswk-swf Chip (DE-588)4197163-2 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content System-on-Chip (DE-588)4740357-3 s Elektrisches Netzwerk (DE-588)4014214-0 s Schaltungsentwurf (DE-588)4179389-4 s Chip (DE-588)4197163-2 s DE-604 Forschungsberichte Mikroelektronik 12 (DE-604)BV012925671 12 GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016987395&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Neeb, Christian 1974- Issues on efficient network-on-chip design = Aspekte des effizienten Network-on-Chip Entwurfs Forschungsberichte Mikroelektronik Schaltungsentwurf (DE-588)4179389-4 gnd Elektrisches Netzwerk (DE-588)4014214-0 gnd System-on-Chip (DE-588)4740357-3 gnd Chip (DE-588)4197163-2 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4014214-0 (DE-588)4740357-3 (DE-588)4197163-2 (DE-588)4113937-9 |
| title | Issues on efficient network-on-chip design = Aspekte des effizienten Network-on-Chip Entwurfs |
| title_alt | Aspekte des effizienten Network-on-Chip Entwurfs |
| title_auth | Issues on efficient network-on-chip design = Aspekte des effizienten Network-on-Chip Entwurfs |
| title_exact_search | Issues on efficient network-on-chip design = Aspekte des effizienten Network-on-Chip Entwurfs |
| title_exact_search_txtP | Issues on efficient network-on-chip design = Aspekte des effizienten Network-on-Chip Entwurfs |
| title_full | Issues on efficient network-on-chip design = Aspekte des effizienten Network-on-Chip Entwurfs Christian Neeb |
| title_fullStr | Issues on efficient network-on-chip design = Aspekte des effizienten Network-on-Chip Entwurfs Christian Neeb |
| title_full_unstemmed | Issues on efficient network-on-chip design = Aspekte des effizienten Network-on-Chip Entwurfs Christian Neeb |
| title_short | Issues on efficient network-on-chip design |
| title_sort | issues on efficient network on chip design aspekte des effizienten network on chip entwurfs |
| title_sub | = Aspekte des effizienten Network-on-Chip Entwurfs |
| topic | Schaltungsentwurf (DE-588)4179389-4 gnd Elektrisches Netzwerk (DE-588)4014214-0 gnd System-on-Chip (DE-588)4740357-3 gnd Chip (DE-588)4197163-2 gnd |
| topic_facet | Schaltungsentwurf Elektrisches Netzwerk System-on-Chip Chip Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016987395&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV012925671 |
| work_keys_str_mv | AT neebchristian issuesonefficientnetworkonchipdesignaspektedeseffizientennetworkonchipentwurfs AT neebchristian aspektedeseffizientennetworkonchipentwurfs |