Embedded multiprocessors: scheduling and synchronization
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Boca Raton, Fla. [u.a.]
CRC Press
2009
|
| Ausgabe: | 2. ed. |
| Schriftenreihe: | Signal processing and communications
3 |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | XXII, 361 S. graph. Darst. |
| ISBN: | 9781420048018 |
Internformat
MARC
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| 005 | 20090429 | ||
| 007 | t | ||
| 008 | 081014s2009 d||| |||| 00||| eng d | ||
| 020 | |a 9781420048018 |c (hbk.) : £67.99 |9 978-1-4200-4801-8 | ||
| 035 | |a (OCoLC)276406232 | ||
| 035 | |a (DE-599)GBV57382035X | ||
| 040 | |a DE-604 |b ger |e aacr | ||
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| 084 | |a ST 153 |0 (DE-625)143597: |2 rvk | ||
| 100 | 1 | |a Sriram, Sundararajan |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Embedded multiprocessors |b scheduling and synchronization |c Sundararajan Sriram, Shuvra S. Bhattacharyya |
| 250 | |a 2. ed. | ||
| 264 | 1 | |a Boca Raton, Fla. [u.a.] |b CRC Press |c 2009 | |
| 300 | |a XXII, 361 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Signal processing and communications |v 3 | |
| 650 | 4 | |a Embedded computer systems | |
| 650 | 4 | |a Memory management (Computer science) | |
| 650 | 4 | |a Multimedia systems | |
| 650 | 4 | |a Multiprocessors | |
| 650 | 4 | |a Scheduling | |
| 650 | 0 | 7 | |a Eingebettetes System |0 (DE-588)4396978-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Mehrprozessorsystem |0 (DE-588)4038397-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Mehrprozessorsystem |0 (DE-588)4038397-0 |D s |
| 689 | 0 | 1 | |a Eingebettetes System |0 (DE-588)4396978-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 700 | 1 | |a Bhattacharyya, Shuvra S. |e Verfasser |4 aut | |
| 830 | 0 | |a Signal processing and communications |v 3 |w (DE-604)BV019738041 |9 3 | |
| 856 | 4 | 2 | |m Digitalisierung UB Bayreuth |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016765397&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-016765397 | ||
Datensatz im Suchindex
| _version_ | 1804138057635463168 |
|---|---|
| adam_text | XV
CONTENTS
1.
INTRODUCTION
.....................................................................................1
1.1
Multiprocessor DSP Systems
2
1.2
Application-Specific Multiprocessors
4
1.3
Exploitation of Parallelism
5
1.4
Dataflow Modeling for DSP Design
6
1.5
Utility of Dataflow for DSP
9
1.6
Overview
11
2.
APPLICATION-SPECIFIC MULTIPROCESSORS
..........................13
2.1
Parallel Architecture Classifications
13
2.2
Exploiting Instruction Level Parallelism
15
2.2.1
ILP in Programmable DSP Processors
15
2.2.2
Subword
Parallelism
17
2.2.3
VLIW Processors
18
2.3
Dataflow DSP Architectures
20
2.4
Systolic and
Wavefront
Arrays
20
2.5
Multiprocessor DSP Architectures
21
2.6
Single-Chip Multiprocessors
23
2.6.1
The MathStar MP-SOC
24
2.6.2
The Ambric Processor
24
2.6.3
The Stream Processor
25
2.6.4
Graphics Processors
25
2.6.5
The
Sandbridge Sandblaster
26
2.6.6
picoChip
26
2.6.7
Single-Chip Multiprocessors from Texas Instruments
27
xvi
EMBEDDED MULTIPROCESSORS
2.6.8
The Tilera Processor
29
2.6.9
Heterogeneous Multiprocessors
29
2.7
Reconfigurable
Computing
30
2.8
Architectures that Exploit Predictable IPC
32
2.9
Summary
34
3.
BACKGROUND TERMINOLOGY AND NOTATION
.....................35
3.1
Graph Data Structures
35
3.2
Dataflow Graphs
36
3.3
Computation Graphs
37
3.4
Petri
Nets
37
3.5
Synchronous Dataflow
38
3.6
Analytical Properties of SDF Graphs
39
3.7
Converting a General SDF Graph into a Homogeneous SDF
Graph
40
3.8
Acyclic Precedence Expansion Graph
42
3.9
Application Graph
44
3.10
Synchronous Languages
44
3.11
HSDFG Concepts and Notations
47
3.12
Complexity of Algorithms
49
3.13
Shortest and Longest Paths in Graphs
51
3.13.1
Dijkstra s
Algorithm
52
3.13.2
The Bellman-Ford Algorithm
52
3.13.3
The Floyd-
Warshall
Algorithm
52
3.14
Solving Difference Constraints Using Shortest Paths
54
3.15
Maximum Cycle Mean
56
3.16
Summary
57
4.
DSP-ORIENTED DATAFLOW MODELS OF COMPUTATION
....59
4.1
Scalable Synchronous Dataflow
60
CONTENTS xvii
4.2 Cyclo-Static
Dataflow
62
4.2.1
Lumped SDF Representations
63
4.2.2 Phase
Repetitions Vectors
66
4.2.3
Equivalent HSDF Graphs
66
4.2.4
Analysis Techniques
67
4.3
Multidimensional Synchronous Dataflow
67
4.4
Parameterized Dataflow
71
4.5
Reactive Process Networks
73
4.6
Integrating Dataflow and State Machine Models
74
4.6.1
CAL
75
4.6.2
FunState
76
4.6.3 Starcharts
and Heterochronous Dataflow
76
4.6.4
DF-STAR
77
4.6.5
DFCharts
78
4.7
Controlled Dataflow Actors
78
4.7.1
Boolean Dataflow
78
4.7.2
Stream-Based Functions
79
4.7.3
Enable-Invoke Dataflow
83
4.8
Summary
83
5.
MULTIPROCESSOR SCHEDULING MODELS
...............................85
5.1
Task-Level Parallelism and Data Parallelism
85
5.2
Static versus Dynamic Scheduling Strategies
86
5.3
Fully-Static Schedules
87
5.4
Self-Timed Schedules
92
5.5
Dynamic Schedules
94
5.6
Quasi-Static Schedules
94
5.7
Schedule Notation
95
5.8
Unfolding HSDF Graphs
99
xviii
EMBEDDED MULTIPROCESSORS
5.9
Execution Time Estimates and Static Schedules
101
5.10
Summary
104
6.
IPC-CONSCIOUS SCHEDULING ALGORITHMS
........................105
6.1
Problem Description
105
6.2
Stone s Assignment Algorithm
106
6.3
List Scheduling Algorithms
110
6.3.1
Graham s Bounds
111
6.3.2
The Basic Algorithms
—
HLFET and ETF
114
6.3.3
The Mapping Heuristic
114
6.3.4
Dynamic Level Scheduling
115
6.3.5
Dynamic Critical Path Scheduling
116
6.4
Clustering Algorithms
117
6.4.1
Linear Clustering
118
6.4.2
Internalization
119
6.4.3
Dominant Sequence Clustering
119
6.4.4
Declustering
120
6.5
Integrated Scheduling Algorithms
122
6.6
Pipelined Scheduling
124
6.7
Summary
129
7.
THE ORDERED-TRANSACTIONS STRATEGY
............................131
7.1
The Ordered-Transactions Strategy
131
7.2
Shared Bus Architecture
133
7.3
Interprocessor
Communication Mechanisms
134
7.4
Using the Ordered-Transactions Approach
137
7.5
Design of an Ordered Memory Access Multiprocessor
138
7.5.1
High Level Design Description
138
7.5.2
A Modified Design
139
7.6
Design Details of a Prototype
142
CONTENTS
ХІХ
7.6.1 Top Level Design 142
7.6.2
Transaction
Order Controller 144
7.6.3 Host Interface 149
7.6.4 Processing Element 150
7.6.5 FPGA
Circuitry
151
7.6.6
Shared
Memory 154
7.6.7
Connecting
Multiple Boards 154
7.7 Hardware and Software Implementation 155
7.7.1 Board Design 155
7.7.2 Software Interface 156
7.8
Ordered I/O and
Parameter
Control
157
7.9 Application
Examples
159
7.9.1
Music Synthesis
159
7.9.2 QMF Filter Bank 159
7.9.3 1024 Point
Complex Fast Fourier Transform (FFT)
162
7.10
Summary
162
8.
ANALYSIS OF THE ORDERED-TRANSACTIONS STRATEGY
165
8.1
Inter-processor Communication Graph (Gjpj.)
168
8.2
Execution Time Estimates
173
8.3
Ordering Constraints Viewed as Added Edges
174
8.4
Periodicity
175
8.5
Optimal Order
176
8.6
Effects of Changes in Execution Times
179
8.6.1
Deterministic Case
180
8.6.2
Modeling Run-time Variations in Execution Times
182
8.6.3
Bounds on the Average Iteration Period
184
8.6.4
Implications for the Ordered Transactions Schedule
185
8.7
Effects of
Interprocessor
Communication Costs
186
XX EMBEDDED MULTIPROCESSORS
8.8
Summary
188
9.
EXTENDING THE
ОМА
ARCHITECTURE
...................................189
9.1
Scheduling BDF Graphs
189
9.2
Parallel Implementation on Shared Memory Machines
191
9.2.1
General Strategy
191
9.2.2
Implementation on the
ОМА
194
9.2.3
Improved Mechanism
196
9.2.4
Generating the Annotated Bus Access List
199
9.3
Data-dependent Iteration
202
9.4
Summary
203
10.
SYNCHRONIZATION IN SELF-TIMED SYSTEMS
......................205
10.1
The Barrier MIMD Technique
206
10.2
Redundant Synchronization Removal in Non-Iterative
Dataflow
207
10.3
Analysis of Self-Timed Execution
210
10.3.1
Estimated Throughput
210
10.4
Strongly Connected Components and Buffer Size
Bounds
210
10.5
Synchronization Model
213
10.5.1
Synchronization Protocols
213
10.5.2
The Synchronization Graph
215
10.6
A Synchronization Cost Metric
218
10.7
Removing Redundant Synchronizations
219
10.7.1
The Independence of Redundant Synchronizations
220
10.7.2
Removing Redundant Synchronizations
221
10.7.3
Comparison with Shaffer s Approach
223
10.7.4
An Example
223
10.8
Making the Synchronization Graph Strongly
CONTENTS XXI
Connected
225
10.8.1
Adding Edges to the Synchronization Graph
227
10.9
Insertion of Delays
229
10.9.1
Analysis of DetermineDelays
231
10.9.2
Delay Insertion Example
234
10.9.3
Extending the Algorithm
236
10.9.4
Complexity
237
10.9.5
Related Work
238
10.10
Summary
239
11.
RESYNCHRONIZATION
...................................................................241
11.1
Definition of Resynchronization
241
11.2
Properties of Resynchronization
243
11.3
Relationship to Set Covering
246
11.4
Intractability of Resynchronization
249
11.5
Heuristic Solutions
252
11.5.1
Applying Set Covering Techniques to Pairs of SCCs
252
11.5.2
A More Flexible Approach
255
11.5.3
Unit-Subsumption Resynchronization Edges
259
11.5.4
Example
261
11.5.5
Simulation Approach
263
11.6
Chainable Synchronization Graphs
264
11.6.1
Chainable Synchronization Graph SCCs
264
11.6.2
Comparison to the Global-Resynchronize Heuristic
266
11.6.3
A Generalization of the Chaining Technique
268
11.6.4
Incorporating the Chaining Technique
268
11.7
Resynchronization of Constraint Graphs for Relative
Scheduling
270
11.8
Summary
271
XXII
EMBEDDED MULTIPROCESSORS
12.
LATENCY-CONSTRAINED RESYNCHRONIZATION
................273
12.1
Elimination of Synchronization Edges
274
12.2
Latency-Constrained Resynchronization
275
12.3
Intractability of LCR
281
12.4
Two-Processor Systems
288
12.4.1
Interval Covering
289
12.4.2
Two-Processor Latency-Constrained
Resynchronization
289
12.4.3
Taking Delays into Account
293
12.5
A Heuristic for General Synchronization Graphs
304
12.5.1
Customization to Transparent Synchronization
Graphs
305
12.5.2
Complexity
307
12.5.3
Example
308
12.6
Summary
315
13.
INTEGRATED SYNCHRONIZATION OPTIMIZATION
.............319
13.1
Computing Buffer Sizes
319
13.2
A Framework for Self-Timed Implementation
320
13.3
Summary
322
14.
FUTURE RESEARCH DIRECTIONS
...............................................325
BIBLIOGRAPHY
...........................................................................................329
INDEX
..............................................................................................................353
ABOUT THE AUTHORS
..............................................................................361
|
| adam_txt |
XV
CONTENTS
1.
INTRODUCTION
.1
1.1
Multiprocessor DSP Systems
2
1.2
Application-Specific Multiprocessors
4
1.3
Exploitation of Parallelism
5
1.4
Dataflow Modeling for DSP Design
6
1.5
Utility of Dataflow for DSP
9
1.6
Overview
11
2.
APPLICATION-SPECIFIC MULTIPROCESSORS
.13
2.1
Parallel Architecture Classifications
13
2.2
Exploiting Instruction Level Parallelism
15
2.2.1
ILP in Programmable DSP Processors
15
2.2.2
Subword
Parallelism
17
2.2.3
VLIW Processors
18
2.3
Dataflow DSP Architectures
20
2.4
Systolic and
Wavefront
Arrays
20
2.5
Multiprocessor DSP Architectures
21
2.6
Single-Chip Multiprocessors
23
2.6.1
The MathStar MP-SOC
24
2.6.2
The Ambric Processor
24
2.6.3
The Stream Processor
25
2.6.4
Graphics Processors
25
2.6.5
The
Sandbridge Sandblaster
26
2.6.6
picoChip
26
2.6.7
Single-Chip Multiprocessors from Texas Instruments
27
xvi
EMBEDDED MULTIPROCESSORS
2.6.8
The Tilera Processor
29
2.6.9
Heterogeneous Multiprocessors
29
2.7
Reconfigurable
Computing
30
2.8
Architectures that Exploit Predictable IPC
32
2.9
Summary
34
3.
BACKGROUND TERMINOLOGY AND NOTATION
.35
3.1
Graph Data Structures
35
3.2
Dataflow Graphs
36
3.3
Computation Graphs
37
3.4
Petri
Nets
37
3.5
Synchronous Dataflow
38
3.6
Analytical Properties of SDF Graphs
39
3.7
Converting a General SDF Graph into a Homogeneous SDF
Graph
40
3.8
Acyclic Precedence Expansion Graph
42
3.9
Application Graph
44
3.10
Synchronous Languages
44
3.11
HSDFG Concepts and Notations
47
3.12
Complexity of Algorithms
49
3.13
Shortest and Longest Paths in Graphs
51
3.13.1
Dijkstra's
Algorithm
52
3.13.2
The Bellman-Ford Algorithm
52
3.13.3
The Floyd-
Warshall
Algorithm
52
3.14
Solving Difference Constraints Using Shortest Paths
54
3.15
Maximum Cycle Mean
56
3.16
Summary
57
4.
DSP-ORIENTED DATAFLOW MODELS OF COMPUTATION
.59
4.1
Scalable Synchronous Dataflow
60
CONTENTS xvii
4.2 Cyclo-Static
Dataflow
62
4.2.1
Lumped SDF Representations
63
4.2.2 Phase
Repetitions Vectors
66
4.2.3
Equivalent HSDF Graphs
66
4.2.4
Analysis Techniques
67
4.3
Multidimensional Synchronous Dataflow
67
4.4
Parameterized Dataflow
71
4.5
Reactive Process Networks
73
4.6
Integrating Dataflow and State Machine Models
74
4.6.1
CAL
75
4.6.2
FunState
76
4.6.3 Starcharts
and Heterochronous Dataflow
76
4.6.4
DF-STAR
77
4.6.5
DFCharts
78
4.7
Controlled Dataflow Actors
78
4.7.1
Boolean Dataflow
78
4.7.2
Stream-Based Functions
79
4.7.3
Enable-Invoke Dataflow
83
4.8
Summary
83
5.
MULTIPROCESSOR SCHEDULING MODELS
.85
5.1
Task-Level Parallelism and Data Parallelism
85
5.2
Static versus Dynamic Scheduling Strategies
86
5.3
Fully-Static Schedules
87
5.4
Self-Timed Schedules
92
5.5
Dynamic Schedules
94
5.6
Quasi-Static Schedules
94
5.7
Schedule Notation
95
5.8
Unfolding HSDF Graphs
99
xviii
EMBEDDED MULTIPROCESSORS
5.9
Execution Time Estimates and Static Schedules
101
5.10
Summary
104
6.
IPC-CONSCIOUS SCHEDULING ALGORITHMS
.105
6.1
Problem Description
105
6.2
Stone's Assignment Algorithm
106
6.3
List Scheduling Algorithms
110
6.3.1
Graham's Bounds
111
6.3.2
The Basic Algorithms
—
HLFET and ETF
114
6.3.3
The Mapping Heuristic
114
6.3.4
Dynamic Level Scheduling
115
6.3.5
Dynamic Critical Path Scheduling
116
6.4
Clustering Algorithms
117
6.4.1
Linear Clustering
118
6.4.2
Internalization
119
6.4.3
Dominant Sequence Clustering
119
6.4.4
Declustering
120
6.5
Integrated Scheduling Algorithms
122
6.6
Pipelined Scheduling
124
6.7
Summary
129
7.
THE ORDERED-TRANSACTIONS STRATEGY
.131
7.1
The Ordered-Transactions Strategy
131
7.2
Shared Bus Architecture
133
7.3
Interprocessor
Communication Mechanisms
134
7.4
Using the Ordered-Transactions Approach
137
7.5
Design of an Ordered Memory Access Multiprocessor
138
7.5.1
High Level Design Description
138
7.5.2
A Modified Design
139
7.6
Design Details of a Prototype
142
CONTENTS
ХІХ
7.6.1 Top Level Design 142
7.6.2
Transaction
Order Controller 144
7.6.3 Host Interface 149
7.6.4 Processing Element 150
7.6.5 FPGA
Circuitry
151
7.6.6
Shared
Memory 154
7.6.7
Connecting
Multiple Boards 154
7.7 Hardware and Software Implementation 155
7.7.1 Board Design 155
7.7.2 Software Interface 156
7.8
Ordered I/O and
Parameter
Control
157
7.9 Application
Examples
159
7.9.1
Music Synthesis
159
7.9.2 QMF Filter Bank 159
7.9.3 1024 Point
Complex Fast Fourier Transform (FFT)
162
7.10
Summary
162
8.
ANALYSIS OF THE ORDERED-TRANSACTIONS STRATEGY
165
8.1
Inter-processor Communication Graph (Gjpj.)
168
8.2
Execution Time Estimates
173
8.3
Ordering Constraints Viewed as Added Edges
174
8.4
Periodicity
175
8.5
Optimal Order
176
8.6
Effects of Changes in Execution Times
179
8.6.1
Deterministic Case
180
8.6.2
Modeling Run-time Variations in Execution Times
182
8.6.3
Bounds on the Average Iteration Period
184
8.6.4
Implications for the Ordered Transactions Schedule
185
8.7
Effects of
Interprocessor
Communication Costs
186
XX EMBEDDED MULTIPROCESSORS
8.8
Summary
188
9.
EXTENDING THE
ОМА
ARCHITECTURE
.189
9.1
Scheduling BDF Graphs
189
9.2
Parallel Implementation on Shared Memory Machines
191
9.2.1
General Strategy
191
9.2.2
Implementation on the
ОМА
194
9.2.3
Improved Mechanism
196
9.2.4
Generating the Annotated Bus Access List
199
9.3
Data-dependent Iteration
202
9.4
Summary
203
10.
SYNCHRONIZATION IN SELF-TIMED SYSTEMS
.205
10.1
The Barrier MIMD Technique
206
10.2
Redundant Synchronization Removal in Non-Iterative
Dataflow
207
10.3
Analysis of Self-Timed Execution
210
10.3.1
Estimated Throughput
210
10.4
Strongly Connected Components and Buffer Size
Bounds
210
10.5
Synchronization Model
213
10.5.1
Synchronization Protocols
213
10.5.2
The Synchronization Graph
215
10.6
A Synchronization Cost Metric
218
10.7
Removing Redundant Synchronizations
219
10.7.1
The Independence of Redundant Synchronizations
220
10.7.2
Removing Redundant Synchronizations
221
10.7.3
Comparison with Shaffer's Approach
223
10.7.4
An Example
223
10.8
Making the Synchronization Graph Strongly
CONTENTS XXI
Connected
225
10.8.1
Adding Edges to the Synchronization Graph
227
10.9
Insertion of Delays
229
10.9.1
Analysis of DetermineDelays
231
10.9.2
Delay Insertion Example
234
10.9.3
Extending the Algorithm
236
10.9.4
Complexity
237
10.9.5
Related Work
238
10.10
Summary
239
11.
RESYNCHRONIZATION
.241
11.1
Definition of Resynchronization
241
11.2
Properties of Resynchronization
243
11.3
Relationship to Set Covering
246
11.4
Intractability of Resynchronization
249
11.5
Heuristic Solutions
252
11.5.1
Applying Set Covering Techniques to Pairs of SCCs
252
11.5.2
A More Flexible Approach
255
11.5.3
Unit-Subsumption Resynchronization Edges
259
11.5.4
Example
261
11.5.5
Simulation Approach
263
11.6
Chainable Synchronization Graphs
264
11.6.1
Chainable Synchronization Graph SCCs
264
11.6.2
Comparison to the Global-Resynchronize Heuristic
266
11.6.3
A Generalization of the Chaining Technique
268
11.6.4
Incorporating the Chaining Technique
268
11.7
Resynchronization of Constraint Graphs for Relative
Scheduling
270
11.8
Summary
271
XXII
EMBEDDED MULTIPROCESSORS
12.
LATENCY-CONSTRAINED RESYNCHRONIZATION
.273
12.1
Elimination of Synchronization Edges
274
12.2
Latency-Constrained Resynchronization
275
12.3
Intractability of LCR
281
12.4
Two-Processor Systems
288
12.4.1
Interval Covering
289
12.4.2
Two-Processor Latency-Constrained
Resynchronization
289
12.4.3
Taking Delays into Account
293
12.5
A Heuristic for General Synchronization Graphs
304
12.5.1
Customization to Transparent Synchronization
Graphs
305
12.5.2
Complexity
307
12.5.3
Example
308
12.6
Summary
315
13.
INTEGRATED SYNCHRONIZATION OPTIMIZATION
.319
13.1
Computing Buffer Sizes
319
13.2
A Framework for Self-Timed Implementation
320
13.3
Summary
322
14.
FUTURE RESEARCH DIRECTIONS
.325
BIBLIOGRAPHY
.329
INDEX
.353
ABOUT THE AUTHORS
.361 |
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| author | Sriram, Sundararajan Bhattacharyya, Shuvra S. |
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| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ST 153 |
| ctrlnum | (OCoLC)276406232 (DE-599)GBV57382035X |
| dewey-full | 004.16 |
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| discipline | Informatik |
| discipline_str_mv | Informatik |
| edition | 2. ed. |
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| id | DE-604.BV035097368 |
| illustrated | Illustrated |
| index_date | 2024-07-02T22:12:48Z |
| indexdate | 2024-07-09T21:22:08Z |
| institution | BVB |
| isbn | 9781420048018 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-016765397 |
| oclc_num | 276406232 |
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| physical | XXII, 361 S. graph. Darst. |
| publishDate | 2009 |
| publishDateSearch | 2009 |
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| publisher | CRC Press |
| record_format | marc |
| series | Signal processing and communications |
| series2 | Signal processing and communications |
| spelling | Sriram, Sundararajan Verfasser aut Embedded multiprocessors scheduling and synchronization Sundararajan Sriram, Shuvra S. Bhattacharyya 2. ed. Boca Raton, Fla. [u.a.] CRC Press 2009 XXII, 361 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Signal processing and communications 3 Embedded computer systems Memory management (Computer science) Multimedia systems Multiprocessors Scheduling Eingebettetes System (DE-588)4396978-1 gnd rswk-swf Mehrprozessorsystem (DE-588)4038397-0 gnd rswk-swf Mehrprozessorsystem (DE-588)4038397-0 s Eingebettetes System (DE-588)4396978-1 s DE-604 Bhattacharyya, Shuvra S. Verfasser aut Signal processing and communications 3 (DE-604)BV019738041 3 Digitalisierung UB Bayreuth application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016765397&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Sriram, Sundararajan Bhattacharyya, Shuvra S. Embedded multiprocessors scheduling and synchronization Signal processing and communications Embedded computer systems Memory management (Computer science) Multimedia systems Multiprocessors Scheduling Eingebettetes System (DE-588)4396978-1 gnd Mehrprozessorsystem (DE-588)4038397-0 gnd |
| subject_GND | (DE-588)4396978-1 (DE-588)4038397-0 |
| title | Embedded multiprocessors scheduling and synchronization |
| title_auth | Embedded multiprocessors scheduling and synchronization |
| title_exact_search | Embedded multiprocessors scheduling and synchronization |
| title_exact_search_txtP | Embedded multiprocessors scheduling and synchronization |
| title_full | Embedded multiprocessors scheduling and synchronization Sundararajan Sriram, Shuvra S. Bhattacharyya |
| title_fullStr | Embedded multiprocessors scheduling and synchronization Sundararajan Sriram, Shuvra S. Bhattacharyya |
| title_full_unstemmed | Embedded multiprocessors scheduling and synchronization Sundararajan Sriram, Shuvra S. Bhattacharyya |
| title_short | Embedded multiprocessors |
| title_sort | embedded multiprocessors scheduling and synchronization |
| title_sub | scheduling and synchronization |
| topic | Embedded computer systems Memory management (Computer science) Multimedia systems Multiprocessors Scheduling Eingebettetes System (DE-588)4396978-1 gnd Mehrprozessorsystem (DE-588)4038397-0 gnd |
| topic_facet | Embedded computer systems Memory management (Computer science) Multimedia systems Multiprocessors Scheduling Eingebettetes System Mehrprozessorsystem |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016765397&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| volume_link | (DE-604)BV019738041 |
| work_keys_str_mv | AT sriramsundararajan embeddedmultiprocessorsschedulingandsynchronization AT bhattacharyyashuvras embeddedmultiprocessorsschedulingandsynchronization |