Optimizing hardware granularity in parallel systems:
Abstract: "In order for parallel architectures to be of any use at all in providing superior performance to uniprocessors, the benefits of splitting the workload among several processing elements must outweigh the overheads associated with this 'divide and conquer' strategy. Whether o...
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
Edinburgh
University of Edinburgh, Dept. of Computer Science
[1995]
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| Schlagworte: | |
| Zusammenfassung: | Abstract: "In order for parallel architectures to be of any use at all in providing superior performance to uniprocessors, the benefits of splitting the workload among several processing elements must outweigh the overheads associated with this 'divide and conquer' strategy. Whether or not this is the case depends on the nature of the algorithm and on the cost: performance functions associated with the real computer hardware available at a given time. This thesis is an investigation into the tradeoff of grain of hardware versus speed of hardware, in an attempt to show how the optimal hardware parallelism can be assessed. A model is developed of the execution time T of an algorithm on a machine as a function of the number of nodes, N. The model is used to examine the degree to which it is possible to obtain an optimal value of N, corresponding to minimum execution time. Specifically, the optimization is done assuming a particular base architecture, an algorithm or class thereof and an overall hardware cost. Two base architectures and algorithm types are considered, corresponding to two common classes of parallel architectures: a shared memory multiprocessor and a message-passing multicomputer. The former is represented by a simple shared-bus multiprocessor in which each processing element performs operations on data stored in a global shared store. The second type is represented by a two- dimensional mesh-connected multicomputer. In this type of system all memory is considered private and data sharing is carried out using 'messages' explicitly passed among the PEs." |
| Beschreibung: | xii, 172 p. ill. 21 cm |
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| 520 | 3 | |a Abstract: "In order for parallel architectures to be of any use at all in providing superior performance to uniprocessors, the benefits of splitting the workload among several processing elements must outweigh the overheads associated with this 'divide and conquer' strategy. Whether or not this is the case depends on the nature of the algorithm and on the cost: performance functions associated with the real computer hardware available at a given time. This thesis is an investigation into the tradeoff of grain of hardware versus speed of hardware, in an attempt to show how the optimal hardware parallelism can be assessed. A model is developed of the execution time T of an algorithm on a machine as a function of the number of nodes, N. The model is used to examine the degree to which it is possible to obtain an optimal value of N, corresponding to minimum execution time. Specifically, the optimization is done assuming a particular base architecture, an algorithm or class thereof and an overall hardware cost. Two base architectures and algorithm types are considered, corresponding to two common classes of parallel architectures: a shared memory multiprocessor and a message-passing multicomputer. The former is represented by a simple shared-bus multiprocessor in which each processing element performs operations on data stored in a global shared store. The second type is represented by a two- dimensional mesh-connected multicomputer. In this type of system all memory is considered private and data sharing is carried out using 'messages' explicitly passed among the PEs." | |
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| institution | BVB |
| language | English |
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| physical | xii, 172 p. ill. 21 cm |
| publishDate | 1995 |
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| publisher | University of Edinburgh, Dept. of Computer Science |
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| spelling | Kelly Thomas Verfasser aut Optimizing hardware granularity in parallel systems Thomas Kelly Edinburgh University of Edinburgh, Dept. of Computer Science [1995] xii, 172 p. ill. 21 cm txt rdacontent n rdamedia nc rdacarrier Thesis (Ph. D.)--University of Edinburgh, 1995 Abstract: "In order for parallel architectures to be of any use at all in providing superior performance to uniprocessors, the benefits of splitting the workload among several processing elements must outweigh the overheads associated with this 'divide and conquer' strategy. Whether or not this is the case depends on the nature of the algorithm and on the cost: performance functions associated with the real computer hardware available at a given time. This thesis is an investigation into the tradeoff of grain of hardware versus speed of hardware, in an attempt to show how the optimal hardware parallelism can be assessed. A model is developed of the execution time T of an algorithm on a machine as a function of the number of nodes, N. The model is used to examine the degree to which it is possible to obtain an optimal value of N, corresponding to minimum execution time. Specifically, the optimization is done assuming a particular base architecture, an algorithm or class thereof and an overall hardware cost. Two base architectures and algorithm types are considered, corresponding to two common classes of parallel architectures: a shared memory multiprocessor and a message-passing multicomputer. The former is represented by a simple shared-bus multiprocessor in which each processing element performs operations on data stored in a global shared store. The second type is represented by a two- dimensional mesh-connected multicomputer. In this type of system all memory is considered private and data sharing is carried out using 'messages' explicitly passed among the PEs." Computer architecture Parallel processing (Electronic computers) (DE-588)4113937-9 Hochschulschrift gnd-content |
| spellingShingle | Kelly Thomas Optimizing hardware granularity in parallel systems Computer architecture Parallel processing (Electronic computers) |
| subject_GND | (DE-588)4113937-9 |
| title | Optimizing hardware granularity in parallel systems |
| title_auth | Optimizing hardware granularity in parallel systems |
| title_exact_search | Optimizing hardware granularity in parallel systems |
| title_exact_search_txtP | Optimizing hardware granularity in parallel systems |
| title_full | Optimizing hardware granularity in parallel systems Thomas Kelly |
| title_fullStr | Optimizing hardware granularity in parallel systems Thomas Kelly |
| title_full_unstemmed | Optimizing hardware granularity in parallel systems Thomas Kelly |
| title_short | Optimizing hardware granularity in parallel systems |
| title_sort | optimizing hardware granularity in parallel systems |
| topic | Computer architecture Parallel processing (Electronic computers) |
| topic_facet | Computer architecture Parallel processing (Electronic computers) Hochschulschrift |
| work_keys_str_mv | AT kellythomas optimizinghardwaregranularityinparallelsystems |