Tradeoffs and optimization in analog CMOS design:
"Analog CMOS (complementary metal-oxide-semiconductor) integrated circuits are in widespread use for communications, entertainment, multimedia, biomedical, and many other applications that interface with the physical world. Although analog CMOS design is greatly complicated by the design choice...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Chichester
Wiley
2008
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Zusammenfassung: | "Analog CMOS (complementary metal-oxide-semiconductor) integrated circuits are in widespread use for communications, entertainment, multimedia, biomedical, and many other applications that interface with the physical world. Although analog CMOS design is greatly complicated by the design choices of drain current, channel width, and channel length present for every MOS device in a circuit, these design choices afford significant opportunities for optimizing circuit performance." "This book addresses tradeoffs and optimization of device and circuit performance for selections of the drain current, inversion coefficient, and channel length, where channel width is implicitly considered. The inversion coefficient is used as a technology independent measure of MOS inversion that permits design freely in weak, moderate, and strong inversion."--BOOK JACKET. |
| Beschreibung: | Literaturverz. S. 562 - 563 |
| Beschreibung: | XXXV, 594 S. graph. Darst. |
| ISBN: | 9780470031360 |
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| 245 | 1 | 0 | |a Tradeoffs and optimization in analog CMOS design |c David M. Binkley |
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| 520 | 1 | |a "Analog CMOS (complementary metal-oxide-semiconductor) integrated circuits are in widespread use for communications, entertainment, multimedia, biomedical, and many other applications that interface with the physical world. Although analog CMOS design is greatly complicated by the design choices of drain current, channel width, and channel length present for every MOS device in a circuit, these design choices afford significant opportunities for optimizing circuit performance." "This book addresses tradeoffs and optimization of device and circuit performance for selections of the drain current, inversion coefficient, and channel length, where channel width is implicitly considered. The inversion coefficient is used as a technology independent measure of MOS inversion that permits design freely in weak, moderate, and strong inversion."--BOOK JACKET. | |
| 650 | 7 | |a Circuits électroniques - Calcul |2 ram | |
| 650 | 7 | |a MOS complémentaires |2 ram | |
| 650 | 4 | |a Metal oxide semiconductors, Complementary |x Design and construction | |
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Datensatz im Suchindex
| _version_ | 1804137936593092608 |
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| adam_text | TRADEOFFS AND OPTIMIZATION IN ANALOG CMOS DESIGN DAVID M. BINKLEY
UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE, USA A JOHN WILEY & SONS,
LTD., PUBLICATION CONTENTS FOREWORD XVII PREFACE XXI ACKNOWLEDGMERITS
XXIII LIST OF SYMBOLS AND ABBREVIATIONS XXV 1 INTRODUCTION 1 1.1
IMPORTANCE OF TRADEOFFS AND OPTIMIZATION IN ANALOG CMOS DESIGN 1 1.2
INDUSTRY DESIGNERS AND UNIVERSITY STUDENTS AS READERS 2 1.3 ORGANIZATION
AND OVERVIEW OF BOOK 3 1.4 FUELL OR SELECTIVE READING OF BOOK 5 1.5
EXAMPLE TECHNOLOGIES AND TECHNOLOGY EXTENSIONS 6 1.6 LIMITATIONS OF THE
METHODS 6 1.7 DISCLAIMER 7 PART I MOS DEVICE PERFORMANCE, TRADEOFFS AND
OPTIMIZATION FOR ANALOG CMOS DESIGN 9 2 MOS DESIGN FROM WEAK THROUGH
STRONG INVERSION 11 2.1 INTRODUCTION 11 2.2 MOS DESIGN COMPLEXITY
COMPARED TO BIPOLAR DESIGN 12 2.3 BIPOLAR TRANSISTOR COLLECTOR CURRENT
AND TRANSCONDUCTANCE 12 2.4 MOS DRAIN CURRENT AND TRANSCONDUCTANCE 13
2.4.1 IN WEAK INVERSION 13 2.4.2 IN STRONG INVERSION WITHOUT VELOCITY
SATURATION EFFECTS 14 2.4.3 IN STRONG INVERSION WITH VELOCITY SATURATION
EFFECTS 16 2.4.4 IN MODERATE INVERSION AND ALL REGIONS OF OPERATION 18
2.5 MOS DRAIN-SOURCE CONDUCTANCE 23 2.6 ANALOG CMOS ELECTRONIC DESIGN
AUTOMATION TOOLS AND DESIGN METHODS 25 2.6.1 ELECTRONIC DESIGN
AUTOMATION TOOLS 25 2.6.2 DESIGN METHODS 28 2.6.3 PREVIOUS APPLICATION
OF DESIGN METHODS PRESENTED IN THIS BOOK 29 REFERENCES 30 3 MOS
PERFORMANCE VERSUS DRAIN CURRENT, INVERSION COEFFICIENT, AND CHANNEL
LENGTH 33 3.1 INTRODUCTION 33 3.2 ADVANTAGES OF SELECTING DRAIN CURRENT,
INVERSION COEFFICIENT, AND CHANNEL LENGTH IN ANALOG CMOS DESIGN 34 VIII
CONTENTS 3.2.1 OPTIMIZING DRAIN CURRENT, INVERSION COEFFICIENT, AND
CHANNEL LENGTH SEPARATELY 35 3.2.2 DESIGN IN MODERATE INVERSION 35 3.2.3
DESIGN INCLUSIVE OF VELOCITY SATURATION EFFECTS 36 3.2.4 DESIGN WITH
TECHNOLOGY INDEPENDENCE 36 3.2.5 SIMPLE PREDICTIONS OF PERFORMANCE AND
TRENDS 36 3.2.6 MINIMIZING ITERATIVE COMPUTER SIMULATIONS - PRESPICE
GUIDANCE 37 3.2.7 OBSERVING PERFORMANCE TRADEOFFS - THE MOSFET OPERATING
PLANE 37 3.2.8 CROSS-CHECKING WITH COMPUTER SIMULATION MOS MODELS 39 3.3
PROCESS PARAMETERS FOR EXAMPLE PROCESSES 40 3.3.1 CALCULATION OF
COMPOSITE PROCESS PARAMETERS 40 3.3.2 DC, SMALL-SIGNAL, AND INTRINSIC
GATE CAPACITANCE PARAMETERS 42 3.3.3 FLICKER NOISE AND LOCAL-AREA DC
MISMATCH PARAMETERS 44 3.3.4 GATE-OVERLAP AND DRAIN-BODY CAPACITANCE
PARAMETERS 45 3.3.5 TEMPERATURE PARAMETERS 46 3.4 SUBSTRATE FACTOR AND
INVERSION COEFFICIENT 46 3.4.1 SUBSTRATE FACTOR 47 3.4.2 INVERSION
COEFFICIENT 50 3.4.2.1 TRADITIONAL INVERSION COEFFICIENT 50 3.4.2.2
FIXED-NORMALIZED INVERSION COEFFICIENT 51 3.4.2.3 USING THE
FIXED-NORMALIZED INVERSION COEFFICIENT IN DESIGN 52 3.4.2.4 REGIONS AND
SUBREGIONS OF INVERSION 53 3.5 TEMPERATURE EFFECTS 55 3.5.1 BANDGAP
ENERGY, THERMAL VOLTAGE, AND SUBSTRATE FACTOR 55 3.5.2 MOBILITY,
TRANSCONDUCTANCE FACTOR, AND TECHNOLOGY CURRENT 57 3.5.3 INVERSION
COEFFICIENT 59 3.5.4 THRESHOLD VOLTAGE 60 3.5.5 DESIGN CONSIDERATIONS 60
3.6 SIZING RELATIONSHIPS 61 3.6.1 SHAPE FACTOR 62 3.6.2 CHANNEL WIDTH 64
3.6.3 GATE AREA AND SILICON COST 65 3.7 DRAIN CURRENT AND BIAS VOLTAGES
67 3.7.1 DRAIN CURRENT 67 3.7.1.1 WITHOUT SMALL-GEOMETRY EFFECTS 68
3.7.1.2 WITH VELOCITY SATURATION EFFECTS 70 3.7.1.3 WITH VFMR EFFECTS 72
3.7.1.4 WITH VELOCITY SATURATION AND VFMR EFFECTS 72 3.7.1.5 THE
EQUIVALENT VELOCITY SATURATION VOLTAGE 75 3.7.1.6 PREDICTED AND MEASURED
VALUES 76 3.7.1.7 THE EXTRAPOLATED THRESHOLD VOLTAGE 79 3.7.2 EFFECTIVE
GATE-SOURCE VOLTAGE 80 3.7.2.1 WITHOUT SMALL-GEOMETRY EFFECTS 80 3.7.2.2
WITH VELOCITY SATURATION AND VFMR EFFECTS 82 3.7.2.3 PREDICTED AND
MEASURED VALUES 86 3.7.2.4 SUMMARY OF TRENDS 88 3.7.3 DRAIN-SOURCE
SATURATION VOLTAGE 89 3.7.3.1 PHYSICAL VERSUS CIRCUIT DEFMITION 89
3.7.3.2 WITHOUT SMALL-GEOMETRY EFFECTS 90 3.7.3.3 WITH VELOCITY
SATURATION EFFECTS 92 CONTENTS IX 3.7.3.4 PREDICTED AND MEASURED VALUES
96 3.7.3.5 SUMMARY OF TRENDS 97 3.8 SMALL-SIGNAL PARAMETERS AND
INTRINSIC VOLTAGE GAIN 98 3.8.1 SMALL-SIGNAL MODEL AND ITS APPLICATION
98 3.8.2 TRANSCONDUCTANCE 103 3.8.2.1 WITHOUT SMALL-GEOMETRY EFFECTS 103
3.8.2.2 WITH VELOCITY SATURATION AND VFMR EFFECTS 106 3.8.2.3 PREDICTED
AND MEASURED VALUES 111 3.8.2.4 SUMMARY OF TRENDS 113 3.8.2.5 UNIVERSAL
G M /I D CHARACTERISTIC IN CMOS TECHNOLOGIES 115 3.8.2.6 DISTORTION 115
3.8.3 BODY-EFFECT TRANSCONDUCTANCE AND RELATIONSHIP TO SUBSTRATE FACTOR
121 3.8.3.1 SUBSTRATE FACTOR 122 3.8.3.2 BODY-EFFECT TRANSCONDUCTANCE
125 3.8.3.3 PREDICTED AND MEASURED VALUES 126 3.8.3.4 SUMMARY OF TRENDS
129 3.8.4 DRAIN CONDUCTANCE 130 ^3.8.4.1 DUE TO CHANNEL LENGTH
MODULATION 131 3.8.4.2 DUETODIBL 141 3.8.4.3 DUE TO HOT-ELECTRON EFFECTS
146 3.8.4.4 IMPACT OF INCREASE NEAR V DSSAL 150 3.8.4.5 MEASURED VALUES
152 3.8.4.6 SUMMARY OF TRENDS 161 3.8.5 INTRINSIC VOLTAGE GAIN 163 3.9
CAPACITANCES AND BANDWIDTH 169 3.9.1 GATE-OXIDE CAPACITANCE 169 3.9.2
INTRINSIC GATE CAPACITANCES 170 3.9.3 EXTRINSIC GATE-OVERLAP
CAPACITANCES 173 3.9.4 DRAIN-BODY AND SOURCE-BODY JUNCTION CAPACITANCES
176 3.9.5 INTRINSIC DRAIN-BODY AND SOURCE-BODY CAPACITANCES 179 3.9.6
INTRINSIC BANDWIDTH 179 3.9.7 EXTRINSIC AND DIODE-CONNECTED BANDWIDTHS
185 3.10 NOISE 188 3.10.1 THERMAL NOISE IN THE OHMIC REGION 189 3.10.2
THERMAL NOISE IN THE SATURATION REGION 190 3.10.2.1 WITHOUT
SMALL-GEOMETRY EFFECTS 190 3.10.2.2 WITH SMALL-GEOMETRY EFFECTS 193
3.10.2.3 SUMMARY OF DRAIN-REFERRED AND GATE-REFERRED THERMAL NOISE 194
3.10.3 FLICKER NOISE 200 3.10.3.1 CARRIER DENSITY FLUCTUATION MODEL 201
3.10.3.2 CARRIER MOBILITY FLUCTUATION MODEL 203 3.10.3.3 UNIFIED,
CARRIER DENSITY, CORRELATED MOBILITY FLUCTUATION MODEL 204 3.10.3.4
FLICKER-NOISE PREDICTION FROM FLICKER-NOISE FACTORS 207 3.10.3.5
REPORTED FLICKER-NOISE FACTORS AND TRENDS 209 3.10.3.6 MEASURED AND
PREDICTED FLICKER NOISE 212 3.10.3.7 SUMMARY OF GATE-REFERRED AND
DRAIN-REFERRED FLICKER NOISE 217 3.10.3.8 FLICKER-NOISE CORNER FREQUENCY
224 3.10.4 GATE, SUBSTRATE, AND SOURCE RESISTANCE THERMAL NOISE 227
3.10.5 CHANNEL AVALANCHE NOISE 229 3.10.6 INDUCED GATE NOISE CURRENT 229
3.10.7 GATE LEAKAGE NOISE CURRENT 231 CONTENTS 3.11 MISMATCH 233 3.11.1
LOCAL-AREA DC MISMATCH 233 3.11.1.1 MODELING 233 3.11.1.2 REPORTED
MISMATCH FACTORS AND TRENDS 237 3.11.1.3 EDGE EFFECTS AND OTHER MODEL
LIMITATIONS 239 3.11.1.4 CALCULATING GATE-SOURCE VOLTAGE AND DRAIN
CURRENT MISMATCH 241 3.11.1.5 THRESHOLD-VOLTAGE MISMATCH INCREASE FOR
NON-ZERO V SB 244 3.11.1.6 THRESHOLD-VOLTAGE DOMINANCE OF MISMATCH 246
3.11.1.7 SUMMARY OF GATE-SOURCE VOLTAGE AND DRAIN CURRENT MISMATCH 247
3.11.2 DISTANCE DC MISMATCH 254 3.11.2.1 MODELING 254 3.11.2.2 REPORTED
MISMATCH FACTORS AND TRENDS 255 3.11.2.3 GATE-SOURCE VOLTAGE AND DRAIN
CURRENT MISMATCH 256 3.11.2.4 THRESHOLD-VOLTAGE DOMINANCE OF MISMATCH
258 3.11.2.5 CRITICAL SPACING FOR COMPARABLE DISTANCE AND LOCAL-AREA
MISMATCH 258 3.11.3 DC MISMATCH EFFECTS ON CIRCUIT PERFORMANCE 259
3.11.3.1 BANDWIDTH, POWER, AND ACCURACY TRADEOFFS IN CURRENT-MODE
CIRCUITS 259 3.11.3.2 BANDWIDTH, POWER, AND ACCURACY TRADEOFFS IN
VOLTAGE-MODE CIRCUITS 262 3.11.3.3 TIRNING SKEW IN DIGITAL CIRCUITS 264
3.11.4 SMALL-SIGNAL PARAMETER AND CAPACITANCE MISMATCH 265 3.11.4.1
TRANSCONDUCTANCE MISMATCH 265 3.11.4.2 DRAIN-SOURCE CONDUCTANCE MISMATCH
267 3.11.4.3 MISMATCH EFFECTS ON CIRCUIT PERFORMANCE 268 3.12 LEAKAGE
CURRENT 268 3.12.1 GATE LEAKAGE CURRENT AND CONDUCTANCE 268 3.12.1.1
GATE CURRENT 269 3.12.1.2 GATE CONDUCTANCE - 273 3.12.2 GATE LEAKAGE
CURRENT EFFECTS ON CIRCUIT PERFORMANCE 274 3.12.2.1 MINIMUM FREQUENCY OF
OPERATION 274 3.12.2.2 INTRINSIC CURRENT GAIN 275 3.12.2.3 DISCHARGE OF
CAPACITANCES 276 3.12.2.4 NOISE 277 3.12.2.5 MISMATCH 277 3.12.2.6
SUMMARY OF TRADEOFFS 278 3.12.3 DRAIN-BODY AND SOURCE-BODY LEAKAGE
CURRENT 279 3.12.4 SUBTHRESHOLD DRAIN LEAKAGE CURRENT 282 REFERENCES 283
TRADEOFFS IN MOS PERFORMANCE, AND DESIGN OF DIFFERENTIAL PAIRS AND
CURRENT MIRRORS 295 4.1 INTRODUCTION 295 4.2 PERFORMANCE TRENDS 296
4.2.1 EXPLORING DRAIN CURRENT, INVERSION COEFFICIENT, AND CHANNEL LENGTH
SEPARATELY 296 4.2.2 TRENDS AS INVERSION COEFFICIENT INCREASES 297 4.2.3
TRENDS AS CHANNEL LENGTH INCREASES 300 4.2.4 TRENDS AS DRAIN CURRENT
INCREASES 302 4.3 PERFORMANCE TRADEOFFS 303 4.3.1 OVERVIEW - THE MOSFET
OPERATING PLANE 303 4.3.2 REGION AND LEVEL OF INVERSION - THE INVERSION
COEFFICIENT AS A NUMBER LINE 304 CONTENTS XI 4.3.3 TRADEOFFS COMMON TO
ALL DEVICES 306 4.3.3.1 CHANNEL WIDTH AND GATE AREA 309 4.3.3.2
INTRINSIC GATE CAPACITANCE AND DRAIN-BODY CAPACITANCE 310 4.3.3.3
EFFECTIVE GATE-SOURCE VOLTAGE AND DRAIN-SOURCE SATURATION VOLTAGE 312
4.3.3.4 TRANSCONDUCTANCE EFFICIENCY AND EARLY VOLTAGE 314 4.3.3.5
INTRINSIC VOLTAGE GAIN AND BANDWIDTH 317 4.3.4 TRADEOFFS SPECIFIC TO
DIFFERENTIAL-PAIR DEVICES 320 4.3.4.1 TRANSCONDUCTANCE DISTORTION 320
4.3.4.2 INTRINSIC GATE CAPACITANCE AND GATE-REFERRED THERMAL-NOISE
VOLTAGE 323 4.3.4.3 GATE-REFERRED FLICKER-NOISE VOLTAGE AND GATE-SOURCE
MISMATCH VOLTAGE 325 4.3.5 TRADEOFFS SPECIFIC TO CURRENT-MIRROR DEVICES
328 4.3.5.1 INTRINSIC BANDWIDTH AND DRAIN-REFERRED THERMAL-NOISE CURRENT
329 4.3.5.2 DRAIN-REFERRED FLICKER-NOISE CURRENT AND DRAIN MISMATCH
CURRENT 333 4.3.6 TRADEOFFS IN FIGURES OF MERIT 336 4.3.6.1
TRANSCONDUCTANCE EFFICIENCY AND EARLY VOLTAGE 338 4.3.6.2 INTRINSIC
VOLTAGE GAIN, BANDWIDTH, AND GAIN-BANDWIDTH 338 4.3.6.3 TRANSCONDUCTANCE
EFFICIENCY AND INTRINSIC BANDWIDTH 339 4.3.6.4 THERMAL-NOISE EFFICIENCY
AND FLICKER-NOISE AREA EFFICIENCY 340 4.3.6.5 BANDWIDTH, POWER, AND
ACCURACY WITH DC OFFSET 340 4.3.6.6 BANDWIDTH, POWER, AND ACCURACY WITH
THERMAL NOISE 342 4.3.6.7 COMPARISON OF BANDWIDTH, POWER, AND ACCURACY
FOR DC OFFSET AND THERMAL NOISE 345 4.3.6.8 EXTENSIONS 345 4.4 DESIGN OF
DIFFERENTIAL PAIRS AND CURRENT MINORS USING THE ANALOG CMOS DESIGN,
TRADEOFFS AND OPTIMIZATION SPREADSHEET 346 4.4.1 SELECTING INVERSION
COEFFICIENT 348 4.4.2 SELECTING CHANNEL LENGTH 353 4.4.3 SELECTING DRAIN
CUNENT 359 4.4.4 OPTIMIZING FOR DC, BALANCED, AND AC PERFORMANCE 363
4.4.4.1 DC OPTIMIZATION 364 4.4.4.2 AC OPTIMIZATION 366 4.4.4.3 BALANCED
OPTIMIZATION 366 4.4.4.4 OPTIMIZATIONS AT MILLIPOWER OPERATION 367
4.4.4.5 OPTIMIZATIONS AT MICROPOWER OPERATION 369 4.4.4.6 SUMMARY OF
MICROPOWER PERFORMANCE CONSIDERATIONS 372 4.4.5 SUMMARY PROCEDURE FOR
DEVICE OPTIMIZATION 372 REFERENCES 373 PART II CIRCUIT DESIGN EXAMPLES
ILLUSTRATING OPTIMIZATION FOR ANALOG CMOS DESIGN 375 5 DESIGN OF CMOS
OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS OPTIMIZED FOR DC, BALANCED, AND
AC PERFORMANCE 377 5.1 INTRODUCTION 377 5.2 CIRCUIT DESCRIPTION 379
5.2.1 SIMPLE OTAS 379 5.2.2 CASCODED OTAS 380 5.3 CIRCUIT ANALYSIS AND
PERFORMANCE OPTIMIZATION 382 5.3.1 TRANSCONDUCTANCE 383 5.3.1.1 SIMPLE
OTAS 383 5.3.1.2 CASCODED OTAS 384 XUE CONTENTS 5.3.1.3 OPTIMIZATION 384
5.3.2 OUTPUT RESISTANCE 385 5.3.2.1 SIMPLE OTAS 385 5.3.2.2 CASCODEDOTAS
385 5.3.2.3 OPTIMIZATION 387 5.3.3 VOLTAGE GAIN 387 5.3.3.1 SIMPLE OTAS
387 5.3.3.2 CASCODED OTAS 388 5.3.3.3 OPTIMIZATION 388 5.3.4 FREQUENCY
RESPONSE 389 5.3.4.1 SIMPLE OTAS 389 5.3.4.2 CASCODEDOTAS 391 5.3.4.3
OPTIMIZATION 392 5.3.5 THERMAL NOISE 393 5.3.5.1 SIMPLE OTAS 393 5.3.5.2
CASCODED OTAS 394 5.3.5.3 OPTIMIZATION 396 5.3.6 FLICKER NOISE 397
5.3.6.1 SIMPLE OTAS 397 5.3.6.2 CASCODEDOTAS 399 5.3.6.3 OPTIMIZATION
400 5.3.7 OFFSET VOLTAGE DUE TO LOCAL-AREA MISMATCH 403 5.3.7.1 SIMPLE
OTAS 403 5.3.7.2 CASCODED OTAS 407 5.3.7.3 OPTIMIZATION 409 5.3.8
SYSTEMATIC OFFSET VOLTAGE FOR SIMPLE OTAS 412 5.3.9 INPUT AND OUTPUT
CAPACITANCES 413 5.3.9.1 SIMPLE OTAS 413 5.3.9.2 CASCODEDOTAS 415
5.3.9.3 OPTIMIZATION 416 5.3.10 SLEW RATE 417 5.3.10.1 SIMPLE OTAS 417
5.3.10.2 CASCODED OTAS 417 5.3.10.3 OPTIMIZATION 417 5.3.11 INPUT AND
OUTPUT VOLTAGE RANGES 417 5.3.11.1 SIMPLE OTAS 417 5.3.11.2 CASCODEDOTAS
419 5.3.11.3 OPTIMIZATION 421 5.3.12 INPUT, 1 DB COMPRESSION VOLTAGE 423
5.3.12.1 SIMPLE OTAS 423 5.3.12.2 CASCODEDOTAS 423 5.3.12.3 OPTIMIZATION
424 5.3.13 MANAGEMENT OF SMALL-GEOMETRY EFFECTS 424 5.4 DESIGN
OPTIMIZATION AND RESULTING PERFORMANCE FOR THE SIMPLE OTAS 425 5.4.1
SELECTION OF MOSFET INVERSION COEFFICIENTS AND CHANNEL LENGTHS 425
5.4.1.1 DC OPTIMIZATION 429 5.4.1.2 AC OPTIMIZATION 430 5.4.1.3 BALANCED
OPTIMIZATION 431 5.4.2 PREDICTED AND MEASURED PERFORMANCE 431 5.4.2.1
TRANSCONDUCTANCE, OUTPUT RESISTANCE, AND VOLTAGE GAIN 435 5.4.2.2
FREQUENCY RESPONSE 439 CONTENTS XIII 5.4.2.3 THERMAL NOISE 439 5.4.2.4
FLICKER NOISE 440 5.4.2.5 OFFSET VOLTAGE DUE TO LOCAL-AREA MISMATCH 441
5.4.2.6 SYSTEMATIC OFFSET VOLTAGE 442 5.4.2.7 INPUT AND OUTPUT
CAPACITANCES 442 5.4.2.8 SLEWRATE 442 5.4.2.9 INPUT AND OUTPUT VOLTAGE
RANGES 443 5.4.2.10 INPUT, LDB COMPRESSION VOLTAGE 443 5.4.2.11 LAYOUT
AREA 444 5.4.2.12 TRADEOFFS IN DC ACCURACY, LOW-FREQUENCY AC ACCURACY,
VOLTAGE GAIN, AND TRANSCONDUCTANCE BANDWIDTH 446 5.4.3 OTHER
OPTIMIZATIONS: ENSURING INPUT DEVICES DOMINATE THERMAL NOISE 447 5.5
DESIGN OPTIMIZATION AND RESULTING PERFORMANCE FOR THE CASCODED OTAS 448
5.5.1 SELECTION OF MOSFET INVERSION COEFFICIENTS AND CHANNEL LENGTHS 448
5.5.1.1 DC OPTIMIZATION 451 5.5.1.2 AC OPTIMIZATION 452 5.5.1.3 B
ALANCED OPTIMIZATION 453 5.5.2 PREDICTED AND MEASURED PERFORMANCE 453
5.5.2.1 TRANSCONDUCTANCE, OUTPUT RESISTANCE, AND VOLTAGE GAIN 458
5.5.2.2 FREQUENCY RESPONSE 461 5.5.2.3 THERMAL NOISE 462 5.5.2.4 FLICKER
NOISE 463 5.5.2.5 OFFSET VOLTAGE DUE TO LOCAL-AREA MISMATCH 464 5.5.2.6
INPUT AND OUTPUT CAPACITANCES 466 5.5.2.7 SLEW RATE 467 5.5.2.8 INPUT
AND OUTPUT VOLTAGE RANGES 467 5.5.2.9 INPUT, 1 DB COMPRESSION VOLTAGE
468 5.5.2.10 LAYOUT AREA 468 5.5.2.11 TRADEOFFS IN DC ACCURACY,
LOW-FREQUENCY AC ACCURACY, VOLTAGE GAIN, AND TRANSCONDUCTANCE BANDWIDTH
470 5.5.2.12 COMPARISON OF PERFORMANCE TRADEOFFS WITH THOSE OF SIMPLE
OTAS 472 5.5.3 OTHER OPTIMIZATIONS: ENSURING INPUT DEVICES DOMINATE
FLICKER NOISE AND LOCAL-AREA MISMATCH 472 5.5.4 OTHER OPTIMIZATIONS:
COMPLEMENTING THE DESIGN 473 5.6 PREDICTION ACCURACY FOR DESIGN GUIDANCE
AND OPTIMIZATION 474 REFERENCES 476 DESIGN OF MICROPOWER CMOS
PREAMPLIFIERS OPTIMIZED FOR LOW THERMAL AND FLICKER NOISE 477 6.1
INTRODUCTION 477 6.2 USING THE LATERAL BIPOLAR TRANSISTOR FOR
LOW-FLICKER-NOISE APPLICATIONS 478 6.3 MEASURES OF PREAMPLIFIER NOISE
PERFORMANCE 479 6.3.1 THERMAL-NOISE EFFICIENCY FACTOR 479 6.3.2
FLICKER-NOISE AREA EFFICIENCY FACTOR 482 6.4 REPORTED MICROPOWER,
LOW-NOISE CMOS PREAMPLIFIERS 483 6.5 MOS NOISE VERSUS THE BIAS
COMPLIANCE VOLTAGE 486 6.5.1 TRANSCONDUCTANCE IN SATURATION 486 6.5.2
DRAIN-SOURCE RESISTANCE AND TRANSCONDUCTANCE IN THE DEEP OHMIC REGION
489 6.5.3 GATE NOISE VOLTAGE 491 6.5.3.1 THERMAL NOISE 491 6.5.3.2
FLICKER NOISE 493 XIV CONTENTS 6.5.4 DRAIN NOISE CURRENT 494 6.5.4.1
THERMAL NOISE 494 6.5.4.2 FLICKER NOISE 494 6.5.5 DRAIN NOISE CURRENT
WITH RESISTIVE SOURCE DEGENERATION 496 6.5.5.1 BIAS COMPLIANCE VOLTAGE
496 6.5.5.2 THERMAL NOISE 497 6.5.5.3 FLICKER NOISE 500 6.6 EXTRACTION
OF MOS FLICKER-NOISE PARAMETERS 504 6.6.1 PREAMPLIFIER INPUT DEVICES 504
6.6.2 PREAMPLIFIER NON-INPUT DEVICES 506 6.6.3 COMPARISONS OF RICKER
NOISE 507 6.7 DIFFERENTIAL INPUT PREAMPLIFIER 507 6.7.1 DESCRIPTION 507
6.7.2 CIRCUIT ANALYSIS, PERFORMANCE OPTIMIZATION, AND PREDICTED
PERFORMANCE 509 6.7.2.1 VOLTAGE GAIN 510 6.7.2.2 FREQUENCY RESPONSE 511
6.7.2.3 THERMAL NOISE 511 6.7.2.4 THERMAL NOISE EXPRESSED FROM DC BIAS
CONDITIONS 512 6.7.2.5 FLICKER NOISE 516 6.7.2.6 FLICKER NOISE EXPRESSED
FROM DC BIAS CONDITIONS 517 6.7.3 SUMMARY OF PREDICTED AND MEASURED
PERFORMANCE 520 6.7.3.1 MOSFET DESIGN SELECTIONS 521 6.7.3.2 RESULTING
PREAMPLIFIER PERFORMANCE 525 6.7.4 DESIGN IMPROVEMENTS 529 6.8
SINGLE-ENDED INPUT PREAMPLIFIER 531 6.8.1 DESCRIPTION 531 6.8.2 CIRCUIT
ANALYSIS, PERFORMANCE OPTIMIZATION, AND PREDICTED PERFORMANCE 532
6.8.2.1 VOLTAGE GAIN 533 6.8.2.2 FREQUENCY RESPONSE 534 6.8.2.3 THERMAL
NOISE 535 6.8.2.4 THERMAL NOISE EXPRESSED FROM DC BIAS CONDITIONS 536
6.8.2.5 FLICKER NOISE 538 6.8.2.6 FLICKER NOISE EXPRESSED FROM DC BIAS
CONDITIONS 539 6.8.3 SUMMARY OF PREDICTED AND MEASURED PERFORMANCE 541
6.8.3.1 MOSFET DESIGN SELECTIONS 541 6.8.3.2 RESULTING PREAMPLIFIER
PERFORMANCE 543 6.8.4 DESIGN IMPROVEMENTS 547 6.9 PREDICTION ACCURACY
FOR DESIGN GUIDANCE AND OPTIMIZATION 549 6.10 SUMMARY OF LOW-NOISE
DESIGN METHODS AND RESULTING CHALLENGES IN LOW-VOLTAGE PROCESSES 550
REFERENCES 552 EXTENDING OPTIMIZATION METHODS TO SMALLER-GEOMETRY CMOS
PROCESSES AND FUTURE TECHNOLOGIES 555 7.1 INTRODUCTION 555 7.2 USING THE
INVERSION COEFFICIENT FOR CMOS PROCESS INDEPENDENCE AND FOR EXTENSION TO
SMALLER-GEOMETRY PROCESSES 556 7.2.1 UNIVERSAL G M /I D , V EFF , AND V
DSSAL CHARACTERISTICS ACROSS CMOS PROCESSES 556 CONTENTS 7.2.2 OTHER
NEARLY UNIVERSAL PERFORMANCE CHARACTERISTICS ACROSS CMOS PROCESSES 556
7.2.3 PORTING DESIGNS ACROSS CMOS PROCESSES 557 7.2.4 EXTENDING DESIGN
METHODS TO SMALLER-GEOMETRY PROCESSES 560 7.3 ENHANCING OPTIMIZATION
METHODS BY INCLUDING GATE LEAKAGE CURRENT EFFECTS 560 7.4 USING AN
INVERSION COEFFICIENT MEASURE FOR NON-CMOS TECHNOLOGIES 561 REFERENCES
562 APPENDIX: THE ANALOG CMOS DESIGN, TRADEOFFS AND OPTIMIZATION
SPREADSHEET 565 INDEX 583
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TRADEOFFS AND OPTIMIZATION IN ANALOG CMOS DESIGN DAVID M. BINKLEY
UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE, USA A JOHN WILEY & SONS,
LTD., PUBLICATION CONTENTS FOREWORD XVII PREFACE XXI ACKNOWLEDGMERITS
XXIII LIST OF SYMBOLS AND ABBREVIATIONS XXV 1 INTRODUCTION 1 1.1
IMPORTANCE OF TRADEOFFS AND OPTIMIZATION IN ANALOG CMOS DESIGN 1 1.2
INDUSTRY DESIGNERS AND UNIVERSITY STUDENTS AS READERS 2 1.3 ORGANIZATION
AND OVERVIEW OF BOOK 3 1.4 FUELL OR SELECTIVE READING OF BOOK 5 1.5
EXAMPLE TECHNOLOGIES AND TECHNOLOGY EXTENSIONS 6 1.6 LIMITATIONS OF THE
METHODS 6 1.7 DISCLAIMER 7 PART I MOS DEVICE PERFORMANCE, TRADEOFFS AND
OPTIMIZATION FOR ANALOG CMOS DESIGN 9 2 MOS DESIGN FROM WEAK THROUGH
STRONG INVERSION 11 2.1 INTRODUCTION 11 2.2 MOS DESIGN COMPLEXITY
COMPARED TO BIPOLAR DESIGN 12 2.3 BIPOLAR TRANSISTOR COLLECTOR CURRENT
AND TRANSCONDUCTANCE 12 2.4 MOS DRAIN CURRENT AND TRANSCONDUCTANCE 13
2.4.1 IN WEAK INVERSION 13 2.4.2 IN STRONG INVERSION WITHOUT VELOCITY
SATURATION EFFECTS 14 2.4.3 IN STRONG INVERSION WITH VELOCITY SATURATION
EFFECTS 16 2.4.4 IN MODERATE INVERSION AND ALL REGIONS OF OPERATION 18
2.5 MOS DRAIN-SOURCE CONDUCTANCE 23 2.6 ANALOG CMOS ELECTRONIC DESIGN
AUTOMATION TOOLS AND DESIGN METHODS 25 2.6.1 ELECTRONIC DESIGN
AUTOMATION TOOLS 25 2.6.2 DESIGN METHODS 28 2.6.3 PREVIOUS APPLICATION
OF DESIGN METHODS PRESENTED IN THIS BOOK 29 REFERENCES 30 3 MOS
PERFORMANCE VERSUS DRAIN CURRENT, INVERSION COEFFICIENT, AND CHANNEL
LENGTH 33 3.1 INTRODUCTION 33 3.2 ADVANTAGES OF SELECTING DRAIN CURRENT,
INVERSION COEFFICIENT, AND CHANNEL LENGTH IN ANALOG CMOS DESIGN 34 VIII
CONTENTS 3.2.1 OPTIMIZING DRAIN CURRENT, INVERSION COEFFICIENT, AND
CHANNEL LENGTH SEPARATELY 35 3.2.2 DESIGN IN MODERATE INVERSION 35 3.2.3
DESIGN INCLUSIVE OF VELOCITY SATURATION EFFECTS 36 3.2.4 DESIGN WITH
TECHNOLOGY INDEPENDENCE 36 3.2.5 SIMPLE PREDICTIONS OF PERFORMANCE AND
TRENDS 36 3.2.6 MINIMIZING ITERATIVE COMPUTER SIMULATIONS - "PRESPICE"
GUIDANCE 37 3.2.7 OBSERVING PERFORMANCE TRADEOFFS - THE MOSFET OPERATING
PLANE 37 3.2.8 CROSS-CHECKING WITH COMPUTER SIMULATION MOS MODELS 39 3.3
PROCESS PARAMETERS FOR EXAMPLE PROCESSES 40 3.3.1 CALCULATION OF
COMPOSITE PROCESS PARAMETERS 40 3.3.2 DC, SMALL-SIGNAL, AND INTRINSIC
GATE CAPACITANCE PARAMETERS 42 3.3.3 FLICKER NOISE AND LOCAL-AREA DC
MISMATCH PARAMETERS 44 3.3.4 GATE-OVERLAP AND DRAIN-BODY CAPACITANCE
PARAMETERS 45 3.3.5 TEMPERATURE PARAMETERS 46 3.4 SUBSTRATE FACTOR AND
INVERSION COEFFICIENT 46 3.4.1 SUBSTRATE FACTOR 47 3.4.2 INVERSION
COEFFICIENT 50 3.4.2.1 TRADITIONAL INVERSION COEFFICIENT 50 3.4.2.2
FIXED-NORMALIZED INVERSION COEFFICIENT 51 3.4.2.3 USING THE
FIXED-NORMALIZED INVERSION COEFFICIENT IN DESIGN 52 3.4.2.4 REGIONS AND
SUBREGIONS OF INVERSION 53 3.5 TEMPERATURE EFFECTS 55 3.5.1 BANDGAP
ENERGY, THERMAL VOLTAGE, AND SUBSTRATE FACTOR 55 3.5.2 MOBILITY,
TRANSCONDUCTANCE FACTOR, AND TECHNOLOGY CURRENT 57 3.5.3 INVERSION
COEFFICIENT 59 3.5.4 THRESHOLD VOLTAGE 60 3.5.5 DESIGN CONSIDERATIONS 60
3.6 SIZING RELATIONSHIPS 61 3.6.1 SHAPE FACTOR 62 3.6.2 CHANNEL WIDTH 64
3.6.3 GATE AREA AND SILICON COST 65 3.7 DRAIN CURRENT AND BIAS VOLTAGES
67 3.7.1 DRAIN CURRENT 67 3.7.1.1 WITHOUT SMALL-GEOMETRY EFFECTS 68
3.7.1.2 WITH VELOCITY SATURATION EFFECTS 70 3.7.1.3 WITH VFMR EFFECTS 72
3.7.1.4 WITH VELOCITY SATURATION AND VFMR EFFECTS 72 3.7.1.5 THE
EQUIVALENT VELOCITY SATURATION VOLTAGE 75 3.7.1.6 PREDICTED AND MEASURED
VALUES 76 3.7.1.7 THE EXTRAPOLATED THRESHOLD VOLTAGE 79 3.7.2 EFFECTIVE
GATE-SOURCE VOLTAGE 80 3.7.2.1 WITHOUT SMALL-GEOMETRY EFFECTS 80 3.7.2.2
WITH VELOCITY SATURATION AND VFMR EFFECTS\ 82 3.7.2.3 PREDICTED AND
MEASURED VALUES 86 3.7.2.4 SUMMARY OF TRENDS 88 3.7.3 DRAIN-SOURCE
SATURATION VOLTAGE 89 3.7.3.1 PHYSICAL VERSUS CIRCUIT DEFMITION 89
3.7.3.2 WITHOUT SMALL-GEOMETRY EFFECTS 90 3.7.3.3 WITH VELOCITY
SATURATION EFFECTS 92 CONTENTS IX 3.7.3.4 PREDICTED AND MEASURED VALUES
96 3.7.3.5 SUMMARY OF TRENDS 97 3.8 SMALL-SIGNAL PARAMETERS AND
INTRINSIC VOLTAGE GAIN 98 3.8.1 SMALL-SIGNAL MODEL AND ITS APPLICATION
98 3.8.2 TRANSCONDUCTANCE 103 3.8.2.1 WITHOUT SMALL-GEOMETRY EFFECTS 103
3.8.2.2 WITH VELOCITY SATURATION AND VFMR EFFECTS 106 3.8.2.3 PREDICTED
AND MEASURED VALUES 111 3.8.2.4 SUMMARY OF TRENDS 113 3.8.2.5 UNIVERSAL
G M /I D CHARACTERISTIC IN CMOS TECHNOLOGIES 115 3.8.2.6 DISTORTION 115
3.8.3 BODY-EFFECT TRANSCONDUCTANCE AND RELATIONSHIP TO SUBSTRATE FACTOR
121 3.8.3.1 SUBSTRATE FACTOR 122 3.8.3.2 BODY-EFFECT TRANSCONDUCTANCE
125 3.8.3.3 PREDICTED AND MEASURED VALUES 126 3.8.3.4 SUMMARY OF TRENDS
129 3.8.4 DRAIN CONDUCTANCE 130 ^3.8.4.1 DUE TO CHANNEL LENGTH
MODULATION 131 3.8.4.2 DUETODIBL 141 3.8.4.3 DUE TO HOT-ELECTRON EFFECTS
146 3.8.4.4 IMPACT OF INCREASE NEAR V DSSAL 150 3.8.4.5 MEASURED VALUES
152 3.8.4.6 SUMMARY OF TRENDS 161 3.8.5 INTRINSIC VOLTAGE GAIN 163 3.9
CAPACITANCES AND BANDWIDTH 169 3.9.1 GATE-OXIDE CAPACITANCE 169 3.9.2
INTRINSIC GATE CAPACITANCES 170 3.9.3 EXTRINSIC GATE-OVERLAP
CAPACITANCES 173 3.9.4 DRAIN-BODY AND SOURCE-BODY JUNCTION CAPACITANCES
176 3.9.5 INTRINSIC DRAIN-BODY AND SOURCE-BODY CAPACITANCES 179 3.9.6
INTRINSIC BANDWIDTH 179 3.9.7 EXTRINSIC AND DIODE-CONNECTED BANDWIDTHS
185 3.10 NOISE 188 3.10.1 THERMAL NOISE IN THE OHMIC REGION 189 3.10.2
THERMAL NOISE IN THE SATURATION REGION 190 3.10.2.1 WITHOUT
SMALL-GEOMETRY EFFECTS 190 3.10.2.2 WITH SMALL-GEOMETRY EFFECTS 193
3.10.2.3 SUMMARY OF DRAIN-REFERRED AND GATE-REFERRED THERMAL NOISE 194
3.10.3 FLICKER NOISE 200 3.10.3.1 CARRIER DENSITY FLUCTUATION MODEL 201
3.10.3.2 CARRIER MOBILITY FLUCTUATION MODEL 203 3.10.3.3 UNIFIED,
CARRIER DENSITY, CORRELATED MOBILITY FLUCTUATION MODEL 204 3.10.3.4
FLICKER-NOISE PREDICTION FROM FLICKER-NOISE FACTORS 207 3.10.3.5
REPORTED FLICKER-NOISE FACTORS AND TRENDS 209 3.10.3.6 MEASURED AND
PREDICTED FLICKER NOISE 212 3.10.3.7 SUMMARY OF GATE-REFERRED AND
DRAIN-REFERRED FLICKER NOISE 217 3.10.3.8 FLICKER-NOISE CORNER FREQUENCY
224 3.10.4 GATE, SUBSTRATE, AND SOURCE RESISTANCE THERMAL NOISE 227
3.10.5 CHANNEL AVALANCHE NOISE 229 3.10.6 INDUCED GATE NOISE CURRENT 229
3.10.7 GATE LEAKAGE NOISE CURRENT 231 CONTENTS 3.11 MISMATCH 233 3.11.1
LOCAL-AREA DC MISMATCH 233 3.11.1.1 MODELING 233 3.11.1.2 REPORTED
MISMATCH FACTORS AND TRENDS 237 3.11.1.3 EDGE EFFECTS AND OTHER MODEL
LIMITATIONS 239 3.11.1.4 CALCULATING GATE-SOURCE VOLTAGE AND DRAIN
CURRENT MISMATCH 241 3.11.1.5 THRESHOLD-VOLTAGE MISMATCH INCREASE FOR
NON-ZERO V SB 244 3.11.1.6 THRESHOLD-VOLTAGE DOMINANCE OF MISMATCH 246
3.11.1.7 SUMMARY OF GATE-SOURCE VOLTAGE AND DRAIN CURRENT MISMATCH 247
3.11.2 DISTANCE DC MISMATCH 254 3.11.2.1 MODELING 254 3.11.2.2 REPORTED
MISMATCH FACTORS AND TRENDS 255 3.11.2.3 GATE-SOURCE VOLTAGE AND DRAIN
CURRENT MISMATCH 256 3.11.2.4 THRESHOLD-VOLTAGE DOMINANCE OF MISMATCH
258 3.11.2.5 CRITICAL SPACING FOR COMPARABLE DISTANCE AND LOCAL-AREA
MISMATCH 258 3.11.3 DC MISMATCH EFFECTS ON CIRCUIT PERFORMANCE 259
3.11.3.1 BANDWIDTH, POWER, AND ACCURACY TRADEOFFS IN CURRENT-MODE
CIRCUITS 259 3.11.3.2 BANDWIDTH, POWER, AND ACCURACY TRADEOFFS IN
VOLTAGE-MODE CIRCUITS 262 3.11.3.3 TIRNING SKEW IN DIGITAL CIRCUITS 264
3.11.4 SMALL-SIGNAL PARAMETER AND CAPACITANCE MISMATCH 265 3.11.4.1
TRANSCONDUCTANCE MISMATCH 265 3.11.4.2 DRAIN-SOURCE CONDUCTANCE MISMATCH
267 3.11.4.3 MISMATCH EFFECTS ON CIRCUIT PERFORMANCE 268 3.12 LEAKAGE
CURRENT 268 3.12.1 GATE LEAKAGE CURRENT AND CONDUCTANCE 268 3.12.1.1
GATE CURRENT 269 3.12.1.2 GATE CONDUCTANCE - 273 3.12.2 GATE LEAKAGE
CURRENT EFFECTS ON CIRCUIT PERFORMANCE 274 3.12.2.1 MINIMUM FREQUENCY OF
OPERATION 274 3.12.2.2 INTRINSIC CURRENT GAIN 275 3.12.2.3 DISCHARGE OF
CAPACITANCES 276 3.12.2.4 NOISE 277 3.12.2.5 MISMATCH 277 3.12.2.6
SUMMARY OF TRADEOFFS 278 3.12.3 DRAIN-BODY AND SOURCE-BODY LEAKAGE
CURRENT 279 3.12.4 SUBTHRESHOLD DRAIN LEAKAGE CURRENT 282 REFERENCES 283
TRADEOFFS IN MOS PERFORMANCE, AND DESIGN OF DIFFERENTIAL PAIRS AND
CURRENT MIRRORS 295 4.1 INTRODUCTION 295 4.2 PERFORMANCE TRENDS 296
4.2.1 EXPLORING DRAIN CURRENT, INVERSION COEFFICIENT, AND CHANNEL LENGTH
SEPARATELY 296 4.2.2 TRENDS AS INVERSION COEFFICIENT INCREASES 297 4.2.3
TRENDS AS CHANNEL LENGTH INCREASES 300 4.2.4 TRENDS AS DRAIN CURRENT
INCREASES 302 4.3 PERFORMANCE TRADEOFFS 303 4.3.1 OVERVIEW - THE MOSFET
OPERATING PLANE 303 4.3.2 REGION AND LEVEL OF INVERSION - THE INVERSION
COEFFICIENT AS A NUMBER LINE 304 CONTENTS XI 4.3.3 TRADEOFFS COMMON TO
ALL DEVICES 306 4.3.3.1 CHANNEL WIDTH AND GATE AREA 309 4.3.3.2
INTRINSIC GATE CAPACITANCE AND DRAIN-BODY CAPACITANCE 310 4.3.3.3
EFFECTIVE GATE-SOURCE VOLTAGE AND DRAIN-SOURCE SATURATION VOLTAGE 312
4.3.3.4 TRANSCONDUCTANCE EFFICIENCY AND EARLY VOLTAGE 314 4.3.3.5
INTRINSIC VOLTAGE GAIN AND BANDWIDTH 317 4.3.4 TRADEOFFS SPECIFIC TO
DIFFERENTIAL-PAIR DEVICES 320 4.3.4.1 TRANSCONDUCTANCE DISTORTION 320
4.3.4.2 INTRINSIC GATE CAPACITANCE AND GATE-REFERRED THERMAL-NOISE
VOLTAGE 323 4.3.4.3 GATE-REFERRED FLICKER-NOISE VOLTAGE AND GATE-SOURCE
MISMATCH VOLTAGE 325 4.3.5 TRADEOFFS SPECIFIC TO CURRENT-MIRROR DEVICES
328 4.3.5.1 INTRINSIC BANDWIDTH AND DRAIN-REFERRED THERMAL-NOISE CURRENT
329 4.3.5.2 DRAIN-REFERRED FLICKER-NOISE CURRENT AND DRAIN MISMATCH
CURRENT 333 4.3.6 TRADEOFFS IN FIGURES OF MERIT 336 4.3.6.1
TRANSCONDUCTANCE EFFICIENCY AND EARLY VOLTAGE 338 4.3.6.2 INTRINSIC
VOLTAGE GAIN, BANDWIDTH, AND GAIN-BANDWIDTH 338 4.3.6.3 TRANSCONDUCTANCE
EFFICIENCY AND INTRINSIC BANDWIDTH 339 4.3.6.4 THERMAL-NOISE EFFICIENCY
AND FLICKER-NOISE AREA EFFICIENCY 340 4.3.6.5 BANDWIDTH, POWER, AND
ACCURACY WITH DC OFFSET 340 4.3.6.6 BANDWIDTH, POWER, AND ACCURACY WITH
THERMAL NOISE 342 4.3.6.7 COMPARISON OF BANDWIDTH, POWER, AND ACCURACY
FOR DC OFFSET AND THERMAL NOISE 345 4.3.6.8 EXTENSIONS 345 4.4 DESIGN OF
DIFFERENTIAL PAIRS AND CURRENT MINORS USING THE ANALOG CMOS DESIGN,
TRADEOFFS AND OPTIMIZATION SPREADSHEET 346 4.4.1 SELECTING INVERSION
COEFFICIENT 348 4.4.2 SELECTING CHANNEL LENGTH 353 4.4.3 SELECTING DRAIN
CUNENT 359 4.4.4 OPTIMIZING FOR DC, BALANCED, AND AC PERFORMANCE 363
4.4.4.1 DC OPTIMIZATION 364 4.4.4.2 AC OPTIMIZATION 366 4.4.4.3 BALANCED
OPTIMIZATION 366 4.4.4.4 OPTIMIZATIONS AT MILLIPOWER OPERATION 367
4.4.4.5 OPTIMIZATIONS AT MICROPOWER OPERATION 369 4.4.4.6 SUMMARY OF
MICROPOWER PERFORMANCE CONSIDERATIONS 372 4.4.5 SUMMARY PROCEDURE FOR
DEVICE OPTIMIZATION 372 REFERENCES 373 PART II CIRCUIT DESIGN EXAMPLES
ILLUSTRATING OPTIMIZATION FOR ANALOG CMOS DESIGN 375 5 DESIGN OF CMOS
OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS OPTIMIZED FOR DC, BALANCED, AND
AC PERFORMANCE 377 5.1 INTRODUCTION 377 5.2 CIRCUIT DESCRIPTION 379
5.2.1 SIMPLE OTAS 379 5.2.2 CASCODED OTAS 380 5.3 CIRCUIT ANALYSIS AND
PERFORMANCE OPTIMIZATION 382 5.3.1 TRANSCONDUCTANCE 383 5.3.1.1 SIMPLE
OTAS 383 5.3.1.2 CASCODED OTAS 384 XUE CONTENTS 5.3.1.3 OPTIMIZATION 384
5.3.2 OUTPUT RESISTANCE 385 5.3.2.1 SIMPLE OTAS 385 5.3.2.2 CASCODEDOTAS
385 5.3.2.3 OPTIMIZATION 387 5.3.3 VOLTAGE GAIN 387 5.3.3.1 SIMPLE OTAS
387 5.3.3.2 CASCODED OTAS 388 5.3.3.3 OPTIMIZATION 388 5.3.4 FREQUENCY
RESPONSE 389 5.3.4.1 SIMPLE OTAS 389 5.3.4.2 CASCODEDOTAS 391 5.3.4.3
OPTIMIZATION 392 5.3.5 THERMAL NOISE 393 5.3.5.1 SIMPLE OTAS 393 5.3.5.2
CASCODED OTAS 394 5.3.5.3 OPTIMIZATION 396 5.3.6 FLICKER NOISE 397
5.3.6.1 SIMPLE OTAS 397 5.3.6.2 CASCODEDOTAS 399 5.3.6.3 OPTIMIZATION
400 5.3.7 OFFSET VOLTAGE DUE TO LOCAL-AREA MISMATCH 403 5.3.7.1 SIMPLE
OTAS 403 5.3.7.2 CASCODED OTAS 407 5.3.7.3 OPTIMIZATION 409 5.3.8
SYSTEMATIC OFFSET VOLTAGE FOR SIMPLE OTAS 412 5.3.9 INPUT AND OUTPUT
CAPACITANCES 413 5.3.9.1 SIMPLE OTAS 413 5.3.9.2 CASCODEDOTAS 415
5.3.9.3 OPTIMIZATION 416 5.3.10 SLEW RATE 417 5.3.10.1 SIMPLE OTAS 417
5.3.10.2 CASCODED OTAS 417 5.3.10.3 OPTIMIZATION 417 5.3.11 INPUT AND
OUTPUT VOLTAGE RANGES 417 5.3.11.1 SIMPLE OTAS 417 5.3.11.2 CASCODEDOTAS
419 5.3.11.3 OPTIMIZATION 421 5.3.12 INPUT, 1 DB COMPRESSION VOLTAGE 423
5.3.12.1 SIMPLE OTAS 423 5.3.12.2 CASCODEDOTAS 423 5.3.12.3 OPTIMIZATION
424 5.3.13 MANAGEMENT OF SMALL-GEOMETRY EFFECTS 424 5.4 DESIGN
OPTIMIZATION AND RESULTING PERFORMANCE FOR THE SIMPLE OTAS 425 5.4.1
SELECTION OF MOSFET INVERSION COEFFICIENTS AND CHANNEL LENGTHS 425
5.4.1.1 DC OPTIMIZATION 429 5.4.1.2 AC OPTIMIZATION 430 5.4.1.3 BALANCED
OPTIMIZATION 431 5.4.2 PREDICTED AND MEASURED PERFORMANCE 431 5.4.2.1
TRANSCONDUCTANCE, OUTPUT RESISTANCE, AND VOLTAGE GAIN 435 5.4.2.2
FREQUENCY RESPONSE 439 CONTENTS XIII 5.4.2.3 THERMAL NOISE 439 5.4.2.4
FLICKER NOISE 440 5.4.2.5 OFFSET VOLTAGE DUE TO LOCAL-AREA MISMATCH 441
5.4.2.6 SYSTEMATIC OFFSET VOLTAGE 442 5.4.2.7 INPUT AND OUTPUT
CAPACITANCES 442 5.4.2.8 SLEWRATE 442 5.4.2.9 INPUT AND OUTPUT VOLTAGE
RANGES 443 5.4.2.10 INPUT, LDB COMPRESSION VOLTAGE 443 5.4.2.11 LAYOUT
AREA 444 5.4.2.12 TRADEOFFS IN DC ACCURACY, LOW-FREQUENCY AC ACCURACY,
VOLTAGE GAIN, AND TRANSCONDUCTANCE BANDWIDTH 446 5.4.3 OTHER
OPTIMIZATIONS: ENSURING INPUT DEVICES DOMINATE THERMAL NOISE 447 5.5
DESIGN OPTIMIZATION AND RESULTING PERFORMANCE FOR THE CASCODED OTAS 448
5.5.1 SELECTION OF MOSFET INVERSION COEFFICIENTS AND CHANNEL LENGTHS 448
5.5.1.1 DC OPTIMIZATION 451 5.5.1.2 AC OPTIMIZATION 452 5.5.1.3 B
ALANCED OPTIMIZATION 453 5.5.2 PREDICTED AND MEASURED PERFORMANCE 453
5.5.2.1 TRANSCONDUCTANCE, OUTPUT RESISTANCE, AND VOLTAGE GAIN 458
5.5.2.2 FREQUENCY RESPONSE 461 5.5.2.3 THERMAL NOISE 462 5.5.2.4 FLICKER
NOISE 463 5.5.2.5 OFFSET VOLTAGE DUE TO LOCAL-AREA MISMATCH 464 5.5.2.6
INPUT AND OUTPUT CAPACITANCES 466 5.5.2.7 SLEW RATE 467 5.5.2.8 INPUT
AND OUTPUT VOLTAGE RANGES 467 5.5.2.9 INPUT, 1 DB COMPRESSION VOLTAGE
468 5.5.2.10 LAYOUT AREA 468 5.5.2.11 TRADEOFFS IN DC ACCURACY,
LOW-FREQUENCY AC ACCURACY, VOLTAGE GAIN, AND TRANSCONDUCTANCE BANDWIDTH
470 5.5.2.12 COMPARISON OF PERFORMANCE TRADEOFFS WITH THOSE OF SIMPLE
OTAS 472 5.5.3 OTHER OPTIMIZATIONS: ENSURING INPUT DEVICES DOMINATE
FLICKER NOISE AND LOCAL-AREA MISMATCH 472 5.5.4 OTHER OPTIMIZATIONS:
COMPLEMENTING THE DESIGN 473 5.6 PREDICTION ACCURACY FOR DESIGN GUIDANCE
AND OPTIMIZATION 474 REFERENCES 476 DESIGN OF MICROPOWER CMOS
PREAMPLIFIERS OPTIMIZED FOR LOW THERMAL AND FLICKER NOISE 477 6.1
INTRODUCTION 477 6.2 USING THE LATERAL BIPOLAR TRANSISTOR FOR
LOW-FLICKER-NOISE APPLICATIONS 478 6.3 MEASURES OF PREAMPLIFIER NOISE
PERFORMANCE 479 6.3.1 THERMAL-NOISE EFFICIENCY FACTOR 479 6.3.2
FLICKER-NOISE AREA EFFICIENCY FACTOR 482 6.4 REPORTED MICROPOWER,
LOW-NOISE CMOS PREAMPLIFIERS 483 6.5 MOS NOISE VERSUS THE BIAS
COMPLIANCE VOLTAGE 486 6.5.1 TRANSCONDUCTANCE IN SATURATION 486 6.5.2
DRAIN-SOURCE RESISTANCE AND TRANSCONDUCTANCE IN THE DEEP OHMIC REGION
489 6.5.3 GATE NOISE VOLTAGE 491 6.5.3.1 THERMAL NOISE 491 6.5.3.2
FLICKER NOISE 493 XIV CONTENTS 6.5.4 DRAIN NOISE CURRENT 494 6.5.4.1
THERMAL NOISE 494 6.5.4.2 FLICKER NOISE 494 6.5.5 DRAIN NOISE CURRENT
WITH RESISTIVE SOURCE DEGENERATION 496 6.5.5.1 BIAS COMPLIANCE VOLTAGE
496 6.5.5.2 THERMAL NOISE 497 6.5.5.3 FLICKER NOISE 500 6.6 EXTRACTION
OF MOS FLICKER-NOISE PARAMETERS 504 6.6.1 PREAMPLIFIER INPUT DEVICES 504
6.6.2 PREAMPLIFIER NON-INPUT DEVICES 506 6.6.3 COMPARISONS OF RICKER
NOISE 507 6.7 DIFFERENTIAL INPUT PREAMPLIFIER 507 6.7.1 DESCRIPTION 507
6.7.2 CIRCUIT ANALYSIS, PERFORMANCE OPTIMIZATION, AND PREDICTED
PERFORMANCE 509 6.7.2.1 VOLTAGE GAIN 510 6.7.2.2 FREQUENCY RESPONSE 511
6.7.2.3 THERMAL NOISE 511 6.7.2.4 THERMAL NOISE EXPRESSED FROM DC BIAS
CONDITIONS 512 6.7.2.5 FLICKER NOISE 516 6.7.2.6 FLICKER NOISE EXPRESSED
FROM DC BIAS CONDITIONS 517 6.7.3 SUMMARY OF PREDICTED AND MEASURED
PERFORMANCE 520 6.7.3.1 MOSFET DESIGN SELECTIONS 521 6.7.3.2 RESULTING
PREAMPLIFIER PERFORMANCE 525 6.7.4 DESIGN IMPROVEMENTS 529 6.8
SINGLE-ENDED INPUT PREAMPLIFIER 531 6.8.1 DESCRIPTION 531 6.8.2 CIRCUIT
ANALYSIS, PERFORMANCE OPTIMIZATION, AND PREDICTED PERFORMANCE 532
6.8.2.1 VOLTAGE GAIN 533 6.8.2.2 FREQUENCY RESPONSE 534 6.8.2.3 THERMAL
NOISE 535 6.8.2.4 THERMAL NOISE EXPRESSED FROM DC BIAS CONDITIONS 536
6.8.2.5 FLICKER NOISE 538 6.8.2.6 FLICKER NOISE EXPRESSED FROM DC BIAS
CONDITIONS 539 6.8.3 SUMMARY OF PREDICTED AND MEASURED PERFORMANCE 541
6.8.3.1 MOSFET DESIGN SELECTIONS 541 6.8.3.2 RESULTING PREAMPLIFIER
PERFORMANCE 543 6.8.4 DESIGN IMPROVEMENTS 547 6.9 PREDICTION ACCURACY
FOR DESIGN GUIDANCE AND OPTIMIZATION 549 6.10 SUMMARY OF LOW-NOISE
DESIGN METHODS AND RESULTING CHALLENGES IN LOW-VOLTAGE PROCESSES 550
REFERENCES 552 EXTENDING OPTIMIZATION METHODS TO SMALLER-GEOMETRY CMOS
PROCESSES AND FUTURE TECHNOLOGIES 555 7.1 INTRODUCTION 555 7.2 USING THE
INVERSION COEFFICIENT FOR CMOS PROCESS INDEPENDENCE AND FOR EXTENSION TO
SMALLER-GEOMETRY PROCESSES 556 7.2.1 UNIVERSAL G M /I D , V EFF , AND V
DSSAL CHARACTERISTICS ACROSS CMOS PROCESSES 556 CONTENTS 7.2.2 OTHER
NEARLY UNIVERSAL PERFORMANCE CHARACTERISTICS ACROSS CMOS PROCESSES 556
7.2.3 PORTING DESIGNS ACROSS CMOS PROCESSES 557 7.2.4 EXTENDING DESIGN
METHODS TO SMALLER-GEOMETRY PROCESSES 560 7.3 ENHANCING OPTIMIZATION
METHODS BY INCLUDING GATE LEAKAGE CURRENT EFFECTS 560 7.4 USING AN
INVERSION COEFFICIENT MEASURE FOR NON-CMOS TECHNOLOGIES 561 REFERENCES
562 APPENDIX: THE ANALOG CMOS DESIGN, TRADEOFFS AND OPTIMIZATION
SPREADSHEET 565 INDEX 583 |
| any_adam_object | 1 |
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| author | Binkley, David M. |
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| callnumber-search | TK7871.99.M44 |
| callnumber-sort | TK 47871.99 M44 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4960 |
| ctrlnum | (OCoLC)171152288 (DE-599)OBVAC06826433 |
| dewey-full | 621.3815/2 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815/2 |
| dewey-search | 621.3815/2 |
| dewey-sort | 3621.3815 12 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| discipline_str_mv | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV035014250 |
| illustrated | Illustrated |
| index_date | 2024-07-02T21:44:52Z |
| indexdate | 2024-07-09T21:20:13Z |
| institution | BVB |
| isbn | 9780470031360 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-016683444 |
| oclc_num | 171152288 |
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| owner_facet | DE-1043 DE-634 DE-859 DE-83 |
| physical | XXXV, 594 S. graph. Darst. |
| publishDate | 2008 |
| publishDateSearch | 2008 |
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| publisher | Wiley |
| record_format | marc |
| spelling | Binkley, David M. Verfasser aut Tradeoffs and optimization in analog CMOS design David M. Binkley Chichester Wiley 2008 XXXV, 594 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Literaturverz. S. 562 - 563 "Analog CMOS (complementary metal-oxide-semiconductor) integrated circuits are in widespread use for communications, entertainment, multimedia, biomedical, and many other applications that interface with the physical world. Although analog CMOS design is greatly complicated by the design choices of drain current, channel width, and channel length present for every MOS device in a circuit, these design choices afford significant opportunities for optimizing circuit performance." "This book addresses tradeoffs and optimization of device and circuit performance for selections of the drain current, inversion coefficient, and channel length, where channel width is implicitly considered. The inversion coefficient is used as a technology independent measure of MOS inversion that permits design freely in weak, moderate, and strong inversion."--BOOK JACKET. Circuits électroniques - Calcul ram MOS complémentaires ram Metal oxide semiconductors, Complementary Design and construction CMOS-Schaltung (DE-588)4148111-2 gnd rswk-swf Analoge integrierte Schaltung (DE-588)4112519-8 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Analoge integrierte Schaltung (DE-588)4112519-8 s CMOS-Schaltung (DE-588)4148111-2 s Schaltungsentwurf (DE-588)4179389-4 s DE-604 GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016683444&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Binkley, David M. Tradeoffs and optimization in analog CMOS design Circuits électroniques - Calcul ram MOS complémentaires ram Metal oxide semiconductors, Complementary Design and construction CMOS-Schaltung (DE-588)4148111-2 gnd Analoge integrierte Schaltung (DE-588)4112519-8 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| subject_GND | (DE-588)4148111-2 (DE-588)4112519-8 (DE-588)4179389-4 |
| title | Tradeoffs and optimization in analog CMOS design |
| title_auth | Tradeoffs and optimization in analog CMOS design |
| title_exact_search | Tradeoffs and optimization in analog CMOS design |
| title_exact_search_txtP | Tradeoffs and optimization in analog CMOS design |
| title_full | Tradeoffs and optimization in analog CMOS design David M. Binkley |
| title_fullStr | Tradeoffs and optimization in analog CMOS design David M. Binkley |
| title_full_unstemmed | Tradeoffs and optimization in analog CMOS design David M. Binkley |
| title_short | Tradeoffs and optimization in analog CMOS design |
| title_sort | tradeoffs and optimization in analog cmos design |
| topic | Circuits électroniques - Calcul ram MOS complémentaires ram Metal oxide semiconductors, Complementary Design and construction CMOS-Schaltung (DE-588)4148111-2 gnd Analoge integrierte Schaltung (DE-588)4112519-8 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| topic_facet | Circuits électroniques - Calcul MOS complémentaires Metal oxide semiconductors, Complementary Design and construction CMOS-Schaltung Analoge integrierte Schaltung Schaltungsentwurf |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=016683444&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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