Chip-level Modeling with VHDL:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | Undetermined |
| Veröffentlicht: |
Englewood Cliffs, NJ
Prentice Hall
1989
|
| Schriftenreihe: | Prentice Hall series in computer engineering
|
| Schlagworte: | |
| Beschreibung: | X, 148 S. |
| ISBN: | 0131331906 |
Internformat
MARC
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| 100 | 1 | |a Armstrong, James R. |e Verfasser |4 aut | |
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Datensatz im Suchindex
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|---|---|
| any_adam_object | |
| author | Armstrong, James R. |
| author_facet | Armstrong, James R. |
| author_role | aut |
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| bvnumber | BV024664334 |
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| ctrlnum | (OCoLC)263668284 (DE-599)BVBBV024664334 |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV024664334 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-09T21:54:14Z |
| institution | BVB |
| isbn | 0131331906 |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-018075383 |
| oclc_num | 263668284 |
| open_access_boolean | |
| owner | DE-83 |
| owner_facet | DE-83 |
| physical | X, 148 S. |
| psigel | TUB-nve |
| publishDate | 1989 |
| publishDateSearch | 1989 |
| publishDateSort | 1989 |
| publisher | Prentice Hall |
| record_format | marc |
| series2 | Prentice Hall series in computer engineering |
| spelling | Armstrong, James R. Verfasser aut Chip-level Modeling with VHDL James R. Armstrong Englewood Cliffs, NJ Prentice Hall 1989 X, 148 S. txt rdacontent n rdamedia nc rdacarrier Prentice Hall series in computer engineering VLSI (DE-588)4117388-0 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf VLSI (DE-588)4117388-0 s Schaltungsentwurf (DE-588)4179389-4 s VHDL (DE-588)4254792-1 s DE-604 |
| spellingShingle | Armstrong, James R. Chip-level Modeling with VHDL VLSI (DE-588)4117388-0 gnd VHDL (DE-588)4254792-1 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4254792-1 (DE-588)4179389-4 |
| title | Chip-level Modeling with VHDL |
| title_auth | Chip-level Modeling with VHDL |
| title_exact_search | Chip-level Modeling with VHDL |
| title_full | Chip-level Modeling with VHDL James R. Armstrong |
| title_fullStr | Chip-level Modeling with VHDL James R. Armstrong |
| title_full_unstemmed | Chip-level Modeling with VHDL James R. Armstrong |
| title_short | Chip-level Modeling with VHDL |
| title_sort | chip level modeling with vhdl |
| topic | VLSI (DE-588)4117388-0 gnd VHDL (DE-588)4254792-1 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| topic_facet | VLSI VHDL Schaltungsentwurf |
| work_keys_str_mv | AT armstrongjamesr chiplevelmodelingwithvhdl |